CN101706760B - Matrix transposition automatic control circuit system and matrix transposition method - Google Patents
Matrix transposition automatic control circuit system and matrix transposition method Download PDFInfo
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Abstract
The invention discloses a matrix transposition automatic control circuit system and a matrix transposition method. The circuit system comprises a configuration register, a control register, a transposition module and a status register, wherein the configuration register is used to receive the input data and transfer the configuration information to the transposition module; the control register is used to receive the input data and control the read and write requests sent by the transposition module; the transposition module is used to receive the information of the configuration register and the control register and complete the transposition operation of matrix according to the information; and the status register is used to store the ending signal of the transposition operation of matrix and return the ending signal. The circuit system and the matrix transposition method can be used to increase the utilization of the cache block and the data bus so as to increase the efficiency of transposition.
Description
Technical field
The present invention relates to field of computer technology, particularly relate to a kind of matrix transposition automatic control circuit system and matrix transpose method.
Background technology
Matrix is a kind of data structure that people know in the computing machine, and it is the popularization of linear list.In current computer utility, in fields such as science and engineering calculation, recreation, Flame Image Process, all need to use the transpose of a matrix computing.
In the prior art, because each access memory needs long time, if only reading the data of a byte of source matrix from internal memory is put in high-speed cache (cache) piece then at every turn, not only can waste valuable data bus bandwidth, also can cause the wasting of resources of other byte in the cacheline, and increase the reading duration.When writing internal memory, the write operation of data also can bring similar problem one by one.
Summary of the invention
The object of the present invention is to provide a kind of matrix transposition automatic control circuit system and matrix transpose method, it overcomes defective of the prior art, improves the utilization factor of high-speed cache (cache) piece and data bus, thereby improves the efficient of transposition.
A kind of matrix transposition automatic control circuit system for realizing that the object of the invention provides comprises cacheline, and second level cache and processor core also comprise configuration register, control register and transposition module, wherein:
Described configuration register is used for receiving the input data, and configuration information is passed to described transposition module;
Described control register is used for receiving the input data, and described transposition module is sent the read-write requests control information;
Described transposition module is used to receive the information of described configuration register, control register, then according to these information, finishes the transpose of a matrix operation, comprises to the read operation of source matrix with to the write operation of purpose matrix.Wherein, described read operation is the read request of sending continuously, and it determines the quantity of each read request of sending continuously according to capacity of cacheline.
In order to guarantee the IO consistance, the transposition module has increased the consistance command channel between second level cache (cache) and processor core and consistance is replied passage.
More preferably, described matrix transposition automatic control circuit system also comprises status register, is used to preserve the end signal of matrix transpose operation, and described end signal is returned;
For realizing the object of the invention, a kind of matrix transpose method also is provided, comprise the following steps:
Steps A when control register allows the peek operation, is sent a plurality of read requests according to the address information that configuration register provides to the source matrix; The address of described read request is discontinuous address; The number of described read request is by the capacity decision of cacheline;
Step B receives the data that a plurality of read requests are returned, and deposits these data in buffer zone;
Step C when the whole buffer memorys of all data of read request finish and control register when allowing write operation, sends the consistance command request;
Step D receives the consistance that second level cache (cache) returns and replys;
Step e is sent write data requests satisfying under the conforming prerequisite of IO;
Step F is taken out data from buffer zone, it is write objective matrix address space;
Step G, the response message of reception write data requests.
Repeat above-mentioned 7 steps, up to finishing source transpose of a matrix operation.
More preferably, described matrix transpose method, described step B also comprises the following steps:
After receiving all data of source matrix with read operation end signal return state register;
And,
After step G, also comprise the following steps:
After all that receive objective matrix are replied with write operation end signal return state register.
Beneficial effect of the present invention: matrix transposition automatic control circuit system of the present invention and matrix transpose method, make full use of the capacity of high-speed cache (cache) piece, has very high resource utilization, improve the utilization factor of high-speed cache (cache) piece and data bus, thereby improve the efficient of transposition.Further, the present invention also supports the IO consistance when write data, can guarantee the buffer consistency between processor and the direct memory access controller (DMA).
Description of drawings
Fig. 1 is the Circuits System synoptic diagram that the matrix transpose of the embodiment of the invention is controlled automatically;
Fig. 2 is the configuration register course of work synoptic diagram of the embodiment of the invention;
Fig. 3 is the control register course of work synoptic diagram of the embodiment of the invention;
Fig. 4 is a control register each several part information synoptic diagram among Fig. 3;
Fig. 5 is the status register course of work synoptic diagram of the embodiment of the invention;
Fig. 6 is the matrix transpose method schematic flow sheet of the embodiment of the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, matrix transposition automatic control circuit system of the present invention and matrix transpose method are further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein is only in order to explain the present invention rather than limitation of the present invention.
As shown in Figure 1, the matrix transposition automatic control circuit system of the embodiment of the invention, the outside links to each other with address/data bus 6 with configuration bus 5.
Wherein, processor or DMA carry out read-write operation by each register of 5 pairs of control circuit system inside of configuration bus, control circuit system need to read the matrix of transposition by address/data bus 6 from internal memory, and by the matrix of address/data bus 6 after internal memory writes transposition.
The matrix transposition automatic control circuit system of the embodiment of the invention comprises configuration register 1, status register 2, and control register 3 and transposition module 4, wherein:
Described configuration register 1 is used for accepting the input data, and configuration informations such as start address and matrix ranks are passed to described transposition module 4;
Described status register 2 is used to preserve the end signal of matrix transpose operation, and described end signal is returned;
Described control register 3 is used for accepting the input data, and the read-write requests that described transposition module 4 is sent is controlled;
Described transposition module 4, be used to accept the information of described configuration register 1, status register 2, control register 3, then according to these information, finish the transpose of a matrix operation, comprise to the read operation of source matrix with to the write operation of purpose matrix, wherein, the quantity of the read request of at every turn sending continuously is by the capacity decision of cacheline.
As a kind of embodiment, the cacheline of matrix transposition automatic control circuit system of the present invention (cache) is 32 bytes, when control register allows the peek operation, send 32 read requests continuously at every turn, promptly read the minor matrix of one 32 byte x32 byte.
The matrix transposition automatic control circuit system of the embodiment of the invention, configuration register 1 is accepted the read-write requests that configuration bus 5 is sent here, and these configuration informations are passed to transposition module 4; Transposition module 4 is sent read request by address/data bus 6 to the source matrix according to these configuration informations then, after receiving the data that read request returns, and then sends write request by address/data bus 6 to objective matrix; After finishing read-write operation, transposition module 4 writes back status register 2 with end signal, and (Direct Memory Access, DMA) (not shown) is so that carry out the operation of matrix transpose next time to pass to processor core or direct memory access controller by configuration bus 5.
As a kind of embodiment, the transposition module 4 of the embodiment of the invention needs configuration register 1 that the configuration information relevant with the read-write requests address is provided, as shown in Figure 2, these configuration informations comprise the start address of source matrix 7 and objective matrix 8, the element number of the element number of source matrix delegation and row, and source matrix 7 and objective matrix 8 place large matrixs are the capable span of unit etc. with the byte.
As a kind of embodiment, the transposition module 4 of the embodiment of the invention also needs control register 3 that the control information of read-write requests is provided, and as shown in Figure 3, these control informations comprise input control and output control information etc.
As a kind of embodiment, in the control register 3 concrete each implication as shown in Figure 4, wherein:
Read-write enables to be used to control transposition module 4 and sends read-write requests; If only enable read request, 4 data with source matrix 7 of transposition module are read in the cacheline; If simultaneously write request also is enabled, 4 of transposition modules can be write the data in the high-speed cache in objective matrix 8 addresses that configuration register 1 provides;
Because 1 of configuration register provides the element number of every row and every row in the source matrix 7, so control register 3 also needs to provide the byte number of each element representation.As a kind of embodiment, with dibit (bit) expression, the element width of dibit has four kinds of values: 00,01,10,11, and wherein 00 this element of expression is represented 1 byte, and 01 represents 2 bytes, and 10 represent 4 bytes, and 11 represent 8 bytes.
Consider and the compatibility of other module that the control register 3 in the embodiment of the invention also provides a control bit, be used for control and whether carry out matrix transpose operation.
In order to control the frequency of sending read-write requests, control register 3 in the embodiment of the invention, also comprise the Flow Control position, be used to control the frequency of sending read-write requests, the periodicity at Flow Control position control transposition module 4 required interval of each request under the situation that can send read request or write request.
The transposition module 4 of the embodiment of the invention can write back status register 2 with the end signal of read-write operation after finishing matrix transpose operation, as shown in Figure 5, status register 2 is passed to processor or DMA with these information by configuration bus 5, tell their this matrix transposes to finish, so that send the operation of matrix transpose next time.
Preferably, in order to guarantee input and output (IO) consistance, transposition module 4 comprises that consistance command channel 41 and consistance reply passage 42, is positioned between second level cache (cache) and the processor core, wherein:
Described consistance command channel 41 is used for receiving all read request data, and control register 3 sends the consistance command request by the read data passage earlier when allowing write operations;
Described consistance is replied passage 42, is used to receive consistance and replys.
Transposition module 4 is just sent write data requests satisfying under the conforming prerequisite of input and output (IO).
The main modular of finishing the matrix transpose operation in the embodiment of the invention is a transposition module 4, and as a kind of embodiment, the structure of its core is the buffer zone buffer of a 1024x8 bit.
Describe the matrix transpose process of the matrix transposition automatic control circuit system of the embodiment of the invention below in detail, promptly the matrix transpose method of the embodiment of the invention as shown in Figure 6, comprises the following steps:
Step S100, when control register 3 allowed the peek operation, transposition module 4 was sent a plurality of read requests according to the address information that configuration register 1 provides to source matrix 7; The number of described read request is by the capacity decision of cacheline;
Consider continuous rdma read and discontinuous internal memory, and the discontinuous rdma read and write performance difference between the internal memory continuously write, as a kind of embodiment, the embodiment of the invention adopts discontinuous rdma read and writes internal memory continuously, and promptly the address of read request is discontinuous address.
Can store the data of 32 bytes at most based on each high-speed cache (cache) piece, therefore ideally each read request all needs the source matrix to return 256 data.Each like this data of coming of reading back can both be write full cacheline, and can not cause the bandwidth waste of data bus.
Equally, also will make full use of the capacity of cacheline when writing matrix, promptly a write operation also is data of writing 32 bytes, therefore needs to send continuously 32 times read request in embodiments of the present invention, and each request provides the data of a byte for write operation.But the address of each read request is discontinuous, and span is the capable span of source matrix 7 place large matrixs.
Like this, transposition module 4 is the minor matrix that is divided into a plurality of 32 byte x, 32 bytes when in fact source matrix 7 being carried out matrix transpose operation, and move these data to buffer zone, this also is that the size that buffering buffer is set in the embodiment of the invention is the reason of 1024x8 bit.
Step S200 receives the data that a plurality of read requests are returned, and deposits these data in buffer zone.
The data of coming write buffer zone with reading back in the internal memory.In order to realize writing internal memory continuously, the buffer area buffer address that data write not is continuous, but 32 byte datas of coming of reading back are discrete writes buffer stopper with each, and the interval of each byte is subjected to the influence of element width.In one embodiment, when the element width was 0, for id0, the buffer stopper that writes was No. 0, No. 32, No. 64, No. 96 ... buffer stopper; And the like.Local in embodiments of the present invention id has only 16, therefore behind the read data of receiving certain id, needs this id of mark, and read request just can be reused this id number like this, thereby can utilize 16 id to send read request 32 times.
In order to realize the buffer consistency between processor core and the direct memory access controller (DMA), this just need increase consistance command channel 41 between second level cache (cache) and processor core and consistance is replied passage 42, and these two passages are respectively by read data request passage and read data backward channel.
Step S300, after all data of receiving 32 byte x, 32 byte minor matrixs, and control register 3 is when allowing write operations, and 4 of transposition modules can be sent the consistance command request to objective matrix according to the address information of objective matrix 8 in the configuration register 1.
Because when this request of sending out, can calculate the address of writing objective matrix 8, may need just can return and reply accordingly through a lot of bats, so the embodiment of the invention is being sent information such as id number of preserving read request when reading Address requests, address, these information are removed when sending the write address request.
Because the embodiment of the invention adopts the mode of writing internal memory continuously, therefore, to each row write operation of matrix, the address increases progressively, have only the start address that just can jump to next line when arriving the end of every row, the capable span of this address and objective matrix 8 place large matrixs is closely related.
Step S400, read data backward channel return the reception consistance and reply, and they are relevant with high-speed cache (cache) consistance, comprise information such as awcache.
Step S500 is satisfying under the conforming prerequisite of IO, and transposition module 4 is sent the write address request according to sending out information such as the address of preserving when reading Address requests and id number to destination address.Wherein the data that can return from step S400 of control information obtain, and information such as address, id number then can obtain from the register information that step S300 preserves.
Step S600, the transposition module is taken out data from buffer zone, it is write objective matrix 8 address spaces.
As a kind of embodiment,, only need this moment order from buffering, to take out data, and it is write the continuation address space at objective matrix 8 places because step S200 has considered the continuity of write operation when depositing the data of source matrix 7.
Preferably, the matrix transpose method of the embodiment of the invention, described step S200 also comprises the following steps:
Step S210, after receiving all data of source matrix with read operation end signal return state register 2;
And, after step S700, also comprise the following steps:
Step S710, after all that receive objective matrix are replied with write operation end signal return state register 2.
Repeat above-mentioned 7 step S100～700, up to finishing source transpose of a matrix operation.
In one embodiment, it is 0X20000000 that source matrix 7 start addresses that register 1 provides are put in establishing, objective matrix 8 start addresses are 0X5,000 0000, the number of source matrix one row element is 0Xa0, the number of source matrix one column element is 0X40, the capable span of source matrix 7 place large matrixs is 0X400, and the capable span of objective matrix 8 place large matrixs is 0X600; Control register 3 is 0X1000100400fe3.After these register informations all passed to transposition module 4, the transpose of a matrix operation then began to have carried out.Transposition module 4 will be sent read request to address 0X2,000 0000, and then read address 0X2,000 0400, and the rest may be inferred, up to reading address 0X2,0c0 0000.Like this, it just reads in buffer zone with the data of 32 byte x, 32 bytes.After the data of last byte write buffer zone buffer, transposition module 4 can begin the matrix after destination address writes transposition.Because write internal memory is continuous, therefore the memory address that writes is 0X5,000 0000,0X5,000 0020,0X5,000 0040,0X5,000 0060,0X5,000 0080, arrive the end of line of objective matrix 8 this moment, and the next line start address that jumps to matrix begins write operation, and promptly 0X5,000 0600; The rest may be inferred, and up to having write last id, the data in the buffering have all been write objective matrix 8, and buffer zone buffer is empty.At this moment, transposed matrix can continue to read the minor matrix of next 32 byte x, 32 bytes in the matrix of source.After all data of source matrix 7 all read out and write in the internal memory at objective matrix 8 places, the end signal of status register 2 will be put, and processor or DMA just know that this matrix transpose operation finished like this.
The matrix transposition automatic control circuit system of the embodiment of the invention and matrix transpose method, make full use of the capacity of cacheline, each read-write operation all is the data at 32 bytes, has very high resource utilization, improve the utilization factor of cacheline and data bus, thereby improve the efficient of transposition.Further, the present invention also supports the IO consistance when write data, can guarantee the buffer consistency between processor and the DMA.
Should be noted that at last that obviously those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these revise and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification.
Claims (8)
1. a matrix transposition automatic control circuit system comprises cacheline, and second level cache and processor core is characterized in that, also comprises configuration register, control register and transposition module, wherein:
Described configuration register is used for receiving the input data, and configuration information is passed to described transposition module;
Described control register is used for receiving the input data, and described transposition module is sent the read-write requests control information;
Described transposition module is used to receive the information of described configuration register, control register, then according to these information, finishes the transpose of a matrix operation, comprises to the read operation of source matrix with to the write operation of purpose matrix; Wherein, described read operation is the read request of sending continuously, and it determines the quantity of each read request of sending continuously according to capacity of cacheline;
Described transposition module comprises that consistance command channel and consistance reply passage, and described consistance command channel and consistance are replied passage between second level cache and processor core, wherein:
Described consistance command channel is used for receiving all read request data, and control register sends the consistance command request by the read data passage earlier when allowing write operation;
Described consistance is replied passage, is used to receive consistance and replys.
2. matrix transposition automatic control circuit system according to claim 1 is characterized in that, also comprises status register, is used to preserve the end signal of matrix transpose operation, and described end signal is returned.
3. matrix transposition automatic control circuit system according to claim 1 and 2 is characterized in that, described Circuits System outside links to each other with address/data bus with configuration bus;
Described configuration bus is carried out read-write operation to configuration register, control register or the status register of described Circuits System inside;
Described Circuits System need to read the matrix of transposition by address/data bus to internal memory, and by the matrix of address/data bus after internal memory writes transposition.
4. matrix transposition automatic control circuit system according to claim 1 is characterized in that:
Described configuration information comprises the start address of source matrix and objective matrix, the element number of the element number of source matrix delegation and row, and source matrix and objective matrix are the capable span of unit with the byte;
Described control information comprises input control information and output control information.
5. a matrix transpose method is characterized in that, comprises the following steps:
Steps A when control register allows the peek operation, is sent a plurality of read requests according to the address information that configuration register provides to the source matrix; Wherein, described a plurality of read requests are read requests of sending continuously, and its capacity according to cacheline is determined the quantity of the described read request of sending continuously;
Step B receives the data that described a plurality of read request is returned, and deposits these data in buffer zone;
Step C, if receive all data of described a plurality of read requests, and control register sends write data requests when allowing write operation;
Step D takes out data from buffer zone, it is write objective matrix address space;
Wherein, described step C comprises the following steps:
Step C1 when the whole buffer memorys of all data of read request finish and control register when allowing write operation, sends the consistance command request by the read data passage earlier;
Step C2 receives the consistance that second level cache returns and replys;
Step C3 sends write data requests satisfying under the input and output coherence request.
6. matrix transpose method according to claim 5 is characterized in that described step B also comprises the following steps:
After receiving all data of source matrix with read operation end signal return state register;
And,
After step D, also comprise the following steps:
After all that receive objective matrix are replied with write operation end signal return state register.
7. according to claim 5 or 6 described matrix transpose methods, it is characterized in that, also comprise the following steps:
Repeating step A～D is up to finishing source transpose of a matrix operation.
8. matrix transpose method according to claim 7 is characterized in that, when the transpose of a matrix of described source is operated, described source matrix is divided into a plurality of minor matrix data, and described data transfer is arrived buffer zone;
In the described steps A, the described address information that provides according to configuration register is sent read request to the source matrix, comprise the following steps: that the address information that provides according to configuration register sends a plurality of read requests to the source matrix, and the address of described read request is discontinuous;
Among the described step D, the described data of taking out from buffer zone with its address space that writes the objective matrix place, comprise the following steps: to take out data from buffer zone, data are write the continuation address space at objective matrix place.
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| CN102508803A (en) * | 2011-12-02 | 2012-06-20 | 南京大学 | Matrix transposition memory controller |
| CN103389967B (en) * | 2013-08-21 | 2016-06-01 | 中国人民解放军国防科学技术大学 | The device and method of a kind of matrix transposition based on SRAM |
| CN103760525B (en) * | 2014-01-06 | 2017-01-11 | 合肥工业大学 | Completion type in-place matrix transposition method |
| CN106934863A (en) * | 2015-12-29 | 2017-07-07 | 龙芯中科技术有限公司 | Horizon culling method and device |
| US9952831B1 (en) | 2017-02-16 | 2018-04-24 | Google Llc | Transposing in a matrix-vector processor |
| CN109408117B (en) * | 2018-10-08 | 2021-01-26 | 京东方科技集团股份有限公司 | Matrix transposing device and method, and display device |
| CN113626081A (en) * | 2020-05-08 | 2021-11-09 | 安徽寒武纪信息科技有限公司 | Data processing method and device and related product |
| CN114328315A (en) * | 2021-11-22 | 2022-04-12 | 北京智芯微电子科技有限公司 | DMA-based data preprocessing method, DMA component and chip structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1442797A (en) * | 2002-03-06 | 2003-09-17 | 松下电器产业株式会社 | Data processing device and program |
| CN1532686A (en) * | 1999-07-26 | 2004-09-29 | ض� | Processor and method for using two group of memory for matrix processing by processor |
| CN1832035A (en) * | 2005-12-27 | 2006-09-13 | 中国科学院计算技术研究所 | DDR memory controller and matrix line access method for matrix transposition |
| CN101093474A (en) * | 2007-08-13 | 2007-12-26 | 北京天碁科技有限公司 | Method for implementing matrix transpose by using vector processor, and processing system |
-
2009
- 2009-10-20 CN CN 200910236075 patent/CN101706760B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1532686A (en) * | 1999-07-26 | 2004-09-29 | ض� | Processor and method for using two group of memory for matrix processing by processor |
| CN1442797A (en) * | 2002-03-06 | 2003-09-17 | 松下电器产业株式会社 | Data processing device and program |
| CN1832035A (en) * | 2005-12-27 | 2006-09-13 | 中国科学院计算技术研究所 | DDR memory controller and matrix line access method for matrix transposition |
| CN101093474A (en) * | 2007-08-13 | 2007-12-26 | 北京天碁科技有限公司 | Method for implementing matrix transpose by using vector processor, and processing system |
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