CN101515221A - Method, device and system for reading data - Google Patents

Method, device and system for reading data Download PDF

Info

Publication number
CN101515221A
CN101515221A CN 200910119499 CN200910119499A CN101515221A CN 101515221 A CN101515221 A CN 101515221A CN 200910119499 CN200910119499 CN 200910119499 CN 200910119499 A CN200910119499 A CN 200910119499A CN 101515221 A CN101515221 A CN 101515221A
Authority
CN
Grant status
Application
Patent type
Prior art keywords
read command
read
data
flash memory
reading
Prior art date
Application number
CN 200910119499
Other languages
Chinese (zh)
Inventor
周建华
Original Assignee
成都市华为赛门铁克科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from or digital output to record carriers, e.g. RAID, emulated record carriers, networked record carriers
    • G06F3/0601Dedicated interfaces to storage systems
    • G06F3/0602Dedicated interfaces to storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • G06F3/0611Improving I/O performance in relation to response time
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from or digital output to record carriers, e.g. RAID, emulated record carriers, networked record carriers
    • G06F3/0601Dedicated interfaces to storage systems
    • G06F3/0628Dedicated interfaces to storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659Command handling arrangements, e.g. command buffers, queues, command scheduling
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from or digital output to record carriers, e.g. RAID, emulated record carriers, networked record carriers
    • G06F3/0601Dedicated interfaces to storage systems
    • G06F3/0668Dedicated interfaces to storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0683Plurality of storage devices
    • G06F3/0685Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

The embodiment of the invention discloses a method, a device and a system for reading data, wherein, the data reading method comprises: sending a first read command to a first flash memory and reading the data pointed by the first read command after receiving the response of the first read command; sending a second read command to a second flash memory, after sending the first read command to the first flash memory and before reading the data pointed by the first read command; receiving the response of the second read command, and reading the data pointed by the second read command after reading the data pointed by the first read command. The method has the following benefits: the second read command can be sent in the time interval between sending the first read command and reading the data pointed by the first read command, thereby, the read latency can be multiplexed, and the read latency between two read data is avoided, the I/O channel utilization rate can be increased, the read speed can be raised.

Description

一种读数据的方法、装置和系统 A method of reading data, apparatus and system

技术领域 FIELD

本发明涉及存储技术领域,特别涉及一种读数据的方法、装置和系统。 The present invention relates to storage technology, and particularly relates to a method for reading data, apparatus and system. 背景技术 Background technique

与非门闪存(NAND Flash)是一种非易失性随机访问存储介质,其特点是断电后数据不消失,因此可以作为外部存储器使用。 NAND flash (NAND Flash) is a non-volatile random access storage medium, which is characterized by the data does not disappear after power failure, it can be used as an external memory. NAND Flash分为S 单层式储存单元(Single Level Cell, SLC )和多层式储存单元(Multi Level Cell, MLC)。 S is divided into single-level NAND Flash storage unit (Single Level Cell, SLC), and multi-layer storage unit (Multi Level Cell, MLC). SLC芯片中,每个存储单元只存放1比特(Bit)的数据,MLC芯片中,每个储存单元可以存放2Bit或更多Bit的数据。 SLC chip, each memory cell storing only one bit (Bit) of the data, the MLC chip, each memory cell can store data of Bit 2Bit or more.

对NAND Flash的操作最主要有读、写和删除。 The most important operation of the NAND Flash read, write and delete. NAND Flash的读、写或删除,都需要命令来指示,这些命令都是以比特(Byte)为单位发布;命令是不同于数据的,所以命令要有使能信号;基于NAND Flash只有一组数据总线,并且总线的幅度只有8位或16位,地址和数据要共用这一组数据总线, 所以就会有地址使能信号;另外,数据读写要有读写控制信号,所以会有读使能信号和写使能信号,NAND Flash的主要引脚及说明如表1所示: NAND Flash read, write or delete command is required to indicate, these commands are in bits (Byte) units issued; command is different from the data, so there must be a command enable signal; only one set of data based on NAND Flash bus, the bus and the amplitude of only 8-bit or 16-bit address and data to the common data bus of this group, so there will address enable signal; Further, write data must be read-write control signal, so there will be a read enable enable signal and a write enable signal, and the main pin of NAND Flash described in table 1:

表1 Table 1

<table>table see original document page 4</column></row> <table> <Table> table see original document page 4 </ column> </ row> <table>

NAND Flash器件通常由内部寄存器和存储矩阵组成,以一种NAND Flash器件为例:存储矩阵包含1024个块(Block),每个Block包含16页(Page ),每个Page包含512+16个比特(byte ),其中的16byte为专有数据;每种NAND Flash芯片的存储矩阵大小定义可以不同,上述NAND Flash以528个byte组成一个Page , 16个Page组成一个Block,由1024个Block 组成Flash存储器。 NAND Flash device usually consists of a matrix of internal registers and memory, in a NAND Flash device as an example: the memory matrix comprises 1024 blocks (Block), each Block comprising 16 pages (Page), each containing 512 Page 16 bits + (byte), wherein the 16byte proprietary data; defines the matrix size of each chip may be different NAND Flash, NAND Flash to the above-described composition of a byte Page 528, composed of a Page Block 16 th, consisting of 1024 Block Flash memory . 在每页中512bytes用于存储数据,16bytes用于存放纠错码(Error Correction Code, ECC )数据校验码。 512bytes per page for storing data, 16bytes for storing an error correction code (Error Correction Code, ECC) check code data.

由于NAND Flash地址、命令和数据的输入输出(Input/Output, I/O )通道是复用的,从NAND Flash中读取数据的过程为:先发送一个时钟周期的读命令i,然后发送五个时钟周期的读地址,然后发送一个时钟周期的读命令2,然后经过一段时间的潜伏期(tR),最后读出数据(data)。 Since the process input and output NAND Flash address, command and data (Input / Output, I / O) channels are multiplexed, the data read from the NAND Flash to: send a first clock cycle of the read command i, then transmitting five clock cycles of read address, and then sends a read command clock cycle 2, then after a latency period of time (tR), and finally the read data (data). 如图1所示, 为单片NAND Flash读取过程示意图,横向为时间轴,表示了R/B端口, I/O 端口, RE弁端口的信息发送状况,单片NAND Flash读速率=数据量/ (发命令时间tCMD +发地址时间tADDR +读潜伏期tR +读出数据时间tDATA ),以读时钟周期为30ns为例:SLC器件单片读速率=4224Bytes/ ( 7*30ns + 25 ms + 4224*30ns) =27.7MB/s; MLC器件单片读速率=4224Bytes/ ( 7*30ns + 60 ju s + 4224*30ns ) =22.5MB/s。 1, a monolithic NAND Flash reading process schematic, transverse axis, showing the R / B port, I / O port status information transmitting port RE Bian, monolithic NAND Flash amount of data read rate = / (time tCMD + commanding hair read address tADDR + latency time data is read time tR + tDATA), 30ns clock cycles to read an example: SLC monolithic device read rate = 4224Bytes / (7 * 30ns + 25 ms + 4224 * 30ns) = 27.7MB / s; MLC monolithic device read rate = 4224Bytes / (7 * 30ns + 60 ju s + 4224 * 30ns) = 22.5MB / s.

为了提高NAND Flash的读写速度,通常可以采用:现场可编程门阵列器件(Field Programmable Gates Array, FPGA)连接4个通道的NAND Flash 控制器,每个控制器控制完成4片NAND Flash的读写。 In order to improve read and write speed of NAND Flash, generally can be used: a field programmable gate array device (Field Programmable Gates Array, FPGA) connected to four channels NAND Flash controller, the controller controls to read and write each of NAND Flash 4 . 在读数据的时候4 片NAND Flash对I/O通道使用是串行的,即:第一片读数据完成之后,再读第二片数据;读完第二片数据后,再读第三片数据;读完第三片数据后, 再读第四片数据,依此类推。 When reading data to the NAND Flash four I / O channel is a serial use, namely: a first sheet after the completion of data reading, data read second sheet; data after reading the second sheet, third sheet data read ; the third sheet data reading, data read fourth sheet, and so on. 多片NAND Flash的读取流程,如图2所示, 横向为时间轴,从上到下依次表示,#端口, 1/0端口, RE弁端口的信息发送状况。 Multi-chip NAND Flash reading process, shown in Figure 2, is a transverse axis, from top to bottom, said port #, 1/0 port, status information transmitted RE Bian port. 假设FPGA使用高级技术附加装置(Advanced Technology Attachment, ATA)接口(外部接口速度最大为133MB/s)的数据输入速率为133MB/s,典型的SLC器件单通道读速率为27.7MB/s,如果四个通道一起读数据,则读速率为27.7MB/s*4=110MB/s;典型的MLC器件单通道读速率为22.5MB/s,如果四个通道一起读数据,则读速率为22.5MB/s*4=90MB/s。 Suppose FPGA using Advanced Technology Attachment (Advanced Technology Attachment, ATA) interface (external interface speed up to 133MB / s) Input data rate of 133MB / s, a typical single-channel device SLC read rate of 27.7MB / s, if four read data channels together, the read rate of 27.7MB / s * 4 = 110MB / s; MLC typical single-channel device read rate of 22.5MB / s, if the read data with four channels, the read rate of 22.5MB / s * 4 = 90MB / s.

用了较长的时间,I/O通道传输数据时两次读数据之间,也会等待潜伏期, With a longer time, I / O data between two read channels for data transmission, will wait for the incubation period,

导致i/o通道利用率较低,读取速率低。 Resulting in lower i / o channel utilization, low read rate. 发明内容 SUMMARY

本发明实施例要解决的技术问题是提供一种读数据的方法、装置和系统, 提高读取速率。 Problem to be solved by embodiments of the present invention to provide a data reading method, apparatus and system to improve the read rates.

为解决上述技术问题,本发明所提供的读数据方法实施例可以通过以下 To solve the above technical problem, embodiments of a data read method of the invention may be provided by

技术方案实现: Technical solution:

本发明实施例提供一种读数据方法,包括: Embodiment of the present invention provides a data reading method, comprising:

向第一闪存片发送第一读命令,接收到所述第一读命令的响应后,读所述第一读命令指向的数据; After sending a first read command to the first flash memory chip in response to receiving said first read command, the read data of the first read command is directed;

在所述向第一闪存片发送第一读命令之后,读所述第一读命令指向的数据之前,向第二闪存片发送第二读命令; Before transmitting after the first read command to the first flash memory chip, the read data read command directed to the first, second transmitting a read command to the second flash memory chip;

接收到所述第二读命令的响应,且所述读第一读命令指向的数据完成后, 读所述第二读命令指向的数据。 After receiving the response to the second read command, and the first read data read command directed completed, the second read command to read data directed.

本发明实施例还提供一种读数据装置,包括: Embodiments of the invention further provides a data reading apparatus, comprising:

读命令发送单元,用于向第一闪存片发送第一读命令,在所述向第一闪存片发送第一读命令之后,读所述第一读命令指向的数据之前,向第二闪存片发送第二读命令; Before reading command transmitting means for transmitting the first read command to the first flash memory chip, after transmitting the first read command to the first flash memory chip, reading the first data read command directed to the second flash memory chip transmitting a second read command;

响应接收单元,用于接收所述第一读命令的响应,接收第二读命令的响 Response receiving unit, for receiving the first read command in response to receiving a second read command response

应; should;

数据读取单元,用于接收到所述第一读命令的响应后,读所述第一读命令指向的数据;接收到所述第二读命令的响应,且所述读第一读命令指向的数据完成后,读所述第二读命令指向的数据。 After the data reading unit, in response to the first read command is received, the first read command to read data directed; in response to receiving the second read command, read command and the first read point after the data is completed, the second read command to read data directed.

本发明实施例再提供一种读数据系统,包括: Embodiments of the invention further provides a data reading system, comprising:

读取控制器、与非门闪存存储器,所述与非门闪存存储器包括第一闪存片,第二闪存片;其特征在于, Read controller, NAND flash memory, a NAND flash memory and a flash memory includes a first sheet, a second flash memory chip; wherein,

所述读取控制器,用于向第一闪存片发送第一读命令,接收到所述第一读命令的响应后,读所述第一读命令指向的数据; After the read controller, for transmitting the first read command to the first flash memory chip in response to receiving said first read command, the read data of the first read command is directed;

在所述向第一闪存片发送第一读命令之后,所述读第一读命令指向的数据之前,向第二闪存片发送第二读命令; Before transmitting after the first read command to the first flash memory chip, the data of the first read command directed to read, sending the second read command to the second flash memory chip;

接收到所述第二读命令的响应,且所述读第一读命令指向的数据完成后,读所述第二读命令指向的数据。 After receiving the response to the second read command, and the first read data read command directed completed, the second read command to read data directed.

上述技术方案具有如下有益效果:通过在第一读命令与读上述第一读命令指向的数据之间,发送第二读命令,复用了读潜伏期,两次读数据之间不再有读潜伏期,提高了I/0通道利用率,从而提高读取速率。 Above technical solutions have the following beneficial effects: by between the first read command and the read data point to the first read command, transmitting the second read command, the read latency multiplexed, there is no latency between the read data read twice improved I / 0 channel utilization, thereby improving the reading rate. 附图说明 BRIEF DESCRIPTION

为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲, 在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。 In order to more clearly illustrate the technical solutions in the embodiments or the prior art embodiment of the present invention, the accompanying drawings briefly described embodiments or the prior art needed to be used in describing the embodiments. Apparently, the drawings in the following description only some embodiments, those of ordinary skill in the art is concerned, without any creative effort, and may still derive other drawings from the accompanying drawings of the present invention.

图l为现有技术读一片闪存片流程示意图; Figure l a schematic flow diagram of a flash memory chip is read prior art;

图2为现有^l支术读四片闪存片流程示意图; Figure 2 is a schematic view of the prior art read branched ^ l four flash flow sheet;

图3为本发明方法实施例一流程示意图; FIG 3 is a schematic flow diagram of a method embodiment of the present invention;

图4为本发明方法实施例二流程示意图; 4 is a flow chart according to a second embodiment of a schematic diagram of the inventive method;

图5为本发明方法实施例二读闪存片流程示意图; Flash flow sheet according to a second reading method of the present invention in FIG. 5 a schematic view;

图6为本发明方法实施例二的一个应用场景示意图; A schematic application scenario according to the second method of the present invention in FIG. 6;

图7为本发明实施例三装置结构示意图; FIG 7 is a schematic configuration example of the third means of the present embodiment of the invention;

图8为本发明实施例四系统结构示意图。 Figure 8 a schematic view of four system configuration example embodiment of the present invention. 具体实施方式 detailed description

本发明实施例要解决的技术问题是提供一种读数据的方法、装置和系统, 提高读取速率。 Problem to be solved by embodiments of the present invention to provide a data reading method, apparatus and system to improve the read rates.

实施例一,如图3所示,本发明实施例提供了一种读数据的方法,包括: 步骤301:向第一闪存片发送第一读命令;接收上述第一读命令的响应; 第一读命令可以为发送的读取请求消息,该读取请求消息包括读命令和读地址; First embodiment, as shown, embodiments of the present invention provides a method of reading data, comprising 3: Step 301: sending a first read command to the first flash memory chip; receiving a response to the first read command; first a read command to read the request message sent to the read request message includes a read command and a read address;

步骤302:在上述向第一闪存片发送第一读命令之后,读上述第一读命令指向的数据之前,向第二闪存片发送第二读命令;接收到上述第二读命令的响应; Step 302: after the transmission before the first read command to the first flash memory chip, reading data of a first read command directed, transmitting the second read command to the second flash memory chip; receiving a response to the second read command;

上述向第二闪存片发送第二读命令可以是:连续向三片第二闪存片分别发送第二读命令; The transmitting second read command to the second flash memory chip may be: continuously transmitting the second read command to the three second flash memory chip, respectively;

7步骤303:接收到上述第一读命令的响应后,读上述第一读命令指向的数 303 Step 7: Upon reception of the response to the first read command, read command to read the above-described first number of points

据; according to;

上述接收到上述第一读命令的响应后,读上述第一读命令指向的数据; 的具体方法可以为:第一闪存片接收到第一读命令后,发送R/B^信号来响应第一读命令,R/B弁信号为就绪(ready)状态,则可以发送RE弁信号读出该片Flash中的数据; Upon reception of the response to the above-described first read command, read command to read the first data point; specific method may include: a first read command after receiving the first flash memory chip, transmits R / B ^ a first signal in response to read command, R / B signal Bian ready (ready) state, a signal may be sent Bian RE reads data in Flash sheet;

步骤304:接收到上述第二读命令的响应,且上述读第一读命令指向的数据完成后,读第二读命令指向的数据。 Step 304: receiving a response to the second read command, and after the read command is directed to the first read data is completed, the second read data read command directed.

第二闪存片中数据的读取方法与第一闪存片的读取方法是相同的。 The second method of reading a flash memory data slice is the same as the method of reading a flash memory of the first sheet.

上述方法的执行主体可以为控制数据读取的各种设备,或者设备中负责数据读取控制的模块;为了表述方便,称一次读取过程中,发送的一条读命令为第一读命令,其指向的闪存片为第一闪存片;上述第一读命令的下一条读命令为第二读命令,第二读命令指向的闪存片为第二闪存片;可以理解的是,第二读命令可以有多条,第二闪存片可以有与第二读命令一样多的片数。 Performing the above method may be subject to control various devices read data, or control device responsible for data reading module; to facilitate the presentation, said first read process, a read command is sent by a first read command which a first sheet is a flash point Flash sheet; at the first read command is a read command of a second read command, a read command to the second flash memory chip is directed the second flash memory chip; It will be appreciated that the second read command a plurality of second flash memory chip can have as many second read command several pieces.

上述方法,通过在第一读命令与读上述第一读命令指向的数据之间,发送第二读命令,复用了读潜伏期,两次读数据之间不再有读潜伏期,提高了I/0 通道利用率,从而提高读取速率。 The above-described method, the first read between the data read command directed to the first read command, transmitting the second read command, the read latency multiplexed, there is no latency between the read data read twice, improved I / 0 channel utilization, thereby improving the reading rate.

实施例二,作为应用实施例一方法的一个例子,本发明实施例还提供了一种读数据的方法,本实施例中,将从四片闪存片(第一闪存片l、第二闪存片2、第三闪存片3、第四闪存片4)中依次读数据;如图4所示,包括以下步骤: According to the second embodiment, as an application example of a method according to one embodiment, embodiment the present invention further provides a method of reading data, in the present embodiment, the flash memory chip from four (L first flash memory chip, the second flash memory chip 2, the third flash memory chip 3,) the fourth flash memory chip 4 to read data sequentially; 4, comprising the steps of:

步骤401:向闪存片l发第一读命令和第一读地址,然后等待闪存片l的R/B^J信号响应; Step 401: Send to the flash memory chip and the first read command l a first read address, and then wait for the flash memory chip l R / B ^ J response signal;

步骤402:在等待闪存片1的R/B弁—l信号响应期间,依次向闪存片2、闪存片3、闪存片4分別发送读命令和读地址(这些读命令可以依次分别为第二读命令、第三读命令和第四读命令;这些读地址可以标记为第二读地址、第三读地址和第四读地址),然后等待闪存片2、闪存片3、闪存片4的R/B弁—2 、 R/B#_3 、 R/B#—4信号响应; Step 402: a flash memory chip during standby of R 1 / B signal response Benten -l, 2 sequentially to the flash memory chip, a flash memory chip 3, a flash memory chip 4 are transmitted read command and a read address (read commands which may in turn respectively second read command, a third read command and a fourth read command; these read addresses may be labeled as a second read address, the read address of the third and fourth read address), and then waits for a flash memory chip 2, the flash memory chip 3, R 4 pieces of flash / B Bian -2, R / B # _3, R / B # -4 signal in response;

由于tR的时间远大于发读命令和读地址的时间,所以4片闪存片发送读命令和读地址完成后,tR应该还没有完成(tR—般为20000ns左右而发送读命令和读地址200ns左右,也就是说理论上一般可以连续向100片闪存片发送读命令和读地址)当然由于读数据的控制装置的型号不同,tR也可以有很多种,但是一般都远大于发送读命令和读地址所需要的时间。 Since the development time tR time is much larger than the read command and read address, the flash memory chip 4 sends a read command and a read address is completed, tR should not completed (Tr- generally from about 20000ns transmits a read command and a read address of about 200ns , that is generally continuous transmission is theoretically read command and a read address to the flash memory chip 100) of course, since the different types of the read data control means, tR may there are many, but are generally much larger than the read address and a read command is time required. 一次连续发送多少个读命令和读地址可以根据本次读取数据需要读取的片数来确定,如果需要读取的闪存片有非常多个, 一次连续发送读命令和读地址的时间超过了潜伏期的时间,也可以分成几次来读取,每次读取的方法,与本实施例的方法相同。 How many read command and a read address of a continuous transmission may be determined according to the number of sheets to be read in this read data of the flash memory chip to be read if there is a plurality, and a continuous read command transmission time exceeds the read address the latency time may be divided into several times to read each reading method, the same method according to the present embodiment.

步骤403:接收到闪存片1返回的R/B弁一1信号为就绪(ready)状态时,向第一闪存片发送RE弁—l信号读出该片Flash中的数据; Step 403: The receiving sheet 1 is returned to the flash memory R / B Benten when a ready signal (ready) state, the transmission signal RE Bian -l sheet reads out the data in the first flash memory Flash sheet;

步骤404:闪存片2返回R/B弁—2信号的时间可能在读闪存片l的数据的时候,此时不发RE弁信号,直到闪存片l的数据读取完成后,向闪存片2发送RE弁信号读出该片Flash中的数据;同理,读取闪存片3、闪存片4的数据; Step 404: return a flash memory chip 2 R / B signal Bian -2 flash time may be read when the data slice l, at this time does not send the signal RE Bian, until after the flash memory chip l data read completion is sent to the flash memory chip 2 Bian RE signal readout data sheet in Flash; Similarly, reading the flash memory chip 3, 4 of the slice data flash;

上述方法实现过程还可以一并参阅图5,图5中显示前三片闪存的读取过程,在上述方法实施例中, 一片的RE弁信号发送完成后再发送下一片的RE弁信号;由于复用了读潜伏期,这样从总体来看,1/0输出的数据基本可以占满I/0 带宽,从而提高了读速率。 The method of the above-described process may also be implemented Referring to FIG. 5, a three-chip flash memory of the read process of FIG. 5, in the above-described method embodiments, the RE and then a completion signal transmitted Benten Benten transmission signal in an RE; as multiplexing read latency, so the whole, the data 1/0 output can substantially fill the I / O bandwidth, thus improving the read rate.

如图6所示,以上述方法的一个应用场景为例:,!/没系统的主才几601 (HOST)通过高级4支术附加装置(Advanced Technology Attachment, ATA) 接口和与非门闪存控制器602 (NAND Flash Controler)连接,来读取与非门闪存603 (NAND Flash)的数据,由于ATA接口最大的传输速率是133MB/s,每片与非门闪存603 (NAND Flash)的最大读写带宽为40MB/s,当NAND Flash 采用30ns的读周期和写周期读写数据的时候,带宽就是33.33MB/s。 6, to the above method an application scenario as an example:!, / No primary system only a few 601 (HOST) advanced by four additional operation means (Advanced Technology Attachment, ATA) interface, and control the NAND flash device 602 (NAND Flash Controler) connected to read the NAND flash 603 (NAND Flash) data, because the maximum ATA interface transfer rate is 133MB / s, the maximum read the NAND flash 603 (NAND Flash) per tablet write bandwidth is 40MB / s, when read and write data using NAND Flash 30ns read and write cycles, the bandwidth is 33.33MB / s. 为了提高系统的速率,采用4个NAND Flash通道并行处理,每个通道的NAND Flash相互独立,因此NANDFlash端的理论最大带宽即33.33举4二133MB/s。 In order to increase the rate of the system, NAND Flash with four parallel processing channels, each channel of the NAND Flash are independent, so the theoretical maximum bandwidth NANDFlash end i.e. give 33.33 4 two 133MB / s. 基于FPGA 的NAND Flash控制器用于接收ATA端的指令来控制NAND Flash。 FPGA-based NAND Flash controller for receiving instructions to control the end ATA NAND Flash. 如果采用现有技术的方式读NAND Flash,根据前面的介绍,对于典型的SLC器件四个通道一起读数据,理论读速率为27.7^48/3*4=110,/8;对于典型的MLC器件四个通道一起读凝:据,理论读速率为22.5MB/s5^ 4=90MB/s。 If the prior art embodiment read NAND Flash, in accordance with the preceding description, for a typical SLC read device with four data channels, read the theoretical rate of 27.7 ^ 48/4 = 3 * 110/8; For a typical MLC device read together condensate four channels: It theory read rate of 22.5MB / s5 ^ 4 = 90MB / s. -使用上述实施例的方法后:每个通道NAND Flash读速率-数据量/(发命令时间tCMD +发地址时 When the data amount / (time commanding the address sent tCMD + - NAND Flash read rate of each channel: - After the above-described method of this embodiment

9间tADDR +读潜伏期tR +读出数据时间tDATA),对于典型的SLC器件读速率=4片*4224Bytes/(7*30ns + 25 ja s + 4224承30ns承4片)=31.75MB/s,那么四个通道一起读数据,理论读速率为31.75MBW4427MB/s;对于典型的MLC器件读速率=4片*4224Bytes/(7*30ns + 60 ja s + 4224*30ns*4# )=29.7MB/s,那么四个通道一起读数据,理论读速率为29.7MB/s+4418MB/s。 9 tADDR + tR + read data read latency time tDATA), for a typical device SLC read rate = 4 * 4224Bytes / (7 * 30ns + 25 ja s + 4224 Cheng Cheng 30ns 4) = 31.75MB / s, data is read four channels together, the theoretical rate is read 31.75MBW4427MB / s; MLC device for a typical read rate = 4 * 4224Bytes / (7 * 30ns + 60 ja s + 4224 * 30ns * 4 #) = 29.7MB / s, then the read data of four channels together, the theoretical rate is read 29.7MB / s + 4418MB / s. 使用本发明实施例的方法,提高了数据的读取速度。 Using the method of Example of the present invention to improve the data read speed.

实施例三,如图7所示,本发明实施例还提供了一种数据读取装置,包括: 读命令发送单元701,用于向第一闪存片发送第一读命令,在上述向第一闪存片发送读命令之后,读上述第一读命令指向的数据之前,向第二闪存片发送第二读命令; The third embodiment, shown in FIG. 7, an embodiment of the present invention further provides a data reading apparatus comprising: read command sending unit 701, configured to send a first read command to the first flash memory chip, in the first to after the flash memory chip read command is issued before the first read command to read the data pointed transmitting the second read command to the second flash memory chip;

响应接收单元702,用于接收上述第一读命令的响应,接收第二读命令的响应; Response receiving unit 702, in response to receiving said first read command, in response to receiving a second read command;

数据读取单元703,用于接收到上述第一读命令的响应后,读上述第一读命令指向的数据;接收到上述第二读命令的响应,且上述读第一读命令指向 Data reading unit 703, in response to receiving said first read command, the read command reading data of the first point; receiving a response to the second read command, the read and the first read command directed

的数据完成后,读第二读命令指向的数据。 After the data is completed, the second read data read command directed.

可选地,上述读命令发送单元702向第二闪存片发送第二读命令后,读命令发送单元702还可以继续向第三闪存片分别发送第三读命令。 Optionally, the unit 702 transmits a read command after sending the second read command to the second flash memory chip, a read command transmitting unit 702 can continue to send the third read command to the third flash memory chip, respectively.

上述装置,通过在第一读命令与读上述第一读命令指向的数据之间,发送第二读命令,复用了读潜伏期,两次读数据之间不再有读潜伏期,提高了I/0 通道利用率,从而提高读取速率。 The above-described apparatus, the read command between a first read command and the read data of the first point above, transmitting a second read command, the read latency multiplexed, there is no latency between the read data read twice, improved I / 0 channel utilization, thereby improving the reading rate.

实施例四,如图8所示,本发明实施例还提供了一种数据读取系统,包括: 读取控制器801、与非门闪存存储器802,上述与非门闪存存储器802包括第一闪存片,第二闪存片; Embodiment 4 FIG. 8, an embodiment of the present invention further provides a data reading system, comprising: a read controller 801, the NAND flash memory 802, the above-described NAND flash memory comprises a first flash 802 sheet, the second flash memory chip;

其中, among them,

读取控制器801,用于向第一闪存片发送第一读命令,接收到上述第一读命令的响应后,读上述第一读命令指向的数据; After the read controller 801, for transmitting the first read command to the first flash memory chip, is received in response to the first read command, reading data of a first read command directed;

在上述向第一闪存片发送读命令之后,上述读第一读命令指向的数据之前,向第二闪存片发送第二读命令; After the above sending a read command to the first flash memory chip, the data before the first read said read command is directed sends a second read command to the second memory chip;

接收到上述第二读命令的响应,且上述读第一读命令指向的数据完成后,读第二读命令指向的数据。 Receiving a response to the second read command, and after the read command is directed to the first read data is completed, the second read data read command directed.

可选地,上述读取控制器801向第二闪存片发送第二读命令后,还包括继续向第三闪存片分别发送第三读命令。 After Alternatively, the reading controller 801 sends a second read command to the second flash memory chip, continue to send further comprising a third read command to the third flash memory chip, respectively.

上述系统,通过在第一读命令与读上述第一读命令指向的数据之间,发 The system described above, between the first read command by reading the data of the first point to the read command, hair

送第二读命令,复用了读潜伏期,两次读数据之间不再有读潜伏期,提高了I/0 Sending the second read command, the read latency multiplexed, there is no latency between the read data read twice, improved I / 0

通道利用率,从而提高读取速率。 Channel utilization, thereby improving the reading rate.

本领域普通技术人员可以理解实现上述实施例方法中的全部或部分步骤是可以通过程序来指令相关的硬件完成,所述的程序可以存储于一种计算机 Those of ordinary skill in the art may understand that the above embodiments of the method steps may be all or part by a program instructing relevant hardware, the program may be stored in a computer

可读存储介质中,上述提到的存储介质可以是存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、或技术领域内所公知的任意其它形式的存储介质中。 Readable storage medium, the storage medium may be a memory (RAM), a memory, a read only memory (ROM), electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, CD -ROM, or well-known in the technical field of any other form of storage medium.

以上对本发明实施例所提供的一种读数据的方法、装置和系统进行了详细介绍,本文中应用了具体个例对本发明的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本发明的方法及其核心思想;同时,对于本领域的一般技术人员,依据本发明的思想,在具体实施方式及应用范围上均会有改变之处,综上所述,本说明书内容不应理解为对本发明的限制。 A method of reading data examples provided above embodiment of the present invention, apparatus and system are described in detail herein through specific examples of the principles and embodiments of the invention are set forth in the above embodiment will be described only to help understanding of the method and core ideas of the present invention; while those of ordinary skill in the art, according to the ideas of the present invention, there are modifications to the specific embodiments and application scope of the specification content is not It should be construed as limiting the present invention.

Claims (9)

  1. 1、一种读数据方法,其特征在于,包括: 向第一闪存片发送第一读命令,接收到所述第一读命令的响应后,读所述第一读命令指向的数据; 在所述向第一闪存片发送第一读命令之后,读所述第一读命令指向的数据之前,向第二闪存片发送第二读命令; 接收到所述第二读命令的响应,且所述读第一读命令指向的数据完成后,读所述第二读命令指向的数据。 A data reading method comprising: transmitting a first read command to the first flash memory chip, after receiving the response to the first read command, read command to read the first data point; in the after sending a first read command to said first flash memory chip, prior to reading said first data read command directed is transmitted to the second read command a second flash memory chip; receiving a response to the second read command, and the after reading the first data point read command is completed, the second read command to read data directed.
  2. 2、 根据权利要求l所述方法,其特征在于,读所述第一读命令指向的数据之前,还向第三闪存片发送第三读命令。 2, l The method according to claim, characterized in that, prior to reading said first data read command directed further third read command transmitted to the third flash memory chip.
  3. 3、 根据权利要求2所述方法,其特征在于,所述第一闪存片和第二闪存片是与非门闪存NAND Flash片。 3. The method according to claim 2, wherein said first sheet and the second flash memory chip is a NAND flash memory NAND Flash Flash sheet.
  4. 4、 一种数据读取装置,其特征在于,包括:读命令发送单元,用于向第一闪存片发送第一读命令,在所述向第一闪存片发送第一读命令之后,读所述第一读命令指向的数据之前,向第二闪存片发送第二读命令;响应接收单元,用于接收所述第一读命令的响应,接收第二读命令的响应;数据读取单元,用于接收到所述第一读命令的响应后,读所述第一读命令指向的数据;接收到所述第二读命令的响应,且所述读第一读命令指向的数据完成后,读所述第二读命令指向的数据。 4. A data reading apparatus comprising: read command sending means for sending a first read command to the first flash memory chip, after transmitting the first read command to the first flash memory chip, the reading before the said first read command directed data is transmitted to the second read command a second flash memory chip; response receiving unit, for receiving a response to the first read command, in response to receiving a second read command; data reading unit, after the response to the first read command is received for reading said first data read command is directed; receiving a response to the second read command and the read command to read the first data point is completed, reading said second data read command directed.
  5. 5、 根据权利要求4所述装置,其特征在于,读所述第一读命令指向的数据之前,所述读命令发送单元还向第三闪存片发送第三读命令。 5. The apparatus as claimed in claim 4, characterized in that, prior to the data read command directed to the first read, the read command transmitting unit further transmits the third read command to the third flash memory chip.
  6. 6、 根据权利要求5所述的装置,其特征在于,所述第一闪存片和所述第二闪存片是与非门闪存NAND Flash片。 6. The apparatus as claimed in claim 5, wherein said first sheet and said second flash memory chip is a NAND flash memory NAND Flash Flash sheet.
  7. 7、 一种数据读取系统,包括:读取控制器、与非门闪存存储器,所述与非门闪存存储器包括第一闪存片,第二闪存片;其特征在于,所述读取控制器,用于向第一闪存片发送第一读命令,接收到所述第一读命令的响应后,读所述第一读命令指向的数据;在所述向第一闪存片发送第一读命令之后,所述读第一读命令指向的数据之前,向第二闪存片发送第二读命令;接收到所述第二读命令的响应,且所述读第一读命令指向的数据完成后, 读所述第二读命令指向的数据。 7. A data reading system, comprising: a read controller, the NAND flash memory, a NAND flash memory and a flash memory includes a first sheet, a second flash memory chip; wherein said read controller for transmitting a first read command to the first flash memory chip in response to receiving said first read command, the read command to read the first data point; transmitting said first sheet to the first flash memory read command Thereafter, the read command before reading the first data point, and transmits the second read command to the second flash memory chip; receiving a response to the second read command, and the first read data read command directed completed, reading said second data read command directed.
  8. 8、 根据权利要求7所述系统,其特征在于,读所述第一读命令指向的数据之前,所述读取控制器还向第三闪存片发送第三读命令。 8. A system according to claim 7, characterized in that, prior to the data read command directed to the first read, the read controller further sends a third read command to the third flash memory chip.
  9. 9、 根据权利要求8所述系统,其特征在于,所述第一闪存片和所述第二闪存片是与非门闪存NAND Flash片。 9. The system as claimed in claim 8, wherein said first sheet and said second flash memory chip is a NAND flash memory NAND Flash Flash sheet.
CN 200910119499 2009-03-17 2009-03-17 Method, device and system for reading data CN101515221A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 200910119499 CN101515221A (en) 2009-03-17 2009-03-17 Method, device and system for reading data

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN 200910119499 CN101515221A (en) 2009-03-17 2009-03-17 Method, device and system for reading data
PCT/CN2010/070752 WO2010105520A1 (en) 2009-03-17 2010-02-25 Method, apparatus and system for reading data

Publications (1)

Publication Number Publication Date
CN101515221A true true CN101515221A (en) 2009-08-26

Family

ID=41039688

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 200910119499 CN101515221A (en) 2009-03-17 2009-03-17 Method, device and system for reading data

Country Status (2)

Country Link
CN (1) CN101515221A (en)
WO (1) WO2010105520A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010105520A1 (en) * 2009-03-17 2010-09-23 成都市华为赛门铁克科技有限公司 Method, apparatus and system for reading data
CN105117179A (en) * 2015-09-22 2015-12-02 天津瑞发科半导体技术有限公司 Method for data interaction of host and storage device and storage controller
CN106155578A (en) * 2015-04-27 2016-11-23 四川效率源信息安全技术有限责任公司 Method for data reconstitution of mobile phone flash memory chip

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140036094A (en) 2012-09-14 2014-03-25 삼성전자주식회사 Host for controlling non-volatile memory crad, system including the same and operating method there-of

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6044429A (en) * 1997-07-10 2000-03-28 Micron Technology, Inc. Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths
KR100448905B1 (en) * 2002-07-29 2004-09-16 삼성전자주식회사 Computer system with nand flash memory for booting and storagement
US6870774B2 (en) * 2002-12-10 2005-03-22 Micron, Technology, Inc. Flash memory architecture for optimizing performance of memory having multi-level memory cells
KR100518604B1 (en) * 2003-12-13 2005-10-04 삼성전자주식회사 Data inversion circuit of semiconductor device for performing inversion operation based on the interval for reading data and data inversion method using the same
US7158442B1 (en) * 2005-05-23 2007-01-02 Spansion Llc Flexible latency in flash memory
CN101515221A (en) * 2009-03-17 2009-08-26 成都市华为赛门铁克科技有限公司 Method, device and system for reading data

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010105520A1 (en) * 2009-03-17 2010-09-23 成都市华为赛门铁克科技有限公司 Method, apparatus and system for reading data
CN106155578A (en) * 2015-04-27 2016-11-23 四川效率源信息安全技术有限责任公司 Method for data reconstitution of mobile phone flash memory chip
CN105117179A (en) * 2015-09-22 2015-12-02 天津瑞发科半导体技术有限公司 Method for data interaction of host and storage device and storage controller

Also Published As

Publication number Publication date Type
WO2010105520A1 (en) 2010-09-23 application

Similar Documents

Publication Publication Date Title
US6453393B1 (en) Method and apparatus for interfacing to a computer memory
US7281079B2 (en) Method and apparatus to counter mismatched burst lengths
US20050289317A1 (en) Method and related apparatus for accessing memory
US20100318718A1 (en) Memory device for a hierarchical memory architecture
US20100115172A1 (en) Bridge device having a virtual page buffer
US7979757B2 (en) Method and apparatus for testing high capacity/high bandwidth memory devices
US7471538B2 (en) Memory module, system and method of making same
US6795899B2 (en) Memory system with burst length shorter than prefetch length
US20100110745A1 (en) Switched interface stacked-die memory architecture
US20110246857A1 (en) Memory system and method
CN103810113A (en) Fusion memory system of nonvolatile memory and dynamic random access memory
US20130297987A1 (en) Method and Apparatus for Reading NAND Flash Memory
US7778092B2 (en) Memory system and method having volatile and non-volatile memory devices at same hierarchical level
US20150261446A1 (en) Ddr4-onfi ssd 1-to-n bus adaptation and expansion controller
CN102063274A (en) Storage array, storage system and data access method
US20110145493A1 (en) Independently Controlled Virtual Memory Devices In Memory Modules
US20080320191A1 (en) System and method for providing a configurable command sequence for a memory interface device
CN101082891A (en) Paralleling flash memory controller
US6532523B1 (en) Apparatus for processing memory access requests
CN101162449A (en) NAND FLASH controller and data interactive method with NAND FLASH chip
US20060236007A1 (en) Apparatus to improve bandwidth for circuits having multiple memory controllers
CN101702326A (en) Memory controller
US20110296118A1 (en) Dynamic Row-Width Memory
US20090103364A1 (en) Serial interface nand
CN101650639A (en) Storage device and computer system

Legal Events

Date Code Title Description
C06 Publication
C10 Request of examination as to substance
C02 Deemed withdrawal of patent application after publication (patent law 2001)