CN110688330B - Virtual memory address translation method based on memory mapping adjacency - Google Patents
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- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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Abstract
The invention discloses a virtual memory address translation method based on memory mapping adjacency, which comprises the following steps: 1) dividing each 2MB virtual address space into 8 memory sub-domains with equal length; 2) when the operating system allocates the memory space, scanning the page table, identifying the memory subdomains mapped continuously, and storing the mapping continuity information inside the memory subdomains and among the memory subdomains in unused bits in the 2-level page table entries; 3) when a page table is searched in the process of address translation, address translation information of a continuous mapping memory domain is merged according to mapping continuity information stored in a 2-level page table entry and is stored in a TLB; 4) in order to further increase the number of pages capable of merging address translation information, continuity between memory sub-domains of continuous mapping is detected when a page table is searched, and continuity information between the memory sub-domains is stored in a memory sub-domain cache to reduce the number of memory access times. The invention can effectively improve the coverage of the TLB and improve the hit rate of the TLB, thereby reducing the overhead of virtual memory address translation.
Description
Technical Field
The invention relates to the fields of virtual memory management, address translation and the like, in particular to a virtual memory address translation method based on memory mapping adjacency.
Background
The virtual memory technology can effectively improve the security of the process and the available memory capacity, and before the memory access based on the virtual memory, the virtual address needs to be translated into a physical address, and then the memory data can be accessed by using the physical address. In a structure with 4-level page tables, since the page tables are stored in the memory, the address translation process needs to access the memory up to 4 times, which is very time-consuming. Address translation operations have long been recognized as one of the performance bottlenecks of processors. Although a Translation Lookaside Buffer (TLB) can avoid multiple memory accesses caused by page table lookup operations to some extent, as the process memory occupancy becomes larger and irregular memory access operations become more and more frequent, the TLB has a more and more limited improvement on the performance of address Translation operations.
In order to further improve the virtual memory efficiency and reduce the address translation overhead, a great deal of research work is carried out in academia and industry. The existing representative research results are mainly divided into the following two aspects:
(1) memory management method based on huge page
The memory management method based on the giant page manages the memory by taking the giant page (such as 2MB or 1GB) as a unit, and the address translation information stored by the TLB takes the giant page as the unit, so that the coverage range of the address translation information in the TLB is increased, the hit rate of the TLB is improved, and the address translation cost is greatly reduced. However, the support of megapages often introduces additional memory management overhead, such as frequent memory compaction and migration.
(2) Address translation merging method based on basic page
The address translation merging method based on the base page manages the memory by taking the base page (4KB) as a unit, does not need the support of a huge page, and generally merges and saves the address translation information of a plurality of continuously mapped adjacent base pages in the TLB in order to improve the address translation efficiency, thereby improving the hit rate of the TLB and reducing the address translation overhead. However, the current address translation merging method based on the base page can only merge the address translation information of a limited number of base pages, and in order to merge the address translation information of as many base pages as possible, the memory management policy of the operating system needs to be changed to allocate and allocate as large continuous mapping memory domains as possible.
In summary, in order to improve the address translation efficiency, the existing method needs to either support the macro page or modify the memory management mechanism of the operating system. The invention provides a virtual memory address translation method based on memory mapping adjacency, which is based on basic pages, can combine address translation information of up to 512 basic pages on the premise of not modifying an operating system memory management strategy, and greatly improves the address translation efficiency.
Disclosure of Invention
The invention solves the problems: the method is based on the basic page, and can combine the address translation information of up to 512 basic pages on the premise of not modifying the memory management strategy of an operating system.
The technical scheme of the invention is that a virtual memory address translation method based on memory mapping adjacency comprises the following steps:
(1) dividing a process virtual address space into memory subdomains, scanning a process Page Table and identifying memory subdomains mapped continuously after an operating system allocates a physical memory space for a process, and finally storing mapping continuity information of the memory subdomains in corresponding 2-Level Page Table entries (Level 2Page Table entries, hereinafter referred to as L2PTE) after expansion;
(2) when a processor executes a memory access instruction, Translation operation from a virtual address to a physical address needs to be executed firstly, and when requested address Translation information does not exist in a Translation Lookaside Buffer (TLB for short), page table query operation is executed;
(3) in the process of page table query, judging the virtual page VPN to which the request address belongs according to the mapping continuity information in the L2PTEreqWhether the VPN is located in the continuous mapping memory sub-domain or not and further obtaining the VPN according to the continuity informationreqMapped physical page number PPNreq；
(4) VPN obtaining virtual page number of request addressreqMapped physical page number PPNreqThen, obtaining the physical address mapped by the requested virtual address according to the offset address in the page, and returning the physical address to the execution unit;
(5) in addition, if the request address belongs to the virtual page VPNregIf the address translation information is located in the continuous mapping memory sub-domain, the merged address translation information of the continuous mapping memory domain is stored in the TLB; otherwise, only the virtual page number VPN to which the request address belongsreqTo physical page number PPNreqThe mapping relation of (2) is stored in the TLB;
(6) when the address translation operation needs to be executed and the TLB is inquired, whether the requested address is in the coverage range of the address translation information in the TLB item or not is judged according to the type of the TLB item, if the TLB item contains the translation information of the requested address, a real physical address can be obtained according to the address translation information in the TLB item, and if not, the step (2) is executed.
Drawings
FIG. 1 is a schematic diagram of the present invention;
FIG. 2 is a comparison of a conventional page table entry format and an extended level 2page table entry format proposed by the present invention;
FIG. 3 is 3 scenarios and methods of page table walk based on memory sub-domain map continuity information;
FIG. 4 is a schematic diagram of the memory sub-domain cache field format and map adjacency information generation;
FIG. 5 is a comparison graph of a conventional TLB field format and a fused TLB field format;
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The basic idea of the present invention is that, as shown in fig. 1, each 2MB large page frame in the virtual address space is equally divided into 8 memory sub-domains with fixed sizes, after the operating system allocates the memory space, the page table is scanned and the mapping continuity of the memory sub-domains is detected, and the mapping continuity information is stored in L2 PTE; in the process of address translation, address translation information of a plurality of adjacent memory subdomains mapped continuously is merged and stored in the TLB by analyzing the mapping continuity information stored in the L2PTE, so that the hit rate of the TLB is increased, and the efficiency of address translation is improved.
The invention relates to a virtual memory address translation method based on memory mapping adjacency, which comprises the following steps:
1. dividing the address space of each 2MB large page frame in the process virtual address space into 8 sub-address spaces with equal length, wherein each sub-address space is called as a memory sub-domain, after an operating system allocates a physical memory space for a process, scanning a process page table and judging the mapping continuity of the memory sub-domain according to whether a segment of continuous virtual address space represented by the memory sub-domain is mapped to a segment of continuous physical address space, and finally, storing the mapping continuity information of the memory sub-domain in the corresponding extended L2PTE bit, as shown in fig. 2, the extension bit in the L2PTE includes:
(1) use of 8 bits (i.e., C) in the unused bits of the L2PTE high order bits0～C7) Used for respectively storing the continuity information of the corresponding 8 memory sub-domains;
(2) using 1 bit (i.e., C) in the unused bits of the L2PTE high order bitsa) For storing mapping continuity information corresponding to 2MB virtual large page frame
The method for storing the mapping continuity information of the memory subdomain in the corresponding expanded L2PTE comprises the following steps:
(1) for each L2PTE of a process page table, sequentially judging the mapping continuity of 8 memory subdomains in a 2MB virtual large page frame pointed by the L2PTE and the mapping continuity of the whole 2MB virtual large page frame;
(2) if a memory sub-field is mapped continuously, the corresponding memory sub-field status bit C in the L2PTE to which the memory sub-field belongsn1, placing;
(3) if an entire 2MB virtual large page frame is mapped to a contiguous 2MB physical address space, C in its L2PTE a1, placing.
2. When a processor executes a memory access instruction, Translation operation from a virtual address to a physical address needs to be executed firstly, and when requested address Translation information does not exist in a Translation Lookaside Buffer (TLB for short), page table query operation is executed;
3. in the process of page table query, judging the virtual page VPN to which the request address belongs according to the mapping continuity information in the L2PTEregWhether the mapping table is located in the continuous mapping memory sub-domain or not is shown in fig. 3, and the specific determination method is as follows:
(1) when reading L2PTE, if CaBit 1 indicates the requested virtual page VPNregContinuously belonging to a continuous mapping memory sub-domain and belonging to a continuous mapping 2MB virtual large page frame;
(2) if C is presentaBit 0, but virtual Page VPNregC corresponding to the located memory sub-domainiBit 1 indicates the requested virtual page VPNregBelongs to a continuous mapping memory sub-domain;
(3) if C is presentaBit is 0 and virtual page VPNregC corresponding to the located memory sub-domainiBit is also 0, indicating the requested virtual page VPNregNot to a contiguous mapped memory sub-domain.
Then, further obtaining VPN according to the continuity informationreqMapped physical page number PPNreqThe specific method comprises the following steps:
(1) virtual page VPN when requestedregWhen 2MB virtual large page frames belonging to continuous mapping only need to read the first level 1 page table item pointed by L2PTE and obtain the physical page number PPN stored in the first level 1 page table item0Then, according to the virtual page number VPN pointed by the first level 1 page table item0The requested virtual page VPN can be obtainedregMapped physical page number PPNreq：PPNreq＝PPN0+(VPNreq-VPN0)；
(2) Virtual page VPN when requestedregNot belonging to a contiguously mapped 2MB virtual large page frame, but belonging to a contiguously mapped memory sub-field ScurThen according to the current memory sub-domain ScurObtaining requested virtual page VPN from continuity between all adjacent memory sub-domainsreqMapped physical page number PPNreq；
(3) Virtual page VPN when requestedregWhen the mapping does not belong to the continuous mapping memory subdomain, directly reading the corresponding level 1 page table entry, wherein the stored physical page number is the virtual page VPNreqMapped physical page number PPNreq。
In the above step (2), according to the current memory domain ScurObtaining requested virtual page VPN from continuity between all adjacent memory sub-domainsreqMapped physical page number PPNreqThe method comprises the following specific steps:
(1) reading all and current memory sub-fields S in current 2MB virtual large page framecurThe level 1 page table item of the first virtual page of the adjacent continuous mapping memory subdomain is not reached until the discontinuous mapping memory subdomain is met;
(2) determining which adjacent contiguously mapped memory subfields and current memory according to physical page number in level 1 page table entry of first virtual page of the contiguously mapped memory subfieldsMemory field ScurCan form a larger continuous mapping memory domain, and then according to the first virtual page number VPN in the formed larger continuous mapping memory domains0And its mapped physical page number PPNs0The requested virtual page VPN is availablereqMapped physical page number PPNreq：PPNreq＝PPNs0+(VPNreq-VPNs0)。
In addition, in order to reduce the number of times of accessing and storing the page table entry of level 1 in step (1), the continuity information between Memory sub-domains is stored in a Memory sub-domain Cache (MSC), as shown in fig. 4, where the MSC entry includes the following fields:
(1) tag: a tag field for storing a virtual large page frame number;
(2) contiity _ Info: mapping the adjacency information field, wherein the length of the adjacency information field is 7 bits, each bit represents whether the corresponding two adjacent memory sub-domains are continuous, and the condition of a certain position 1 is as follows: two corresponding adjacent memory sub-fields are continuously mapped, and the two adjacent memory sub-fields can form a larger continuously mapped memory field;
(3) flag: an identification field, holding validity information, etc.
4. VPN obtaining virtual page number of request addressreqMapped physical page number PPNreqThen, obtaining the physical address mapped by the requested virtual address according to the offset address in the page, and returning the physical address to the execution unit;
5. in addition, if the request address belongs to the virtual page VPNregIf the address translation information is located in the continuous mapping memory sub-domain, the merged address translation information of the continuous mapping memory domain is stored in the TLB; otherwise, only the virtual page number VPN to which the request address belongsreqTo physical page number PPNreqThe mapping relation of (2) is stored in the TLB; the merging method of the address translation information comprises the following steps:
(1) virtual page VPN when requestedregWhen the 2MB virtual large page frame belongs to continuous mapping, the global number of the first memory subdomain of the 2MB address space, the number of the memory subdomains in the 2MB virtual large page frame and the 2MB virtual large page are determinedThe physical page number of the first virtual page mapping of the frame is stored in the TLB entry;
(2) virtual page VPN when requestedregNot belonging to a contiguously mapped 2MB virtual large page frame, but belonging to a contiguously mapped memory sub-field ScurThen, the current memory sub-domain S is setcurThe global number of the first memory subdomain in a larger continuous mapping memory domain formed by a plurality of continuous mapping memory subdomains adjacent to the first memory subdomain, the number of the memory subdomains in the larger continuous mapping memory domain and the physical page number of the first virtual page mapping in the larger continuous mapping memory domain are stored in the TLB item;
(3) virtual page VPN when requestedregWhen not in the continuous mapping memory sub-domain, the virtual page VPN of the request address is directly usedreqAnd its mapped physical page number PPNreqStored in the TLB entry.
6. When the address translation operation needs to be executed and the TLB is inquired, whether the requested address is in the coverage range of the address translation information in the TLB item or not is judged according to the type of the TLB item, if the TLB item contains the translation information of the requested address, a real physical address can be obtained according to the address translation information in the TLB item, and if not, the step (2) is executed.
As shown in fig. 5, the TLB entry types include 2 types: (1) storing the aggregated TLB item of the merged address translation information; (2) saving a conventional TLB entry mapping a conventional virtual page number to a physical page number; the format of a conventional TLB entry does not change, and the aggregate TLB entry contains the following fields:
(1) tag: a tag field for storing the global number of the memory sub-domain;
(2) length: a length field indicating the number of consecutive mapped memory subdomains aggregated by the TLB entry;
(3) base: a starting physical page number field, which represents the initial physical page number of the physical address space mapped by the continuous mapping memory subdomain aggregated by the TLB item;
(4) flag: an identification field, holding validity information, etc.
In performing an address translation operation and querying an aggregate TLB entry, if the TLB entry is valid, the following steps are performed to compute a request virtual page VPNreqMapped physical page number PPNreq：
(1) Calculating the range of virtual page covered by the item according to Tag and Length fields in the item of the aggregation TLB (minimum virtual page VPN)minAnd maximum virtual page VPNmax)：
VPNmin＝Tag＜＜6
VPNmax＝((Tag+Length)＜＜6)|0x3F
(2) Virtual page VPN if requestedreq∈[VPNmin，VPNmax]Then, it indicates that virtual page VPN is requestedreqMapped physical page number PPNreqFrom this TLB entry: PPNreq＝Base+(VPNreq-VPNmin)；
(3) VPN for requesting virtual page if none of TLB entries contains a requestregThe page table walk operation needs to be further executed.
The invention has not been described in detail and is within the skill of the art.
The above description is only a part of the embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (9)
1. A virtual memory address translation method based on memory mapping adjacency is characterized by comprising the following steps:
(1) dividing the address space of each 2MB large page frame in the process virtual address space into 8 sub-address spaces with equal length, wherein each sub-address space is called as a memory subdomain, after an operating system distributes a physical memory space for a process, scanning a process page table and identifying a memory subdomain which is mapped continuously, and finally, storing the mapping continuity information of the memory subdomain in a corresponding extended 2-level page table item L2 PTE;
(2) when the processor executes the access instruction, the translation operation from the virtual address to the physical address needs to be executed firstly, and when the requested address translation information does not exist in the bypass translation cache TLB, the page table query operation is executed;
(3) in the process of page table query, judging the virtual page VPN to which the request address belongs according to the mapping continuity information in the L2PTEreqWhether the VPN is located in the continuous mapping memory sub-domain or not and further obtaining the VPN according to the continuity informationreqMapped physical page number PPNreq；
(4) VPN obtaining virtual page number of request addressreqMapped physical page number PPNreqThen, obtaining the physical address mapped by the requested virtual address according to the offset address in the page, and returning the physical address to the execution unit;
(5) in addition, if the request address belongs to the virtual page VPNreqIf the address translation information is located in the continuous mapping memory sub-domain, the merged address translation information of the continuous mapping memory domain is stored in the TLB; otherwise, only the virtual page number VPN to which the request address belongsreqTo physical page number PPNreqThe mapping relation of (2) is stored in the TLB;
(6) when the address translation operation needs to be executed and the TLB is inquired, whether the requested address is in the coverage range of the address translation information in the TLB item or not is judged according to the type of the TLB item, if the TLB item contains the translation information of the requested address, a real physical address can be obtained according to the address translation information in the TLB item, and if not, the step (2) is executed.
2. The method of claim 1, wherein the virtual memory address translation method based on memory map adjacency comprises: in the step (1), scanning a process page table and identifying a memory sub-field which is mapped continuously, wherein the condition for judging whether the memory sub-field is mapped continuously is whether a section of continuous virtual address space represented by the memory sub-field is mapped to a section of continuous physical address space; the method for storing the mapping continuity information of the memory sub-domain in the corresponding L2PTE after expansion comprises the following steps:
(1) for each L2PTE of a process page table, sequentially judging the mapping continuity of 8 memory subdomains in a 2MB virtual large page frame pointed by the L2PTE and the mapping continuity of the whole 2MB virtual large page frame;
(2) if one isIf each memory sub-domain is mapped continuously, the corresponding memory sub-domain status bit C in the L2PTE to which it belongsn1, placing;
(3) if an entire 2MB virtual large page frame is mapped to a contiguous 2MB physical address space, C in its L2PTEa1, placing.
3. The method of claim 1, wherein the virtual memory address translation method based on memory map adjacency comprises: in the step (1), the mapping continuity information of the memory sub-domain is stored in the corresponding extended L2PTE bit, and the extension mode of the L2PTE is as follows:
(1) using 8-bit C in the unused bits of the L2PTE high order bits0～C7Respectively storing the continuity information of the corresponding 8 memory sub-domains;
(2) using 1-bit C in the unused bits of the L2PTE high order bitsaFor storing mapping continuity information corresponding to 2MB virtual large page frames.
4. The method according to claim 1, wherein in step (3), the virtual page VPN to which the request address belongs is determined according to mapping continuity information in L2PTEreqWhether the mapping table is located in the continuous mapping memory sub-domain or not is determined by the following specific method:
(1) when reading L2PTE, if CaBit 1 indicates the requested virtual page VPNreqContinuously belonging to a continuous mapping memory sub-domain and belonging to a continuous mapping 2MB virtual large page frame;
(2) if C is presentaBit 0, but virtual Page VPNreqC corresponding to the located memory sub-domainiBit 1 indicates the requested virtual page VPNreqBelongs to a continuous mapping memory sub-domain;
(3) if C is presentaBit is 0 and virtual page VPNreqC corresponding to the located memory sub-domainiBit is also 0, indicating the requested virtual page VPNreqNot to a contiguous mapped memory sub-domain.
5. The method according to claim 1, wherein in step (3), the VPN is further obtained according to the continuity informationreqMapped physical page number PPNreqThe specific method comprises the following steps:
(1) virtual page VPN when requestedreqWhen 2MB virtual large page frames belonging to continuous mapping only need to read the first level 1 page table item pointed by L2PTE and obtain the physical page number PPN stored in the first level 1 page table item0Then, according to the virtual page number VPN pointed by the first level 1 page table item0The requested virtual page VPN can be obtainedreqMapped physical page number PPNreq：PPNreq＝PPN0+(VPNreq-VPN0)；
(2) Virtual page VPN when requestedreqNot belonging to a contiguously mapped 2MB virtual large page frame, but belonging to a contiguously mapped memory sub-field ScurThen according to the current memory sub-domain ScurObtaining requested virtual page VPN from continuity between all adjacent memory sub-domainsreqMapped physical page number PPNreq；
(3) Virtual page VPN when requestedreqWhen the mapping does not belong to the continuous mapping memory subdomain, directly reading the corresponding level 1 page table entry, wherein the stored physical page number is the virtual page VPNreqMapped physical page number PPNreq。
6. The method according to claim 5, wherein in step (2), the virtual memory address translation method is based on the current memory sub-domain ScurObtaining requested virtual page VPN from continuity between all adjacent memory sub-domainsreqMapped physical page number PPNreqThe method comprises the following specific steps:
(1) reading all and current memory sub-fields S in current 2MB virtual large page framecurThe level 1 page table item of the first virtual page of the adjacent continuous mapping memory subdomain is not reached until the discontinuous mapping memory subdomain is met;
(2) according to the number of these consecutive memory sub-fieldsPhysical page numbers in level 1 page table entries of a virtual page determine which contiguous contiguously mapped memory sub-fields are adjacent to the current memory sub-field ScurCan form a larger continuous mapping memory domain, and then according to the first virtual page number VPN in the formed larger continuous mapping memory domains0And its mapped physical page number PPNs0The requested virtual page VPN is availablereqMapped physical page number PPNreq：PPNreq＝PPNs0+(VPNreq-VPNs0)；
In order to reduce the number of times of accessing and storing the 1-level page table entry in the step (1), the continuity information between memory sub-domains is stored in a memory sub-domain cache MSC, wherein the MSC entry comprises the following fields:
(1) tag: a tag field for storing a virtual large page frame number;
(2) contiity _ Info: the length of the adjacency information field is 7 bits, wherein each bit represents whether two corresponding adjacent memory sub-domains are continuous, and the condition of a certain position 1 is as follows: two corresponding adjacent memory sub-fields are continuously mapped, and the two adjacent memory sub-fields can form a larger continuously mapped memory field;
(3) flag: and the identification field stores validity information and related data of the replacement algorithm.
7. The virtual memory address translation method based on memory mapping adjacency according to claim 1, wherein in step (5), the merged address translation information of the consecutive mapping memory domains is stored in the TLB by a specific merging method:
(1) virtual page VPN when requestedreqWhen the 2MB virtual large page frames belong to continuous mapping, storing the global number of a first memory subdomain of the 2MB address space, the number of memory subdomains in the 2MB virtual large page frame and the physical page number of the first virtual page mapping of the 2MB virtual large page frame in a TLB item;
(2) virtual page VPN when requestedreqNot belonging to a contiguously mapped 2MB virtual large page frame, but belonging to a contiguously mapped memory sub-field ScurThen, the current memory sub-domain S is setcurThe global number of the first memory subdomain in a larger continuous mapping memory domain formed by a plurality of continuous mapping memory subdomains adjacent to the first memory subdomain, the number of the memory subdomains in the larger continuous mapping memory domain and the physical page number of the first virtual page mapping in the larger continuous mapping memory domain are stored in the TLB item;
(3) virtual page VPN when requestedreqWhen not in the continuous mapping memory sub-domain, the virtual page VPN of the request address is directly usedreqAnd its mapped physical page number PPNreqStored in the TLB entry.
8. The method for virtual memory address translation based on memory mapping adjacency according to claim 1, wherein in step (6), it is determined whether the requested address is within the coverage of address translation information in the TLB entry according to the type of TLB entry, wherein the types of TLB entry include 2 types: (1) storing aggregated TLB entries of the merged address translation information and (2) storing conventional TLB entries mapping from conventional virtual page numbers to physical page numbers; where the format of the conventional TLB entry is unchanged, the aggregate TLB entry contains the following fields:
(1) tag: a tag field for storing the global number of the memory sub-domain;
(2) length: a length field indicating the number of consecutive mapped memory subdomains aggregated by the TLB entry;
(3) base: a starting physical page number field, which represents the initial physical page number of the physical address space mapped by the continuous mapping memory subdomain aggregated by the TLB item;
(4) flag: an identification field, holding validity information, etc.
9. The method for virtual memory address translation based on memory mapping adjacency according to claim 1, wherein in step (6), the address translation operation is executed and the TLB is queried, wherein when querying the aggregated TLB entry in the TLB, if the TLB entry is valid, the steps are as follows:
(1) calculating the minimum virtual page VPN of the range of the virtual page covered by the aggregation TLB according to the Tag field and the Length field in the aggregation TLB entryminAnd maximum virtualizationPage VPNmax：
VPNmin＝Tag＜＜6
VPNmax＝((Tag+Length)＜＜6)|0x3F
(2) Virtual page VPN if requestedreq∈[VPNmin，VPNmax]Then, it indicates that virtual page VPN is requestedreqMapped physical page number PPNreqFrom this TLB entry: PPNreq＝Base+(VPNreq-VPNmin)；
(3) VPN for requesting virtual page if none of TLB entries contains a requestreqThe page table walk operation needs to be further executed.
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