CN111666230B - Method for supporting macro page in set associative TLB - Google Patents
Method for supporting macro page in set associative TLB Download PDFInfo
- Publication number
- CN111666230B CN111666230B CN202010464274.1A CN202010464274A CN111666230B CN 111666230 B CN111666230 B CN 111666230B CN 202010464274 A CN202010464274 A CN 202010464274A CN 111666230 B CN111666230 B CN 111666230B
- Authority
- CN
- China
- Prior art keywords
- page
- tlb
- group
- macro
- giant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a method for supporting a giant page in a group-associated TLB, wherein the group-associated TLB and a giant page record table are arranged for a common page and a giant page, and the group-associated TLB is accessed according to the group address and the TAG of the common page first in the process of accessing, and then the giant page record table is accessed according to the group address of the giant page. Compared with the scheme of using the group-associated and the full-associated TLB at the same time, the invention uses only one full-associated TLB to simultaneously store page table entries of a normal page and a giant page, accesses the TLB for addresses for multiple times according to the mode of analyzing the normal page and the giant page respectively, and obtains the page table entries of the possible normal page and the giant page. The giant page record table records whether the giant page table entries possibly exist according to groups, and each group only needs one bit, so that the occupied area is small.
Description
Technical Field
The invention relates to the technical field of set associative TLB access, in particular to a method for supporting a huge page in a set associative TLB.
Background
As the performance of processors increases, the capacity requirements of TLBs (Translation Lookup Table, commonly known as fast tables) are also increasing. The TLB of the conventional fully-associative structure cannot meet the requirement of TLB capacity increase due to high design complexity, so that more and more processors use the TLB of the set associative.
The group association refers to the way in which data in a memory is mapped into a specified group according to an address, and can be put into TLB and cache of any way in the group. The implementation complexity of the set associative TLB is greatly reduced relative to the fully associative TLB, so that a greater number of TLB entries may be supported.
Modern operating systems no longer require that all memory pages be of uniform size for improved performance, but rather have a distinction between Regular pages (pages) and giant pages (Huge pages). Most programs use smaller normal pages because the size of the macro page is much larger than normal pages, and for programs that are stream data processing based, the use of macro pages can greatly reduce the need for the number of TLB entries, reducing the performance penalty caused by TLB misses.
However, the set associative TLB suffers from the problem of supporting large pages, as shown in fig. 1, since the capacity of a large page is much larger than a normal page, its intra-page offset requires more address bits to represent: typically the page number of a normal page is the high order of the group-associative intra-page offset, while the intra-page offset of a normal page is the low order of the group-associative intra-page offset. The set-associative TLB is indexed using a portion of the address bits above the intra-page offset as the set address, and because the number of address bits used for intra-page offsets is different between the macro page and the normal page, the normal page and the macro page have different set addresses, and their corresponding TLB entries may be placed in different sets of the set-associative TLB.
In order to support the huge Page in the set-associative TLB, the conventional technology generally additionally sets a fully-associative TLB (for example, as described in MIPS Architecture For Programers Vol.3), and uses a fully-associative VTLB (Variable-Page-Size TLB) to cooperate with a set-associative FTLB (Fixed-Page-Size TLB), wherein the FTLB is responsible for storing Page table entries of normal pages, while the VTLB is mainly responsible for storing Page table entries of huge pages, when not using huge pages, the VTLB can also be used for storing Page table entries of normal pages, and the use of two TLB increases the complexity of the system, and needs to determine whether the two TLB hit at the same time, although the fully-associative TLB can also store Page directory of normal pages, but also needs to have an algorithm to determine whether the normal Page is stored in the fully-associative TLB or the set-associative TLB; the chip area occupied by the full associated TLB is much larger than the set associated TLB of the same number of entries.
Disclosure of Invention
The present invention is directed to a method for supporting megapages in a set associative TLB to solve the above-mentioned problems.
In order to achieve the above purpose, the present invention provides the following technical solutions: the method for supporting the megapage in the set-associative TLB comprises the following technical flows:
the first step, set up the set and associativity TLB and huge page record table to the ordinary page and huge page;
secondly, accessing the TLB;
step three, firstly, accessing a group-associated TLB according to the group address and the TAG of a common page in the process of accessing;
fourth, accessing the macro page record table according to the group address of the macro page;
and fifthly, judging the access result of the TLB.
Preferably, during operation in the first step, only a single set associative TLB is used, with page table entries for both pages and megapages typically held in the set associative TLB.
Preferably, during the operation of the first step, the macro page record table stores whether the set uses macro pages according to the set address of the macro page.
Preferably, the macro page record table records whether each group has a page table entry, when the page table entry of a macro page is loaded into any group, the corresponding bit of the group in the macro page record table is set to 1, and when the group is accessed, the corresponding bit is cleared to 0 when the group finds that the macro page does not exist.
Preferably, in the fifth step, when the TLB is hit in the normal page manner, the page table entry of the normal page is returned, when the TLB is not hit in the normal page manner, and when the set address of the macro page is used to find the macro page record table, the address is resolved in the macro page manner and the TLB is accessed again, and after the hit, the page table entry of the macro page is returned.
Preferably, in the fifth step, when the TLB cannot be hit by the address resolution method of both the normal page and the macro page, it is determined that the TLB is missing.
Compared with the prior art, the invention has the beneficial effects that:
1. compared with the scheme of using the set-associative and the full-associative TLB, the invention uses only one full-associative TLB to simultaneously store page table entries of a normal page and a giant page, accesses the TLB for multiple times according to the mode of analyzing the normal page and the giant page for the address respectively, acquires the page table entries of the possible normal page and the giant page, and saves the chip area compared with the prior art.
2. The invention uses the huge page record table to filter unnecessary TLB access, and reduces the number of invalid accesses. The giant page record table records whether the giant page table entries possibly exist according to groups, and each group only needs one bit, so that the occupied area is small.
3. When the invention accesses the TLB of the group each time, the invention can judge whether the page table item of the giant page exists in the group or not by the way, and update the giant page record table in time.
Drawings
FIG. 1 is a schematic diagram of a macro page and a normal page mapping to a different set.
FIG. 2 is a block diagram of a set associative TLB in accordance with the present invention.
FIG. 3 is a flow chart of the internal TLB read process according to the present invention
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 2 and 3, the present invention provides a technical solution: the method for supporting the megapage in the set-associative TLB comprises the following technical flows:
in the first step, setting a group-associated TLB and a giant page record table for normal pages and giant pages, only using a unique group-associated TLB, storing page table entries of normal pages and giant pages in the group-associated TLB, recording whether each group has page table entries in the giant page record table, setting a corresponding bit in the giant page record table to be 1 when the page table entries of the giant pages are loaded into any group, and clearing a corresponding bit of 0 when the group is accessed to find that the group does not have the giant pages, wherein the giant page record table stores whether the group uses the giant pages according to the group address of the giant pages.
Secondly, accessing the TLB;
step three, firstly, accessing a group-associated TLB according to the group address and the TAG of a common page in the process of accessing;
fourth, accessing the macro page record table according to the group address of the macro page;
and fifthly, judging the access result of the TLB.
When the TLB is hit in the normal page mode, the page table item of the normal page is returned, when the TLB is not hit in the normal page mode, and when the set address of the macro page is used for searching the macro page record table to find the macro page, the address is resolved in the macro page mode and the TLB is accessed again, after the TLB is hit, the page table item of the macro page is returned, when the TLB is not hit in the address resolution modes of the normal page and the macro page, the TLB is determined to be missing
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (1)
1. The method for supporting the megapage in the set-associative TLB is characterized by comprising the following technical processes:
the first step, set up the set and associativity TLB and huge page record table to the ordinary page and huge page;
secondly, accessing the TLB;
step three, firstly, accessing a group-associated TLB according to the group address and the TAG of a common page in the process of accessing;
fourth, accessing the macro page record table according to the group address of the macro page;
fifthly, judging the access result of the TLB;
in the first step of operation, only a unique set associative TLB is used, and page table entries for both pages and megapages are typically held in the set associative TLB;
in the first step of operation, the macro page record table stores whether the macro page is used according to the group address of the macro page;
recording whether each group of page table entries exist in the giant page record table, setting the corresponding bit of the group in the giant page record table to be 1 when the page table entries of the giant page are loaded into any group, and clearing 0 when the group is accessed and the group is found that the giant page does not exist;
in the fifth step, when the TLB is hit in the normal page mode, the page table item of the normal page is returned, when the TLB is not hit in the normal page mode, and when the group address of the macro page is used for searching the macro page record table and the macro page is considered to exist, the address is resolved in the macro page mode and the TLB is accessed again, and after the TLB is hit, the page table item of the macro page is returned;
in the fifth step, when the TLB cannot be hit by the address resolution method of both the normal page and the macro page, it is determined that the TLB is missing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010464274.1A CN111666230B (en) | 2020-05-27 | 2020-05-27 | Method for supporting macro page in set associative TLB |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010464274.1A CN111666230B (en) | 2020-05-27 | 2020-05-27 | Method for supporting macro page in set associative TLB |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111666230A CN111666230A (en) | 2020-09-15 |
| CN111666230B true CN111666230B (en) | 2023-08-01 |
Family
ID=72385024
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010464274.1A Active CN111666230B (en) | 2020-05-27 | 2020-05-27 | Method for supporting macro page in set associative TLB |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111666230B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113360243B (en) * | 2021-03-17 | 2023-07-14 | 龙芯中科技术股份有限公司 | Device processing method, device, electronic device and readable medium |
| CN116225670A (en) * | 2021-12-02 | 2023-06-06 | 中兴通讯股份有限公司 | Memory management method, device and computer readable storage medium |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992022867A1 (en) * | 1991-06-17 | 1992-12-23 | Digital Equipment Corporation | Improving computer performance by simulated cache associativity |
| CN1124378A (en) * | 1994-04-19 | 1996-06-12 | 株式会社日立制作所 | Data processor |
| US6594750B1 (en) * | 1999-12-08 | 2003-07-15 | Ati International Srl | Method and apparatus for handling an accessed bit in a page table entry |
| US7330959B1 (en) * | 2004-04-23 | 2008-02-12 | Transmeta Corporation | Use of MTRR and page attribute table to support multiple byte order formats in a computer system |
| CN102184142A (en) * | 2011-04-19 | 2011-09-14 | 中兴通讯股份有限公司 | Method and device for reducing central processing unit (CPU) resource consumption by using giant page mapping |
| CN105760312A (en) * | 2010-09-24 | 2016-07-13 | 英特尔公司 | Apparatus, Method, And System For Implementing Micro Page Tables |
| CN107209715A (en) * | 2015-08-20 | 2017-09-26 | 华为技术有限公司 | File data accessing method and computer system |
| WO2019105566A1 (en) * | 2017-12-01 | 2019-06-06 | Huawei Technologies Co., Ltd. | Systems and methods for clustering sub-pages of physical memory pages |
| CN110688330A (en) * | 2019-09-23 | 2020-01-14 | 北京航空航天大学 | Virtual memory address translation method based on memory mapping adjacency |
| CN110990299A (en) * | 2020-03-03 | 2020-04-10 | 江苏华创微系统有限公司 | Non-regular group associative cache group address mapping method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10108550B2 (en) * | 2016-09-22 | 2018-10-23 | Google Llc | Memory management supporting huge pages |
-
2020
- 2020-05-27 CN CN202010464274.1A patent/CN111666230B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992022867A1 (en) * | 1991-06-17 | 1992-12-23 | Digital Equipment Corporation | Improving computer performance by simulated cache associativity |
| CN1124378A (en) * | 1994-04-19 | 1996-06-12 | 株式会社日立制作所 | Data processor |
| US6594750B1 (en) * | 1999-12-08 | 2003-07-15 | Ati International Srl | Method and apparatus for handling an accessed bit in a page table entry |
| US7330959B1 (en) * | 2004-04-23 | 2008-02-12 | Transmeta Corporation | Use of MTRR and page attribute table to support multiple byte order formats in a computer system |
| CN105760312A (en) * | 2010-09-24 | 2016-07-13 | 英特尔公司 | Apparatus, Method, And System For Implementing Micro Page Tables |
| CN102184142A (en) * | 2011-04-19 | 2011-09-14 | 中兴通讯股份有限公司 | Method and device for reducing central processing unit (CPU) resource consumption by using giant page mapping |
| CN107209715A (en) * | 2015-08-20 | 2017-09-26 | 华为技术有限公司 | File data accessing method and computer system |
| WO2019105566A1 (en) * | 2017-12-01 | 2019-06-06 | Huawei Technologies Co., Ltd. | Systems and methods for clustering sub-pages of physical memory pages |
| CN110688330A (en) * | 2019-09-23 | 2020-01-14 | 北京航空航天大学 | Virtual memory address translation method based on memory mapping adjacency |
| CN110990299A (en) * | 2020-03-03 | 2020-04-10 | 江苏华创微系统有限公司 | Non-regular group associative cache group address mapping method |
Non-Patent Citations (5)
| Title |
|---|
| A Low-Power Super-Performance Four-Way Set-Associative;Sun Hui等;《半导体学报》;20040408;第25卷(第4期);全文 * |
| Linux桌面环境下内存去重技术的研究与实现;周霄;《CNKI优秀硕士学位论文全文库》;20140215(第02期);全文 * |
| SPARC V8处理器中存储管理单元的设计;肖建青等;《科学技术与工程》;20101108(第31期);全文 * |
| 基于ARM9的高速缓存和内存管理单元的电路设计与实现;张巍;《CNKI优秀硕士学位论文全文库》;20140115;全文 * |
| 基于连续页面合并以及缓存的硬件载入技术;党倩;《现代电子技术》;20140801;第37卷(第15期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111666230A (en) | 2020-09-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7805588B2 (en) | Caching memory attribute indicators with cached memory data field | |
| US8082416B2 (en) | Systems and methods for utilizing an extended translation look-aside buffer having a hybrid memory structure | |
| US6442666B1 (en) | Techniques for improving memory access in a virtual memory system | |
| US8984254B2 (en) | Techniques for utilizing translation lookaside buffer entry numbers to improve processor performance | |
| US7793049B2 (en) | Mechanism for data cache replacement based on region policies | |
| EP2011010B1 (en) | Virtually-tagged instruction cache with physically-tagged behavior | |
| US6304944B1 (en) | Mechanism for storing system level attributes in a translation lookaside buffer | |
| US20070094476A1 (en) | Updating multiple levels of translation lookaside buffers (TLBs) field | |
| US20100185831A1 (en) | Semiconductor integrated circuit and address translation method | |
| CN111666230B (en) | Method for supporting macro page in set associative TLB | |
| WO2021061465A1 (en) | Address translation methods and systems | |
| US5778427A (en) | Method and apparatus for selecting a way of a multi-way associative cache by storing waylets in a translation structure | |
| US6446187B1 (en) | Virtual address bypassing using local page mask | |
| WO2021061446A1 (en) | Storage management apparatus, storage management method, processor, and computer system | |
| JP2002149490A (en) | Microprocessor and address converting method of microprocessor | |
| US6990551B2 (en) | System and method for employing a process identifier to minimize aliasing in a linear-addressed cache | |
| US8688952B2 (en) | Arithmetic processing unit and control method for evicting an entry from a TLB to another TLB | |
| CN111241012A (en) | TLB architecture supporting multi-level page tables | |
| CN111124954B (en) | Management device and method for two-stage conversion bypass buffering | |
| EP0486154B1 (en) | Method of operating a virtual memory system | |
| US6581139B1 (en) | Set-associative cache memory having asymmetric latency among sets | |
| US20210026770A1 (en) | Instruction cache coherence | |
| CN113076267A (en) | Address conversion method based on hotspot collection and data storage device | |
| JPH07117918B2 (en) | Data processing system | |
| MX2008005091A (en) | Caching memory attribute indicators with cached memory data |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |