CN101825997A - Asynchronous first-in first-out storage - Google Patents
Asynchronous first-in first-out storage Download PDFInfo
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Abstract
The invention provides an asynchronous first-in first-out storage, comprising a writing logic unit, a read logic unit and a data register, and also comprising a width acquiring unit, wherein the width acquiring unit is used for receiving a width selection signal and acquiring corresponding read-out width in a read-out width set according to the width selection signal; the read logic unit comprises a read-address generating unit for generating and outputting a read-address signal and a read-enable signal, and an address space of the read address is determined according to the capacity of the data register and the acquired read width; and the data register comprises an output control unit for controlling the data register to output data with the width of being the acquired read-out width from the read-address position when receiving the read-enable signal and the read-address signal. According to the asynchronous first-in first-out storage, data output with various widths can be realized, and data transmission of an asynchronous clock domain is more flexible and highly efficient.
Description
Technical field
The present invention relates to memory technology, particularly a kind of asynchronous first-in/first-out memory (FIFO) of supporting multiple different in width data transmission.
Background technology
In the types of applications of computing machine, the communications field, often need carry out the data transmission between the different clock-domains.If the transmission of multi-bit certificate, the data integrity when guaranteeing transmission between the asynchronous clock domain, a kind of method in common is to use asynchronous FIFO.Fig. 1 is the structural representation of the asynchronous FIFO of prior art, and the feature of this asynchronous FIFO is that read-write end clock zone separately is asynchronous fully.
With reference to Fig. 1, data enter metadata cache in writing clock zone, in reading clock zone, from metadata cache, read, do not write and read when guaranteeing metadata cache and can cause loss of data and repetition, the address pointer of read and write carries out clock zone respectively and passes through, writing logical block and reading respectively write address and the relative position of reading the address to be carried out logic in the logical block and compare then, whether the state of judging metadata cache according to comparative result is full or empty, when metadata cache is in full state, can not write, when metadata cache is in dummy status, can not read, so, realized the data buffer memory is carried out safe read-write.
Fig. 2 is the logical organization synoptic diagram of metadata cache in the asynchronous FIFO of prior art.With reference to Fig. 2, the capacity of metadata cache is t * n bit, and wherein, the data write width is n, and the spatial depth of read/write address is t, that is to say, the address pointer scope (0 to t-1) of read-write two ends logic is identical, and the width of data (n) is also consistent.
If data not only need to pass through asynchronous clock domain, and the width demand of read-write end data is inconsistent, and for example data width in a clock zone is n, need convert that width is m in another clock zone to, then need additionally to carry out the conversion of data width, synoptic diagram as shown in Figure 3.The input data could be imported the data width m that width n change output terminal into through also needing behind the asynchronous FIFO from the data of input end through a data width conversion process among Fig. 3.
For complicated more application system, if target data not only needs to pass through asynchronous clock domain, and output data may need the form of multiple width, for example data width in a clock zone is n, need convert that width is m or k in another clock zone to, then need additionally to carry out the conversion of several data width, and then multichannel selection output, synoptic diagram is as shown in Figure 4.The input data are carried out different data width conversion through dividing two-way behind the asynchronous FIFO among Fig. 4, select output through MUX then.MUX receives the width of outside input and selects signal, and for example, when described width selected signal to be " 0 ", the output width was the data of m, and when described width selected signal to be " 1 ", the output width was the data of k.
As seen, the read-write end data width of asynchronous FIFO is identical in the prior art, for realizing the data transmission of different in width, needs this asynchronous FIFO and width converter unit are carried out cascade; Support the output of multiple different in width data if desired, then need a plurality of width converter units of cascade, carry out multichannel then and select.The complex structure of this implementation, data transmission need be through repeatedly conversion and selection, and transfer efficiency is low, is unfavorable for the transmission of Large Volume Data.
Summary of the invention
Technical matters to be solved by this invention provides a kind of asynchronous first-in/first-out memory, to realize the data output of multiple width, makes the data transmission of asynchronous clock domain more flexible and efficient.
For solving the problems of the technologies described above, it is as follows to the invention provides technical scheme:
A kind of asynchronous first-in/first-out memory comprises and writes logical block, reads logical block and metadata cache, wherein, also comprises:
Width acquisition unit is used to receive width and selects signal, selects signal to obtain the corresponding width of reading from read the width set according to described width;
Described read to comprise in the logical block read address-generation unit, be used for producing and output is read address signal and read enable signal, the described address space of reading the address is determined according to the capacity of described metadata cache and the width of reading that is obtained;
Comprise output control unit in the described metadata cache, be used for describedly reading enable signal and when reading address signal receiving, control described metadata cache and read the address to export width be the data of being obtained of reading width from described.
Above-mentioned asynchronous first-in/first-out memory, wherein, described writing in the logical block comprises:
First address conversioning unit is used in writing clock zone, and write address is converted to the bit addresses of writing that characterizes the bit position, will read address translation for characterizing the bit addresses of reading of bit position;
Full scale will generation unit is used for writing bit addresses and reading bit addresses and compare at the relative position of described metadata cache described, produces full scale will according to comparative result.
Above-mentioned asynchronous first-in/first-out memory, wherein, described first address conversioning unit is further used for, in writing clock zone, with write address with write width and multiply each other, obtain writing bit addresses, multiply each other with the width of reading that is obtained reading the address, obtain reading bit addresses.
Above-mentioned asynchronous first-in/first-out memory, wherein, described full scale will generation unit is further used for, when the described bit addresses of writing equates with the described bit addresses of reading, and described equate be since described write bit addresses from after caught up with describedly when reading bit addresses and causing, produce full scale will.
Above-mentioned asynchronous first-in/first-out memory, wherein, described reading comprises in the logical block:
Second address conversioning unit is used in reading clock zone, and write address is converted to the bit addresses of writing that characterizes the bit position, will read address translation for characterizing the bit addresses of reading of bit position;
Empty sign generation unit, be used for to described write bit addresses and read bit addresses compare at the relative position of described metadata cache, produce empty sign according to comparative result.
Above-mentioned asynchronous first-in/first-out memory, wherein, described second address conversioning unit is further used for, in reading clock zone, with write address with write width and multiply each other, obtain writing bit addresses, multiply each other with the width of reading that is obtained reading the address, obtain reading bit addresses.
Above-mentioned asynchronous first-in/first-out memory, wherein, described empty sign generation unit is further used for, when the described bit addresses of writing equates with the described bit addresses of reading, and described equate be since described read bit addresses from after caught up with describedly when writing bit addresses and causing, produce empty sign.
Above-mentioned asynchronous first-in/first-out memory, wherein, the capacity of described metadata cache is to write width and described all that comprise in the width set of reading are read the common multiple of width.
Above-mentioned asynchronous first-in/first-out memory, wherein, described metadata cache is the dual-ported memory of single-bit visit.
The present invention is by allowing the read-write logical timer domain addresses pointer of asynchronous FIFO distinguish corresponding different metadata cache address spaces, can allow fan-out factor according to being multiple width, overcome and designed the fixing restriction of asynchronous FIFO read-write two ends data width in the past, can when passing through, asynchronous clock carry out the conversion of data different in width, thereby simplified system design, improved the efficient of data transmission.
Description of drawings
Fig. 1 is the structural representation of the asynchronous FIFO of prior art;
Fig. 2 is the logical organization synoptic diagram of metadata cache in the asynchronous FIFO of prior art;
Fig. 3 is for carrying out a kind of implementation synoptic diagram of data width conversion in the prior art;
Fig. 4 is for carrying out the another kind of implementation synoptic diagram of data width conversion in the prior art;
Fig. 5 is the structural representation of the asynchronous FIFO of the embodiment of the invention;
Fig. 6 is the detailed structure synoptic diagram of the asynchronous FIFO of the embodiment of the invention;
Fig. 7 is the logical organization synoptic diagram of metadata cache in the asynchronous FIFO of the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, describe the present invention below in conjunction with the accompanying drawings and the specific embodiments.
With reference to Fig. 5, mainly comprise in the asynchronous FIFO of the embodiment of the invention: write logical block, read logical block, metadata cache and width acquisition unit, wherein:
Described width acquisition unit is used to receive width and selects signal, selects signal to obtain the corresponding width (index is read the end data width according to buffer memory) of reading from read the width set according to described width.Describedly read width set and alternatively read the set that width constitutes for what set in advance, it is the signal of outside input that described width is selected signal, store signal value and the corresponding relation of reading width in the width acquisition unit, for example, when signal is " 0 ", representing width is m, and when signal was " 1 ", representing width was k.Need to prove,, in specific implementation, also can write logical block, read to be provided with respectively in logical block and the metadata cache width acquisition unit though the width acquisition unit among Fig. 5 is arranged on and writes logical block, reads outside logical block and the metadata cache.
Described writing comprises the write address generation unit in the logical block, be used for generation and write address output signal and write enable signal.In the present invention, the end data width (being referred to as to write width) that writes of metadata cache is fixed, and for example, writes width and is set to n, and the address space of write address is determined according to the capacity and the said write width of described metadata cache.Specifically, whenever carry out write operation one time, write address increases by 1, after write address is increased to maximal value in the write address space, again since 0 counting.
Described metadata cache receives described when writing enable signal and writing address signal, and receiving width is the data of said write width, and with the data storage that the receives position in write address correspondence described in the notebook data buffer memory.
Described read to comprise in the logical block read address-generation unit, be used for producing and output is read address signal and read enable signal, the described address space of reading the address is determined according to the capacity of described metadata cache and the width of reading that is obtained.In the present invention, read the address space of address and do not fix, but read the width difference and different according to what obtain, this just makes the read/write address pointer can distinguish corresponding different metadata cache address spaces.Specifically, whenever carry out a read operation, reading the address increases by 1, reads after the address is increased to the maximal value of reading in the address space, again since 0 counting.
Comprise output control unit in the described metadata cache, be used for describedly reading enable signal and when reading address signal receiving, control described metadata cache and read the address to export width be the data of being obtained of reading width from described.As seen, in the present invention, the fan-out factor that can allow metadata cache is according to being multiple width, overcome and designed the fixing restriction of asynchronous FIFO read-write two ends data width in the past, can when passing through, asynchronous clock carry out the conversion of data different in width, thereby simplified system design, improved the efficient of data transmission.
In addition, in order to realize the output of different pieces of information width, require metadata cache support read-write bitwise, that is, described metadata cache is the dual-ported memory (for example, dual port RAM) of single-bit visit.
Further,, also need sky/full state to judge, when metadata cache is in full state, can not write, when metadata cache is in dummy status, can not read the data buffer memory in order to realize that the data buffer memory is carried out safe read-write.Because the read/write address pointer among the present invention may be distinguished corresponding different metadata cache address spaces, directly to described read/write address pointer compare can not the specified data buffer memory state whether be full or empty.Therefore, in the asynchronous FIFO of following embodiment, after read/write address being converted to the address that characterizes the bit position (that is, the address correspondence after the conversion be the position of 1 Bit data in metadata cache), compare again, come the sky/full state of specified data buffer memory.
Fig. 6 is the detailed structure synoptic diagram of the asynchronous FIFO of the embodiment of the invention, with reference to Fig. 6, mainly comprises in the described asynchronous FIFO: write logical block, read logical block and metadata cache, wherein:
Describedly write logical block, read to be provided with width acquisition unit in logical block and the metadata cache, described width acquisition unit is used to receive width and selects signal, selects signal to obtain the corresponding width (index is read the end data width according to buffer memory) of reading from read the width set according to described width.Describedly read width set and alternatively read the set that width constitutes for what set in advance, it is the signal of outside input that described width is selected signal, store signal value and the corresponding relation of reading width in the width acquisition unit, for example, when signal is " 0 ", representing width is m, and when signal was " 1 ", representing width was k.
Described writing also comprises write address generation unit, first address conversioning unit and full scale will generation unit in the logical block.
Described write address generation unit is used for generation and write address output signal and writes enable signal.In the present invention, the end data width (being referred to as to write width) that writes of metadata cache is fixed, and for example, writes width and is set to n, and the address space of write address is determined according to the capacity and the said write width of described metadata cache.Specifically, whenever carry out write operation one time, write address increases by 1, after write address is increased to maximal value in the write address space, again since 0 counting.
Described first address conversioning unit is used in writing clock zone, and write address is converted to the bit addresses of writing that characterizes the bit position, will read address translation for characterizing the bit addresses of reading of bit position.Particularly, be in writing clock zone, with write address with write width and multiply each other, obtain writing bit addresses, multiply each other with the width of reading that is obtained reading the address, obtain reading bit addresses.
Described full scale will generation unit is used for writing bit addresses and reading bit addresses and compare at the relative position of described metadata cache described, produces full scale will according to comparative result.Particularly, when the described bit addresses of writing equates with the described bit addresses of reading, and described equate be since described write bit addresses from after caught up with describedly when reading bit addresses and causing, produce full scale will.Read the address as for how determining that write address has been caught up with, still read the address and caught up with write address, there is multiple implementation in the prior art, now provide a kind of implementation wherein: be respectively and read the address and write address is provided with a zone bit, when reading address or write address again when 0 counts, with the zone bit negate of correspondence, promptly, become 1 by 0, perhaps, become 0 by 1; When the described bit addresses of writing when reading bit addresses and equating, judges whether these two zone bits equate with described, if, illustrate that reading bit addresses has caught up with and write bit addresses, if not, illustrate that then writing bit addresses has caught up with and read bit addresses.
Described metadata cache receives described when writing enable signal and writing address signal, and receiving width is the data of said write width, and with the data storage that the receives position in write address correspondence described in the notebook data buffer memory.
Described reading also comprises in the logical block: read address-generation unit, second address conversioning unit and empty sign generation unit.
The described address-generation unit of reading is used for producing and output is read address signal and read enable signal, and the described address space of reading the address is determined according to the capacity of described metadata cache and the width of reading that is obtained.In the present invention, read the address space of address and do not fix, but read the width difference and different according to what obtain, this just makes the read/write address pointer can distinguish corresponding different metadata cache address spaces.Specifically, whenever carry out a read operation, reading the address increases by 1, reads after the address is increased to the maximal value of reading in the address space, again since 0 counting.
Described second address conversioning unit is used in reading clock zone, and write address is converted to the bit addresses of writing that characterizes the bit position, will read address translation for characterizing the bit addresses of reading of bit position.Particularly, be in reading clock zone, with write address with write width and multiply each other, obtain writing bit addresses, multiply each other with the width of reading that is obtained reading the address, obtain reading bit addresses.
Described empty sign generation unit, be used for to described write bit addresses and read bit addresses compare at the relative position of described metadata cache, produce empty sign according to comparative result.Particularly, when the described bit addresses of writing equates with the described bit addresses of reading, and described equate be since described read bit addresses from after caught up with describedly when writing bit addresses and causing, produce empty sign.
Also comprise output control unit in the described metadata cache, be used for describedly reading enable signal and when reading address signal receiving, control described metadata cache and read the address to export width be the data of being obtained of reading width from described.As seen, in the present invention, the fan-out factor that can allow metadata cache is according to being multiple width, overcome and designed the fixing restriction of asynchronous FIFO read-write two ends data width in the past, can when passing through, asynchronous clock carry out the conversion of data different in width, thereby simplified system design, improved the efficient of data transmission.
Need to prove,, also can not need produce sky and/or full scale will by asynchronous FIFO if enough big with the capacity setting of metadata cache perhaps, externally controlled read-write data speed.
Preferably, in asynchronous FIFO shown in Figure 6, the capacity of employed metadata cache should be and writes width and described all that comprise in the width set of reading are read the common multiple of width, otherwise, will cause losing of transmission data.
Fig. 7 is the logical organization synoptic diagram of metadata cache in the asynchronous FIFO of the embodiment of the invention.With reference to Fig. 7, in this embodiment, the input data width is n, and the output data width is m or k, and m or k can be not equal to n, and the capacity of metadata cache is n * m * k bit.In writing logical block, address space is 0 to m * k-1, and each data width is n.In reading logical block, when width selects signal to equal " 0 ", the metadata cache address space is considered as 0 to n * k-1, each data width is m; When width selects signal to equal " 1 ", the metadata cache address space is considered as 0 to n * m-1, each data width is k.
Because write address and to read the address valid value range different, writing logical block and reading to carry out in the logical block sky/when completely judging, they need be converted to the address of sign bit.Particularly, be that write address is taken advantage of n, the address be will read and m (when width is selected signal=" 0 ") or k (when width is selected signal=" 1 ") multiply by, just obtain the particular location (position of each data bit) in the same metadata cache of their correspondences, can carry out logic then and relatively produce sky/full scale will.
Above-mentioned metadata cache capacity is a kind of selection, can select the arbitrary integer times (that is the common multiple of n, m, k) of the lowest common multiple of n, m, k in addition.
In the foregoing description, alternative output data width is 2 kinds, but the invention is not restricted to this, also can realize the selection of any multiple output data width, for example: alternative output data width is set to 4 kinds, and it then is " 00 ", " 01 ", " 10 ", " 11 " that corresponding width is selected signal.
In sum, utilize the technique scheme of the embodiment of the invention, for data transfer among asynchronous clock domains, this asynchronous FIFO and width converter unit need not be carried out cascade, just can change the width of fan-out factor certificate, and can realize the data output of multiple width, make the data transmission of asynchronous clock domain more flexible and efficient.
Should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from the spiritual scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (9)
1. asynchronous first-in/first-out memory comprises and writes logical block, reads logical block and metadata cache, it is characterized in that, also comprises:
Width acquisition unit is used to receive width and selects signal, selects signal to obtain the corresponding width of reading from read the width set according to described width;
Described read to comprise in the logical block read address-generation unit, be used for producing and output is read address signal and read enable signal, the described address space of reading the address is determined according to the capacity of described metadata cache and the width of reading that is obtained;
Comprise output control unit in the described metadata cache, be used for describedly reading enable signal and when reading address signal receiving, control described metadata cache and read the address to export width be the data of being obtained of reading width from described.
2. asynchronous first-in/first-out memory as claimed in claim 1 is characterized in that, described writing in the logical block comprises:
First address conversioning unit is used in writing clock zone, and write address is converted to the bit addresses of writing that characterizes the bit position, will read address translation for characterizing the bit addresses of reading of bit position;
Full scale will generation unit is used for writing bit addresses and reading bit addresses and compare at the relative position of described metadata cache described, produces full scale will according to comparative result.
3. asynchronous first-in/first-out memory as claimed in claim 2 is characterized in that:
Described first address conversioning unit is further used for, in writing clock zone, with write address with write width and multiply each other, obtain writing bit addresses, multiply each other with the width of reading that is obtained reading the address, obtain reading bit addresses.
4. asynchronous first-in/first-out memory as claimed in claim 3 is characterized in that:
Described full scale will generation unit is further used for, when the described bit addresses of writing equates with the described bit addresses of reading, and described equate be since described write bit addresses from after caught up with describedly when reading bit addresses and causing, produce full scale will.
5. asynchronous first-in/first-out memory as claimed in claim 1 is characterized in that, described reading comprises in the logical block:
Second address conversioning unit is used in reading clock zone, and write address is converted to the bit addresses of writing that characterizes the bit position, will read address translation for characterizing the bit addresses of reading of bit position;
Empty sign generation unit, be used for to described write bit addresses and read bit addresses compare at the relative position of described metadata cache, produce empty sign according to comparative result.
6. asynchronous first-in/first-out memory as claimed in claim 5 is characterized in that:
Described second address conversioning unit is further used for, in reading clock zone, with write address with write width and multiply each other, obtain writing bit addresses, multiply each other with the width of reading that is obtained reading the address, obtain reading bit addresses.
7. asynchronous first-in/first-out memory as claimed in claim 6 is characterized in that:
Described empty sign generation unit is further used for, when the described bit addresses of writing equates with the described bit addresses of reading, and described equate be since described read bit addresses from after caught up with describedly when writing bit addresses and causing, produce sky and indicate.
8. as claim 4 or 7 described asynchronous first-in/first-out memories, it is characterized in that:
The capacity of described metadata cache is to write width and described all that comprise in the width set of reading are read the common multiple of width.
9. asynchronous first-in/first-out memory as claimed in claim 1 is characterized in that:
Described metadata cache is the dual-ported memory of single-bit visit.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102508631A (en) * | 2011-09-26 | 2012-06-20 | 福建星网锐捷网络有限公司 | Written data processing device of first input first output (FIFO) for writing any byte data |
| CN106502922A (en) * | 2016-10-28 | 2017-03-15 | 上海顺久电子科技有限公司 | A kind of data read-write method of data fifo buffer and data buffer |
| CN106919363A (en) * | 2015-12-28 | 2017-07-04 | 北京航天测控技术有限公司 | A kind of SDRAM buffers based on asynchronous first in first out |
| WO2020118713A1 (en) * | 2018-12-14 | 2020-06-18 | 深圳市汇顶科技股份有限公司 | Bit width matching circuit, data writing apparatus, data reading apparatus, and electronic device |
| CN113485647A (en) * | 2021-07-13 | 2021-10-08 | 湖南国科微电子股份有限公司 | Data writing method, data reading method and first-in first-out memory |
| CN115357095A (en) * | 2022-10-19 | 2022-11-18 | 中科声龙科技发展（北京）有限公司 | Asynchronous signal processing method and structure |
| CN116431099A (en) * | 2023-06-13 | 2023-07-14 | 摩尔线程智能科技(北京)有限责任公司 | Data processing method, multi-input-output queue circuit and storage medium |
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- 2010-01-28 CN CN201010102972A patent/CN101825997A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102508631A (en) * | 2011-09-26 | 2012-06-20 | 福建星网锐捷网络有限公司 | Written data processing device of first input first output (FIFO) for writing any byte data |
| CN102508631B (en) * | 2011-09-26 | 2014-07-30 | 福建星网锐捷网络有限公司 | Written data processing device of first input first output (FIFO) for writing any byte data |
| CN106919363A (en) * | 2015-12-28 | 2017-07-04 | 北京航天测控技术有限公司 | A kind of SDRAM buffers based on asynchronous first in first out |
| CN106502922A (en) * | 2016-10-28 | 2017-03-15 | 上海顺久电子科技有限公司 | A kind of data read-write method of data fifo buffer and data buffer |
| CN106502922B (en) * | 2016-10-28 | 2020-02-18 | 青岛海信电器股份有限公司 | Data reading and writing method of FIFO data buffer and data buffer |
| CN111566614A (en) * | 2018-12-14 | 2020-08-21 | 深圳市汇顶科技股份有限公司 | Bit width matching circuit, data writing device, data reading device, and electronic device |
| WO2020118713A1 (en) * | 2018-12-14 | 2020-06-18 | 深圳市汇顶科技股份有限公司 | Bit width matching circuit, data writing apparatus, data reading apparatus, and electronic device |
| CN111566614B (en) * | 2018-12-14 | 2023-09-08 | 深圳市汇顶科技股份有限公司 | Bit width matching circuit, data writing device, data reading device, and electronic apparatus |
| CN113485647A (en) * | 2021-07-13 | 2021-10-08 | 湖南国科微电子股份有限公司 | Data writing method, data reading method and first-in first-out memory |
| CN115357095A (en) * | 2022-10-19 | 2022-11-18 | 中科声龙科技发展（北京）有限公司 | Asynchronous signal processing method and structure |
| CN115357095B (en) * | 2022-10-19 | 2023-01-24 | 中科声龙科技发展（北京）有限公司 | Asynchronous signal processing method and structure |
| WO2024082497A1 (en) * | 2022-10-19 | 2024-04-25 | 声龙(新加坡)私人有限公司 | Asynchronous signal processing method and structure |
| CN116431099A (en) * | 2023-06-13 | 2023-07-14 | 摩尔线程智能科技(北京)有限责任公司 | Data processing method, multi-input-output queue circuit and storage medium |
| CN116431099B (en) * | 2023-06-13 | 2023-09-19 | 摩尔线程智能科技(北京)有限责任公司 | Data processing method, multi-input-output queue circuit and storage medium |
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