CN206431615U - A kind of fifo controller of multichannel read-write multicapacity selection - Google Patents
A kind of fifo controller of multichannel read-write multicapacity selection Download PDFInfo
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Abstract
The utility model is related to a kind of fifo controller of multichannel read-write multicapacity selection, belongs to the technical field of digital integrated electronic circuit.Controller includes：Fifo control circuit, user SRAM read-write control circuits, address decoding circuitry, multiplexer circuit, SRAM memory bank circuits.The controller distributes current FIFO capacity according to system input capacity selection signal, carry out dividing the data space for obtaining the similar FIFO operations of each user equipment to removing the SRAM memory banks circuit after FIFO space-consumings, FIFO read-write operation and the similar FIFO of system selected user equipment operations according to selected by the selection signal completion system that address decoding circuitry is exported, it is optional that FIFO capacity is realized using same Large Copacity SRAM, and with the unappropriated SRAM address spaces of miscellaneous equipment share and access FIFO, incorporate full chip SRAM memory banks, improve resource utilization.
Description
Technical field
The utility model is related to a kind of fifo controller of multichannel read-write multicapacity selection, belongs to the skill of digital integrated electronic circuit
Art field.
Background technology
FIFO（First In First Out）, i.e. the abbreviation of push-up storage, in system design, in order to increase
Data transmission problems between message transmission rate, mass disposal data flow, solution different clocks domain system, it is usually used
FIFO memory.
Common FIFO memory typically has two kinds of constituted modes：One kind is made up of shift register array, another
It is to be made up of the two-port RAM with reading and write address pointer.The clock zone worked according to FIFO, again can be by FIFO memory
It is divided into synchronization fifo and the class of asynchronous FIFO two, synchronization fifo refers to read clock and writes clock for same clock, and asynchronous FIFO
Refer to that it is two mutual independent clocks to read clock and write clock.FIFO use widely, wherein again to be made up of SRAM
The more compact practicalities of FIFO, the utility model proposes to improve primarily directed to the FIFO being made up of SRAM.
In realization is typically designed, one piece of SRAM is only used for realizing a FIFO, and monolithic SRAM capacity is generally used for
The FIFO of caching capacity is much bigger, then, the SRAM of Large Copacity only realizes that a FIFO can waste remaining deposit
Store up space.When especially SRAM application demands are more or need the design requirements such as multiple capacity different FIFO, multiple SRAM are remained
Remaining waste of storage space is more serious, and resource utilization is also than relatively low.
Utility model content
Goal of the invention of the present utility model is to be directed to the not enough of above-mentioned background technology to read and write multicapacity there is provided a kind of multichannel
The fifo controller of selection, realizes being adjusted flexibly for FIFO capacity and making full use of for the remaining memory bank spaces of SRAM, solves
One piece of SRAM determined only to realize that a FIFO has the low technical problem of resource utilization.
The utility model is adopted the following technical scheme that for achieving the above object：
A kind of fifo controller of multichannel read-write multicapacity selection, including：
Fifo control circuit, current FIFO capacity is distributed according to system input capacity selection signal, is adjusted current FIFO and is read
Address signal and current FIFO writing address signals,
User's SRAM read-write control circuits, receive the current FIFO capacity indication signal of fifo control circuit output, according to
SRAM memory banks circuit removes the read-write that the residual capacity after current FIFO capacity distributes similar FIFO operations for each user equipment
Address,
Address decoding circuitry, current FIFO and user equipment according to selected by system equipment address signal exports sign system
Selection signal,
Multiplexer circuit, the current FIFO for receiving fifo control circuit output reads address signal and current FIFO write addresses
Signal, the read/write address of the similar FIFO operations of each user equipment of user SRAM read-write control circuits output, address decoding circuitry
The selection signal of output, the similar FIFO behaviour of current FIFO read-write operation and system selected user equipment selected by completion system
Make, and,
SRAM memory bank circuits, with the current FIFO memory banks space and each user divided according to current FIFO capacity
The data back space of the similar FIFO operations of equipment.
Read and write the further prioritization scheme of the fifo controller of multicapacity selection as multichannel, similar FIFO operation include but
It is not limited to RAM read-write operations, stack manipulation.
The further prioritization scheme of the fifo controller of multicapacity selection is read and write as multichannel, fifo control circuit includes：
FIFO Capacity Selection circuits, the system input capacity selection signal received according to its input and SRAM memory banks
The threshold value in different bank space selects current FIFO capacity in circuit,
Current length signal generating circuit, according to the numerical relation of the value of current length signal and current FIFO capacity,
FIFO writes data and enables signal, FIFO reading data enable signals, and foundation prevents Writing overflow from adjusting current length with the principle for reading sky
The value of signal,
Read address signal generation circuit, carry out FIFO read operations during, according to current FIFO read address signal with
The numerical relation of current FIFO capacity adjusts the value that current FIFO reads address signal, and,
Writing address signal generation circuit, address signal sum and current FIFO are read according to current length signal and current FIFO
The numerical relation of capacity adjusts current FIFO writing address signals.
Further, the FIFO Capacity Selection circuits in the fifo controller of multichannel read-write multicapacity selection pass through multichannel
Selector realizes that the threshold value in different bank space in the input input SRAM memory bank circuits of MUX, multichannel is selected
The selection terminating systems input capacity selection signal of device is selected, MUX exports current FIFO capacity.
Further, the current length signal generating circuit in the fifo controller of multichannel read-write multicapacity selection：
FIFO write data enable signal effectively and current length signal value in current FIFO ranges of capacity when, to current length signal
Value add a carry out FIFO write operations, otherwise, FIFO read data enable signal effectively and current length signal value be more than zero
Carry out FIFO read operations that when subtracts one to the value of current length signal.
Further, the current length signal generating circuit bag in the fifo controller of multichannel read-write multicapacity selection
Include：Two alternative data selectors and d type flip flop,
First alternative data selector, it is effective that it selects input FIFO reading data enable signal reading data in end to enable signal
And current length signal value is more than 0 logic discriminant, its 1 input inputs the value that current length signal subtracts one,
Second alternative data selector, it selects end input FIFO write enable signals effectively and current length signal value exists
Logic discriminant in current FIFO ranges of capacity, the value that its 1 input input current length signal adds one, its 0 input termination
The output end of first alternative data selector,
D type flip flop, it inputs the output end of the second alternative data selector of termination, and it exports the first alternative number of termination
According to 0 input of selector.
Further, the reading address signal generation circuit in the fifo controller of multichannel read-write multicapacity selection：
Data enable signal is read in FIFO effectively and current length signal is more than in the case of 0：Current FIFO reads address letter
When number in current FIFO ranges of capacity, read current FIFO address signal and carry out Jia one operation, until current FIFO readings address
When signal exceeds current FIFO ranges of capacity, address signal is read to current FIFO and carries out rezero operation；Keep working as in the case of remaining
It is constant that preceding FIFO reads address signal.
Further, the reading address signal generation circuit in the fifo controller of multichannel read-write multicapacity selection includes：
Two alternative data selectors and d type flip flop,
First alternative data selector, it selects end to input current FIFO and reads address signal equal to current FIFO capacity
Logic discriminant, its 0 input inputs current FIFO and reads the value that address signal adds one, and its 1 input inputs 0,
Second alternative data selector, it selects end input FIFO reading data enables signal effectively and current length signal
Logic discriminant more than 0, the output end of its 1 input the first alternative data selector of termination,
D type flip flop, it inputs the output end of the second alternative data selector of termination, and it exports the second alternative number of termination
According to 0 input of selector.
Further, the writing address signal generation circuit in the fifo controller of multichannel read-write multicapacity selection：
When current length signal reads address signal sum in current FIFO ranges of capacity with current FIFO, with current length
Signal and current FIFO read address signal and be current FIFO writing address signals,
When current length signal reads address signal sum beyond current FIFO ranges of capacity with current FIFO, by current length
The value that signal and current FIFO read to subtract current FIFO capacity again after address signal is cumulative assigns current FIFO writing address signals.
Further, the writing address signal generation circuit in the fifo controller of multichannel read-write multicapacity selection passes through one
Alternative data selector realizes that selection end input current length signal and the current FIFO of the alternative data selector read ground
Location signal sum is more than the logic discriminant of current FIFO capacity, and the 0 input input of the alternative data selector is current long
Spend signal and current FIFO and read address signal sum, the 1 input input current length signal of the alternative data selector and
Current FIFO reads to subtract the value of current FIFO capacity after address signal is cumulative again.
The utility model uses above-mentioned technical proposal, has the advantages that：FIFO is distributed by fifo control circuit
Capacity simultaneously distributes SRAM read/write address for the current FIFO operations of system, passes through user SRAM read-write control circuits and address decoding electricity
The design on road realizes other unappropriated SRAM address spaces of user equipment share and access FIFO, and sram chip can be adjusted flexibly
The division in memory bank space simultaneously makes full use of the SRAM address spaces not taken by FIFO, has effectively integrated SRAM memory banks, has carried
High resource utilization.
Brief description of the drawings
Fig. 1 is the system block diagram for the fifo controller that the utility model is related to.
Fig. 2 is the block diagram of FIFO Capacity Selection circuits.
Fig. 3 is the block diagram for reading address signal generation circuit.
Fig. 4 is the block diagram of current length signal generating circuit.
Fig. 5 is the block diagram of writing address signal generation circuit.
Label declaration in figure：101st, fifo control circuit, 102, user's SRAM read-write control circuits, 103, address decoding electricity
Road, 104, multiplexer circuit, 105, SRAM memory bank circuits.
Embodiment
The technical scheme to utility model is described in detail below in conjunction with the accompanying drawings.
The fifo controller of multichannel that the utility model is related to read-write multicapacity selection as shown in figure 1, including：FIFO is controlled
Circuit 101, user SRAM read-write control circuits 102, address decoding circuitry 103, multiplexer circuit 104 and SRAM memory banks
Circuit 105.
Fifo control circuit 101：Current FIFO capacity is selected according to system input capacity selection signal fifo_size, held
Amount instruction signal is depth, output capacity indication signal depth to user SRAM read-write control circuits 102；FIFO is write into number
Fifo_din is output to according to wr_din；FIFO is write into data enable signal wr_en and is output to fifo_wr；FIFO readings data are made
Energy signal rd_en is output to fifo_rd；In addition, fifo control circuit 101 exports the reading address signal fifo_raddr to SRAM
（I.e. current FIFO reads address signal）With writing address signal fifo_waddr（I.e. current FIFO writing address signals）.The above 5 is defeated
Go out signal and be output to multiplexer circuit 104.
User SRAM read-write control circuits 102, are made up of multiple User Defined SRAM read-write control circuits, input FIFO
The capacity indication signal depth for controlling circuit 101 to produce.Herein according to SRAM remaining space sizes, expansible N number of SRAM read-writes
Control submodule user1_ctr1 to userN_ctr1, first submodule output write-in data user1_din, reads address signal
User1_raddr, writing address signal user1_waddr, read data and enable signal user1_rd, write data and enable signal user1_
wr.The like, n-th submodule output write-in data userN_din reads address signal userN_raddr, writing address signal
UserN_waddr, reads data and enables signal userN_rd, writes data and enables signal userN_wr.Above signal is output to many
Road selection circuit 104.
Address decoding circuitry 103, is inputted as system equipment address signal dev_addr, to system equipment address signal dev_
Output multi-channel selection signal sel is to multiplexer circuit 104, the multi-path choice characterization system after the processing of addr address decodings
Selected current FIFO and user equipment.
Multiplexer circuit 104, inputs the 5 tunnel control signals exported for fifo control circuit 101, user SRAM read-write controls
The multi-path choice signal sel that the N roads signal and address decoding circuitry 103 that circuit 102 processed is exported are exported, meanwhile, export SRAM
Write data signal din, SRAM read address signal raddr, and SRAM write address signal waddr, SRAM read data enable signal rd,
SRAM write data enable signal wr, the tunnel signal output of the above 5 to SRAM memory banks circuit 105.
SRAM memory banks circuit 105 is according to current FIFO capacity and the similar FIFO read-writes of user's SRAM read-write control circuits
The memory bank space of address distribution, inputs SRAM write data-signal din, the SRAM exported for multiplexer circuit 104 and reads address
Signal raddr, SRAM write address signal waddr, SRAM read data and enable signal rd, SRAM write data enable signal wr, output
For SRAM reading data signals dout.Fifo space are current FIFO memory banks space, user1 space to userN space
For the data back space of the similar FIFO operations of each user equipment, similar FIFO operations include RAM read-write operations, storehouse behaviour
Make etc..
Fifo control circuit 101 is produced by FIFO Capacity Selections circuit, reading address signal generation circuit, current length signal
Circuit and writing address signal generation circuit are constituted.
FIFO Capacity Selections circuit according to system input capacity selection signal fifo_size as shown in Fig. 2 determine current
FIFO capacity depth.FIFO Capacity Selections circuit can realize that the input of MUX is inputted by a MUX
The threshold value Threshold_1 to Threshold_n in different bank space in SRAM memory banks circuit 105, MUX
Terminating systems input capacity selection signal fifo_size is selected, MUX exports current FIFO capacity depth.
Read address signal generation circuit as shown in Figure 3：When FIFO reading data enable signals rd_en is effective, current length letter
When number len_addr is more than zero and current FIFO and reads address signal r_addr and be not equal to depth-1, address letter is read current FIFO
Number r_addr adds a carry out read operation, until FIFO reads address signal r_addr when being equal to depth-1, FIFO reads address signal r_
Addr is zeroed out；FIFO reads address signal r_addr and keeps constant in the case of other.Reading address signal generation circuit specifically can be by
Two alternative data selectors and d type flip flop realization, the selection end input logic discriminate of the first alternative data selector：
R_addr==(depth-1), the 0 input input r_addr+1 of the first alternative data selector, the choosing of the first alternative data
Select the 1 input input 0 of device, the selection end input logic discriminate of the second alternative data selector：rd_en&&(len_
addr>0), the output end of 1 input the first alternative data selector of termination of the second alternative data selector, d type flip flop
The output end of input the second alternative data selector of termination, the 0 of output the second alternative data selector of termination of d type flip flop
Input.
Current length signal generating circuit is as shown in Figure 4：When FIFO writes, data enable signal wr_en is effective and FIFO is current
When length signals len_addr is less than current FIFO capacity depth, FIFO current length signals len_addr adds one；Otherwise, when
When FIFO reading data enable signals rd_en is effectively and FIFO current length signals len_addr is more than zero, FIFO current lengths letter
Number len_addr subtracts one.Current length signal generating circuit is specific to be realized by two alternative data selectors and d type flip flop, the
The selection end input logic discriminate of one alternative data selector：rd_en&&(len_addr>0), the first alternative data are selected
Select the 1 input input len_addr-1 of device, the selection end input logic discriminate of the second alternative data selector：wr_
en&&( len_addr<Depth), the 1 input input len_addr+1 of the second alternative data selector, the second alternative
The output end of 0 input the first alternative data selector of termination of data selector, the input of d type flip flop terminates the second alternative
The output end of data selector, 0 input of output the first alternative data selector of termination of d type flip flop.
Writing address signal generation circuit is as shown in Figure 5：When FIFO current length signals len_addr is plus reading address signal
When r_addr is more than depth-1, FIFO write addresses w_addr is equal to FIFO current length signals len_addr and reads ground plus FIFO
Location signal r_addr's and subtract FIFO and currently select capacity depth；Otherwise, FIFO write addresses w_addr is currently long equal to FIFO
Spend the sum that signal len_addr reads address signal r_addr plus FIFO.Writing address signal generation circuit can specifically pass through one or two choosings
The realization of one data selector, the selection end input logic discriminate of the alternative data selector：len_addr>( depth-1-
R_addr), 0 input of the alternative data selector inputs len_addr+ r_addr, the 1 of the alternative data selector
Input input len_addr+ r_addr-depth.
Read-write operation control and the control of read/write address for fifo control circuit 101 to SRAM memory banks above
Journey, read-write operation control of the user SRAM read-write control circuits 102 to SRAM memory banks can be accessed directly.If by user
Submodule example inside SRAM read-write control circuits 102 turns to fifo control circuit, then the utility model can be realized multiple
FIFO shares same SRAM, and this scheme can be considered a kind of expansion deformation scheme of the present utility model, other similar expansion deformations
Scheme should should also be included in protection domain of the present utility model.
Claims (10)
1. a kind of fifo controller of multichannel read-write multicapacity selection, it is characterised in that including：
Fifo control circuit（101）, current FIFO capacity is distributed according to system input capacity selection signal, current FIFO is adjusted and reads
Address signal and current FIFO writing address signals,
User's SRAM read-write control circuits（102）, receive fifo control circuit（101）The current FIFO capacity of output indicates letter
Number, according to SRAM memory bank circuits（105）Remove the residual capacity after current FIFO capacity and distribute similar for each user equipment
The read/write address of FIFO operations,
Address decoding circuitry（103）, current FIFO and user equipment according to selected by system equipment address signal exports sign system
Selection signal,
Multiplexer circuit（104）, receive fifo control circuit（101）The current FIFO of output reads address signal and current FIFO
Writing address signal, user's SRAM read-write control circuits（102）The read/write address of the similar FIFO operations of each user equipment of output,
Location decoding circuit（103）The selection signal of output, the read-write operation and system selected user of current FIFO selected by completion system are set
Standby similar FIFO operations, and,
SRAM memory bank circuits（105）, with the current FIFO memory banks space divided according to current FIFO capacity and each use
The data back space of the similar FIFO operations of family equipment.
2. the fifo controller that a kind of multichannel read-write multicapacity is selected according to claim 1, it is characterised in that described similar
FIFO is operated including but not limited to RAM read-write operations, stack manipulation.
3. the fifo controller that a kind of multichannel read-write multicapacity is selected according to claim 1, it is characterised in that FIFO is controlled
Circuit（101）Including：
FIFO Capacity Selection circuits, the system input capacity selection signal received according to its input and SRAM memory bank circuits
（105）The threshold value in middle different bank space selects current FIFO capacity,
Current length signal generating circuit, writes according to the numerical relation of the value of current length signal and current FIFO capacity, FIFO
Data enable signal, FIFO and read data enable signal, and foundation prevents Writing overflow from adjusting current length signal with empty principle is read
Value,
Address signal generation circuit is read, during FIFO read operations are carried out, address signal is read and current according to current FIFO
The numerical relation of FIFO capacity adjusts the value that current FIFO reads address signal, and,
Writing address signal generation circuit, address signal sum and current FIFO capacity are read according to current length signal and current FIFO
Numerical relation adjust current FIFO writing address signals.
4. a kind of fifo controller that multichannel read-write multicapacity is selected according to claim 3, it is characterised in that the FIFO
Capacity Selection circuit realizes that the input of MUX inputs SRAM memory bank circuits by MUX（105）In not
With the threshold value in memory bank space, the selection terminating systems input capacity selection signal of MUX, MUX output is worked as
Preceding FIFO capacity.
5. the fifo controller that a kind of multichannel read-write multicapacity is selected according to claim 3, it is characterised in that described current
Length signals generation circuit：FIFO write data enable signal effectively and current length signal value in current FIFO ranges of capacity
When interior, the value to current length signal adds a carry out FIFO write operations, otherwise, and it is effectively and current to read data enable signal in FIFO
The carry out FIFO read operations that subtract one to the value of current length signal when the value of length signals is more than zero.
6. the fifo controller that a kind of multichannel read-write multicapacity is selected according to claim 5, it is characterised in that described current
Length signals generation circuit includes：Two alternative data selectors and d type flip flop, the first alternative data selector, it is selected
Select end input FIFO reading data enables signal effectively and current length signal value is more than 0 logic discriminant, the input of its 1 input
The value that current length signal subtracts one,
Second alternative data selector, it selects end input FIFO write enable signals effectively and current length signal value is current
Logic discriminant in FIFO ranges of capacity, the value that its 1 input input current length signal adds one, its 0 input termination first
The output end of alternative data selector,
D type flip flop, it inputs the output end of the second alternative data selector of termination, and it exports termination the first alternative data choosing
Select 0 input of device.
7. the fifo controller that a kind of multichannel read-write multicapacity is selected according to claim 3, it is characterised in that the reading
Location signal generating circuit：
Data enable signal is read in FIFO effectively and current length signal is more than in the case of 0：Current FIFO reads address signal and existed
When in current FIFO ranges of capacity, Jia one to current FIFO reading address signal progress and operate, until current FIFO reads address signal
During beyond current FIFO ranges of capacity, address signal is read to current FIFO and carries out rezero operation；Kept in the case of remaining current
It is constant that FIFO reads address signal.
8. the fifo controller that a kind of multichannel read-write multicapacity is selected according to claim 7, it is characterised in that the reading
Location signal generating circuit includes：Two alternative data selectors and d type flip flop,
First alternative data selector, it selects end to input current FIFO and reads the logic that address signal is equal to current FIFO capacity
Discriminate, its 0 input inputs current FIFO and reads the value that address signal adds one, and its 1 input inputs 0,
Second alternative data selector, it is selected, and end input FIFO reads data enable signal effectively and current length signal is more than
0 logic discriminant, the output end of its 1 input the first alternative data selector of termination,
D type flip flop, it inputs the output end of the second alternative data selector of termination, and it exports termination the second alternative data choosing
Select 0 input of device.
9. the fifo controller that a kind of multichannel read-write multicapacity is selected according to claim 3, it is characterised in that described to write ground
Location signal generating circuit：
When current length signal reads address signal sum in current FIFO ranges of capacity with current FIFO, with current length signal
With current FIFO read address signal and for current FIFO writing address signals,
When current length signal reads address signal sum beyond current FIFO ranges of capacity with current FIFO, by current length signal
Current FIFO writing address signals are assigned with the current FIFO values for reading to subtract current FIFO capacity again after address signal is cumulative.
10. the fifo controller that a kind of multichannel read-write multicapacity is selected according to claim 9, it is characterised in that described to write
Address signal generation circuit realizes that the selection end input of the alternative data selector is current by an alternative data selector
Length signals reads the logic discriminant that address signal sum is more than current FIFO capacity, alternative data selection with current FIFO
0 input input current length signal and the current FIFO of device read address signal sum, 1 input of the alternative data selector
End input current length signal and current FIFO read to subtract the value of current FIFO capacity after address signal is cumulative again.
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| CN201621462473.4U CN206431615U (en) | 2016-12-28 | 2016-12-28 | A kind of fifo controller of multichannel read-write multicapacity selection |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106776357A (en) * | 2016-12-28 | 2017-05-31 | 无锡芯响电子科技有限公司 | A kind of fifo controller of multichannel read-write multicapacity selection |
| CN111783167A (en) * | 2020-07-24 | 2020-10-16 | Oppo广东移动通信有限公司 | FIFO read-write control circuit, chip, electronic equipment and data transmission method |
| CN113485672A (en) * | 2021-09-07 | 2021-10-08 | 苏州浪潮智能科技有限公司 | Information generation method, device, equipment and medium based on FIFO memory |
-
2016
- 2016-12-28 CN CN201621462473.4U patent/CN206431615U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106776357A (en) * | 2016-12-28 | 2017-05-31 | 无锡芯响电子科技有限公司 | A kind of fifo controller of multichannel read-write multicapacity selection |
| CN106776357B (en) * | 2016-12-28 | 2023-12-15 | 无锡芯研微电子有限公司 | FIFO controller with multiple paths of reading and writing and multiple capacity selections |
| CN111783167A (en) * | 2020-07-24 | 2020-10-16 | Oppo广东移动通信有限公司 | FIFO read-write control circuit, chip, electronic equipment and data transmission method |
| CN113485672A (en) * | 2021-09-07 | 2021-10-08 | 苏州浪潮智能科技有限公司 | Information generation method, device, equipment and medium based on FIFO memory |
| CN113485672B (en) * | 2021-09-07 | 2021-11-19 | 苏州浪潮智能科技有限公司 | Information generation method, device, equipment and medium based on FIFO memory |
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