CN102932696B - Satellite-borne high-speed data multiplexer system and realizing method thereof - Google Patents

Satellite-borne high-speed data multiplexer system and realizing method thereof Download PDF

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CN102932696B
CN102932696B CN201210375466.0A CN201210375466A CN102932696B CN 102932696 B CN102932696 B CN 102932696B CN 201210375466 A CN201210375466 A CN 201210375466A CN 102932696 B CN102932696 B CN 102932696B
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data
groups
sdram
module
segment
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CN102932696A (en
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李永峰
赵妍
袁素春
张建华
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西安空间无线电技术研究所
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Abstract

The invention discloses a satellite-borne high-speed data multiplexer system and a realizing method thereof. The system comprises a data grouping module, a data sub-packaging module, an SDRAM (Synchronous Dynamic random access memory) optimal control module, a virtual channel scheduling module and a channel coding module, wherein the data grouping module receives 30 paths of information source data; the 30 paths of information source data are divided into 5 groups according to a transmission priority or a strategy of balanced data volume; the data sub-packaging module is used for splitting and organizing packets in each path of the information source data in the 5 groups so as to form 5 groups of protocol unit data; the SDRAM optimal control module is used for respectively writing 5 groups of protocol unit data into 5 SDRAMs for caching and reading control so as to form 5 groups of virtual channel data; the virtual channel scheduling module is used for performing dynamic scheduling management and multiple connection on the 5 groups of virtual channel data and one group of empty frames so as to be combined to form one path of form type code flow; and the channel coding module is used for isolating the one path of form type code flow from an FIFO (first in and first out) by a local clock, and coding and scrambling the isolated form type code flow so as to form one path of data transmission frame as the output of the data multiplexer system.

Description

A kind of spaceborne high-speed data multiplexer system and implementation method

Technical field

The present invention relates to a kind of spaceborne high-speed data multiplexer system and implementation method, belong to the data transmission system field of spacecraft.

Background technology

The theoretical foundation of data multiplexing is the concept of pseudo channel.A physical channel is divided into multiple logic channel, and each logic channel is identified separately and is transmitted a kind of data flow, and each data flow can use different business, and a logic channel is exactly a pseudo channel.Pseudo channel makes a physical space channel be shared in a time multiplexed manner by multiple high level data stream, thus the data of number of different types can be transmitted on a physical channel.

Onboard data multiplexer system is responsible for receiving multi-source data in spatial data transmission, the i.e. information source data (visible ray packed data, spectroscopic data, SAR data, investigation load data, satellite platform data etc.) of multichannel different-format, different rates, the input form of every road information source data is general as shown in Figure 5; To every road information source data, adopt the concept of " subpackage " to organize, form the protocol element data with consolidation form according to CCSDS agreement; The protocol element data corresponding to multichannel various information source, the concept of " pseudo channel " is adopted to carry out multiple connection, the data of various information source are assembled into unified data transmission frames (frame format as shown in Figure 4), after encryption and coding, transmit between star-star or star-ground through Same Physical channel., at receiving terminal, according to information such as the virtual channel identifier in transfer of data frame format, frame counter, BPDU top guides, the complete information of each various information source can be restored to one of them requirement of onboard data multiplexer system.

Data multiplexing device system generally comprises data buffer storage unit, data protocol unit, data scheduling unit, channel encoding unit 4 parts, data buffer storage unit is used for carrying out clock zone switching and data buffer storage to the multi-source data of input, data protocol unit generates and meets the virtual channel data unit unit that CCSDS agreement has specific format, data scheduling unit carries out dynamic dispatching management and asynchronous multiplexing to multiple virtual channel data unit unit, organising data frame, generate the data code flow that has consolidation form, channel encoding unit carries out RS/LDPC coding to above-mentioned data code flow, scrambling, generate the data code flow being applicable to physical channel transmission.

Prior art relates generally to the design of hardware and software of multichannel data multiplexer system under 100,000,000 stage speeds, multiple connection algorithm and implementation strategy.

The emerging paper " design based on the restructural multiplexer of Advanced Orbiting Systems " the 3rd page of Space Sci. & Application Research Center, Chinese Academy of Sciences's old sight in 2010 describes a kind of structure of multichannel data multiplexer, for the typical composition of the multiplexer based on prior art structure, as shown in Figure 1,4 circuit-switched data multiple connections can be realized.

Master's thesis " design of the configurable multiplexer of the high speed based on CCSDSAOS and FPGA " the 3rd chapter of Postgraduate School, Chinese Academy of Sciences 2007 great writers describes a kind of implementation method of multichannel data multiplexer, 6 circuit-switched data multiple connections can be realized, processing speed is 144Mbps, for typical based on the multiplexer implementation method of prior art, as shown in Figure 2.

The paper " high-speed multiplexer principle prototype and sky-ground transmission system thereof " of Space Sci. & Application Research Center, Chinese Academy of Sciences's Yang Yi health in 2006 proposes a kind of implementation method of multichannel data multiplexer, and bit rate is 640Mbps.

Within 1996, Chinese patent " a kind of high-speed multiplexer and its implementation " (patent No.: CN96109329.3) provides a kind of multiplexer implementation method for spacecraft, can complete the asynchronous multiplexing of 3 tunnel input data, processing speed is 100,000,000 grades.

The multiplexer implementation method that other document is introduced, similar with the implementation method in above-mentioned document, there is following four problems:

(1) only support that burst length is less, and burst length fixes the multi-source data multiple connection of (in Fig. 5, the t1 time is shorter, is generally less than 16K clock cycle, and for every circuit-switched data, t1 length immobilizes);

(2) data buffer storage unit generally selects the outer FIFO of sheet, the outer SRAM of sheet or ram in slice as buffer, and with input information source data one_to_one corresponding (the corresponding sheet External Registers of every road information source data), data buffer storage speed is lower, and buffer memory capacity is less;

(3) attainable multiple connection object less (whole realization is lower than the different pieces of information multiple connection on 8 tunnels);

(4) processing speed lower (being generally less than 700Mbps).

Summary of the invention

Technology of the present invention is dealt with problems: the above-mentioned deficiency overcoming prior art, a kind of spaceborne multichannel data multiplexer system and implementation method are provided, break through the restriction of 100,000,000 grades of processing speeds, the high speed multiple connection of G bit-level multichannel data can be realized, increase data multiplexing way simultaneously, realize the real-time multiple connection of 30 tunnel different pieces of informations.

The technology of the present invention solution: a kind of spaceborne high-speed data multiplexer system, comprise: packet module, data subpackage module, SDRAM optimal control module, virtual channel schedule module, channel coding module, this system with FPGA and SDRAM for implementation platform, in the logic function of above-mentioned each module and sheet, buffer memory is realized by FPGA, the outer buffer memory of sheet is realized by SDRAM, wherein:

Packet module: receive 30 tunnel information source data, be divided into 5 groups, often organize 6 circuit-switched data according to the strategy of transmission priority or equilibrium criterion amount, inputs as data subpackage module;

Data subpackage module: the 5 groups of data receiving packet module, every Zu Zhongmei road information source number according to this packet is unit input, described packet is split, form some segment datas, produce some segment informations in split process simultaneously, segment information comprises fragment counter and BPDU top guide, segment information and segment data are organized, generate protocol element data, 5 groups of corresponding 5 groups of protocol element data of data, as the input of SDRAM optimal control module;

SDRAM optimal control module: the 5 groups of protocol element data receiving data subpackage module, write 5 SDRAM respectively and carry out buffer memory, under the reading request signal of virtual channel schedule module, read 5 SDRAM data, form 5 groups of virtual channel data, as the input of virtual channel schedule module;

Virtual channel schedule module: the 5 groups of virtual channel data receiving SDRAM optimal control module, and produce 1 group of empty frame by infilled frame unit, dynamic dispatching management and multiple connection are carried out to above-mentioned 6 groups of data, is combined into 1 road form code stream, as the input of channel coding module;

Channel coding module: the 1 road form code stream receiving virtual channel schedule module, isolated by local clock and FIFO, eliminate the shake that high frequency clock is introduced in process and transmitting procedure, to the form code stream parallel encoding after isolation and scrambling, generate 1 circuit-switched data transmission frame, as the output of data multiplexing device system.

Described packet module is implemented as: when dividing into groups according to transmission priority, according to inhomogeneity information source data to the difference of requirement of real-time, information source data the highest for requirement of real-time are divided at the 1st group, the like, information source data minimum for requirement of real-time are divided at the 5th group; When dividing into groups according to the strategy of equilibrium criterion amount, add up the valid data amount of 30 tunnel information source data, according to average amount principle, 30 tunnel information source data are divided into 5 groups of data.

Described data subpackage module is implemented as:

(1) the corresponding every road information source data often organizing data, when the packet of these information source data is split, the segment data formed and segment information need buffer memory in sheet, set up two RAM in FPGA inside respectively and realize buffer memory in sheet, i.e. segment data RAM and segment information RAM, wherein segment data RAM is used for buffer memory segment data, segment information RAM is used for buffer memory segment information, segment information comprises fragment counter, for the BPDU top guide of the byte length of identified segments data, when carrying out buffer memory in sheet, segment data and segment information are write each self-corresponding RAM respectively,

(2) synchrodata reading is carried out to two RAM, when namely reading the data of a certain address field of segment data RAM, read the data of segment information RAM appropriate address section simultaneously, the data of reading are organized, and add frame alignment word, virtual channel identifier, form protocol element data;

(3) 5 groups of data form 5 groups of protocol element data.

Described SDRAM optimal control module concrete grammar is:

(1) correspondence often organizes protocol element data, uses 1 SDRAM as the outer buffer memory of sheet;

(2) on the sdram after electric initialization, by the control and optimize of SDRAM for writing process, read procedure and null process, according to refresh cycle of SDRAM, operating frequency and protocol data unit length, determine a work period, above-mentionedly writing process, switching between read procedure and null process;

(3) perform when meeting SDRAM write condition and write process, by protocol element data write SDRAM, meet when SDRAM reads condition and perform read procedure, read SDRAM data genaration virtual channel data, when not meeting the write condition of SDRAM or read condition, perform null process;

(4) 5 groups of protocol element data form 5 groups of virtual channel data.

Described virtual channel schedule module is implemented as:

(1) correspondence often organizes virtual channel data, need buffer memory in sheet when dynamic dispatching management, set up 1 formatted data RAM in FPGA inside, for the digital independent frequency of the outer buffer memory of trimmer, and reading data are carried out buffer memory in sheet, 5 groups of corresponding 5 formatted data RAM of virtual channel data;

(2) carry out Read-write Catrol according to the buffer data size of formatted data RAM to form data RAM, read-write operation is independent, produces 5 groups of formatted datas when reading 5 formatted data RAM;

(3) 1 group of empty frame is produced by infilled frame unit;

(4) 5 groups of formatted datas and 1 group of empty frame are carried out data multiplexing, be combined into 1 road AOS form code stream.

Described channel coding module is implemented as:

(1) 1 road AOS form code stream is received, FIFO is set up in FPGA inside, with the synchronised clock of form code stream by AOS form code stream write FIFO, FIFO is read with local clock, for eliminating the shake that high frequency clock is introduced in process and transmitting procedure, and improve the stability of interface adaptability and system;

(2) data structure for making above-mentioned FIFO isolation not affect AOS form code stream, carries out frame format arrangement to the formatted data read from FIFO, recovers its data structure;

(3) chnnel coding and scrambling are carried out to formatted data, generate data transmission frames.

A kind of spaceborne high-speed data multiplexer method, performing step is as follows:

(1) receive 30 tunnel information source data, be divided into 5 groups according to the strategy of transmission priority or equilibrium criterion amount, often organize 6 circuit-switched data;

(2) 5 groups of data of packet module are received, every Zu Zhongmei road information source number according to this packet is unit input, described packet is split, form some segment datas, produce some segment informations in split process simultaneously, segment information and segment data are organized, generates protocol element data, 5 groups of corresponding 5 groups of protocol element data of data;

(3) receive 5 groups of protocol element data of data subpackage module, write 5 SDRAM respectively and carry out buffer memory, under reading request signal, read 5 SDRAM data, form 5 groups of virtual channel data;

(4) receive 5 groups of virtual channel data, and produce 1 group of empty frame by infilled frame unit, dynamic dispatching management and multiple connection are carried out to above-mentioned 6 groups of data, is combined into 1 road form code stream;

(5) 1 road form code stream is received, isolated by local clock and FIFO, eliminate the shake that high frequency clock is introduced in process and transmitting procedure, to the form code stream parallel encoding after isolation and scrambling, generate 1 circuit-switched data transmission frame, as the output of data multiplexing device system.

The present invention compared with prior art has following beneficial effect:

(1) the present invention proposes the generation method of the subpackage of a kind of large burst length data and respective protocol data cell, burst length cannot be realized with prior art and be greater than the data subpackage of 1M byte and protocol Data Unit generates, prior art only processes burst length and is tens K bytes and the fixing information source data of length, along with the development of earth observation technology, for the single channel information source data that spacecraft exports, its burst data length dynamically changeable, and scope be a few K byte to tens Mbytes, the present invention propose method efficiently solve the deficiencies in the prior art;

(2) optimal control of SDRAM of the present invention substantially reduces the complexity that SDRAM controls, and makes SDRAM can be used for the outer buffer unit of sheet of multiplexer, improves buffer memory rate and buffer memory capacity, achieve high speed multiple connection and the process of G bit-level data;

(3) the buffer unit technology of sharing of inhomogeneity data of the present invention, 6 kinds of inhomogeneity data sharings sheet data file, decreases sheet External Registers number, greatly reduces cost, improve level of integrated system.

(4) Clock Isolation Technique in channel coding module of the present invention, can eliminate the shake that high frequency clock is introduced in process and transmitting procedure, improves the stability of interface adaptability and system.

Accompanying drawing explanation

Fig. 1 is multiplexer structure chart in prior art;

Fig. 2 is the implementation method schematic diagram of multiplexer in prior art;

Fig. 3 is the composition frame chart of present system;

Fig. 4 is the flow chart that multi-source data of the present invention is input to data transmission frames output;

Fig. 5 is the data format of data transmission frames of the present invention;

Fig. 6 is the input data mode of a certain information source of the present invention;

Fig. 7 is fractionation and the protocol element data genaration schematic diagram of the present invention's a certain information source one bag data;

Fig. 8 is the state machine diagram of SDRAM optimal control of the present invention;

Fig. 9 is pseudo channel dynamic dispatching management procedure chart of the present invention;

Figure 10 is the schematic diagram of channel coding module of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the present invention is described in further detail with concrete enforcement:

As shown in Figure 3, a kind of spaceborne high-speed data multiplexer system of the present invention comprises 5 modules such as packet module, data subpackage module, SDRAM optimal control module, virtual channel schedule module, channel coding module, wherein:

Packet module: receive the 30 inhomogeneous multi-source datas in road, represent with MSD1, MSD2 ..., MSD30 respectively, divide into groups according to the strategy of transmission priority or equilibrium criterion amount, every 6 circuit-switched data are one group, be divided into 5 groups, be followed successively by the 1st group (MGD1), the 2nd group (MGD2), the 3rd group (MGD3), the 4th group (MGD4), the 5th group (MGD5); When dividing into groups according to transmission priority, according to the difference of inhomogeneity data to requirement of real-time, information source data the highest for requirement of real-time are divided at the 1st group, the like, divide at the 5th group to the information source data that requirement of real-time is minimum; When dividing into groups according to the strategy of equilibrium criterion amount, add up the average amount of 30 circuit-switched data, according to the principle of valid data amount close to average amount often organizing data after grouping, 30 road multi-source datas are divided into 5 groups of data.

Data subpackage module: the 5 groups of data receiving packet module, for Mei Zumei road information source data, according to the length in data transmission frames BPDU bit stream data territory in Fig. 5, bag data (corresponding to the t1 time) in Fig. 6 are split, form some segment datas, produce some segment informations in split process simultaneously, segment information comprises fragment counter and BPDU top guide, after splitting, a complete packet is divided into some segment datas, frame alignment word is added in each segment data front portion, spacecraft identifier, virtual channel identifier, fragment counter, BPDU top guide, VCDU error control territory is reserved at every segment data rear portion, position, checking symbol territory, generate protocol element data, 5 groups of corresponding 5 groups of protocol element data of data,

Wherein the generation concrete grammar of data subpackage and protocol element data is:

For Mei Zumei road information source data, its data packet length is variable, general from a few K byte to tens Mbytes, for wherein bag data of specifying in certain road information source, its data length is determined, be assumed to be DP_LENTH, the maximum length in data transmission frames BPDU bit stream data territory is assumed to be DU_LENTH, and bag data are divided into M section, M=DP_LENTH/DU_LENTH+i, when wherein DP_LENTH is the integral multiple of DU_LENTH, i equals 0, otherwise i equals 1; One bag data are divided into some segment datas, 1st byte of the 1st segment data corresponds to the 1st byte of these bag data, the length of the 1st segment data equals DU_LENTH, the length of M segment data is MD_LENTH, MD_LENTH=DP_LENTH%DU_LENTH, BPDU bit stream data territory corresponding to M segment data by these bag data last MD_LENTH byte and be partially filled byte (byte of padding length is DU_LENTH-MD_LENTH) and form.

The segmentation of packet and the generation of protocol element data are with FPGA for realizing carrier, and FPGA has storage resources in abundant sheet to may be used for data buffer storage, and a large amount of trigger resources and combination logic resource can be used for realizing sequence circuit.To road information source data, two RAM are set up as buffer area in FPGA inside, one is segment data RAM, for carrying out real-time segmentation and buffer memory to this circuit-switched data of input, each segment data is buffered in the different address fields of segment data RAM respectively, and another object of segment data RAM is that clock zone switches; Another buffer area is segment information RAM, for carrying out buffer memory to the segment information produced during segmentation, and the wherein position of this segment data of segment data counter identification in a complete data packet or order, BDDU top guide identifies the byte length of this segment data; In data sectional process, at the clock gap that each segment data first character joint is corresponding, the fragment counter of this segment data is buffered in segment information RAM, at the clock gap that last byte of each segment data is corresponding, the BPDU top guide of this segment data is buffered in segment information RAM, for each segment data, corresponding address field is distributed in segment data RAM and segment information RAM, complete information cache (segment data and segment information) can be carried out, namely, in segment data RAM and segment information RAM, be carry out buffer memory in units of section.In packet module, often organizing data and comprise 6 tunnel information source data, therefore for often organizing data, setting up 6 segment data RAM and 6 segment information RAM in FPGA inside respectively, for realizing the real-time independent buffer memory of 6 tunnel information source data.W_req signal (written request signal of SDRAM) is produced in SDRAM optimal control module, form the reading request signal of segment data RAM and segment information RAM by W_req signal and read sequential, according to the data buffer storage amount of 6 segment data RAM, when only having the buffer memory of a segment data RAM to be greater than 1 segment data, this number segmentation is read according to RAM, when the buffer memory of multiple segment data RAM is greater than 1 segment data, poll reading is carried out to multiple segment data RAM; When segment data RAM is read, each reading continuously 1 segment data, and from segment information RAM, read corresponding fragment counter, BPDU top guide, reading under sequential, be filled in corresponding time slot respectively, frame alignment word, spacecraft identifier, virtual channel identifier are filled in corresponding time slot simultaneously, complete the generation of protocol Data Unit with this.

SDRAM optimal control module: above-mentioned 2nd module achieves the fractionation of packet, the generation of protocol element data and a data multiplexing, 6 tunnel information source data (one group of data) multiple connection is (or being combined into) 1 group of protocol element data, data are write as a slice SDRAM, protocol element packet contains the necessary information distinguishing each road information source and the information source subpackage of each road, therefore 6 kinds of inhomogeneity data can use a sheet External Registers SDRAM as data buffer area, multiple information source data are shared a sheet External Registers, greatly reduce the number of sheet External Registers, be conducive to reducing cost and improving level of integrated system.Use SDRAM as sheet External Registers, SDRAM has at a high speed and jumbo feature, with FIFO, the sheets such as SRAM store outward and compare, the control of SDRAM is comparatively complicated, therefore in this module, the control of SDRAM is optimized, what be SDRAM with the data buffer storage amount of 6 segment data RAM in above-mentioned 2nd module writes controlled condition, what be SDRAM with the output speed of data multiplexing device system and pseudo channel priority reads controlled condition, realize the optimal control of SDRAM, the high-speed chip simultaneously realizing G bit-level data stores outward and exchanges with the high-speed data of process chip FPGA, in the present invention, the processing speed of data multiplexing device is higher than 3.6Gbps,

To the concrete grammar of SDRAM optimal control be wherein:

In high-speed data multiplexer, the read-write of SDRAM is by page operations, protocol element data in corresponding above-mentioned 2nd module of one page data, its length is 1024 bytes according to CCSDS suggestion, select the SDRAM of 32 bit data bit wides, then a write operation of SDRAM is, in continuous print 256 clocks, each clock writes the data of 32 bits (4 byte) to SDRAM, equally, a read operation of SDRAM is, reads 1024 bytes (data of 256 32 bit bit wides) from SDRAM one-time continuous, the control and optimize of SDRAM is 4 kinds of operations (process) such as initialization operation, write operation, read operation, do-nothing operation, wherein initialization operation completes in the 300us time period after electricity on the sdram, comprise the wait that powers on of 200us, and preliminary filling, refreshing, mode register such as to arrange at 3 orders, after initialization operation completes, until before SDRAM re-powers next time, no longer carry out the initialization operation of SDRAM, the working clock frequency of SDRAM is selected to be greater than 50MHz, according to the requirement of SDRAM refresh interval, the all BANKs refreshings of every 280 clocks to SDRAM are set and once (send a refresh command to SDRAM), with 280 clocks for the cycle, select to carry out write operation, read operation or do-nothing operation to SDRAM, after SDRAM completes initialization operation, be exactly at write operation to the operation of SDRAM, rotate between read operation and do-nothing operation, the time interval between each operation is 280 clocks, when meeting write operation condition, namely in above-mentioned 2nd module, the protocol Data Unit number of data RAM buffer memory is greater than 1, a write operation is carried out to SDRAM, the write pointer of SDRAM moves down 256 addresses simultaneously, a simple write operation comprises 1 line activating order, 1 write order, 1 preliminary filling order, 1 refresh command and a 276 null command (write operation 280 clocks, time each, clockwise SDRAM sends a control command, when not sending effective control command, null command is sent) to SDRAM, by a write operation, by a protocol Data Unit write SDRAM, when meeting read operation condition, namely when the 4th module proposes reading request signal to SDRAM, a read operation is carried out to SDRAM, the read pointer of SDRAM moves down 256 addresses simultaneously, a simple read operation comprises 1 line activating order, 1 read command, 1 preliminary filling order, 1 refresh command and 276 null commands, by a read operation, read a protocol Data Unit from SDRAM, when write operation condition and the equal deficiency of read operation condition meet, carry out a do-nothing operation to SDRAM, a simple do-nothing operation comprises 1 refresh command and 279 null commands, when write operation condition and read operation condition meet simultaneously, for reducing the empty frame per second of multiplexer, preferentially carry out the read operation of SDRAM.

Virtual channel schedule module: according to the output speed requirement of data multiplexing device system, carry out selection to the data of 5 sheet External Registers SDRAM to read, selection gist is transmission priority, and the SDRAM corresponding to the virtual channel data higher to transmission priority, answers prioritizing selection to read; Without under transmission priority condition, for the data from overflow risk of reducing tab External Registers, select the maximum SDRAM of data buffer storage amount preferentially to read, or be the Data distribution8 density of the multiple virtual channel data of balance in a physical channel, poll reading can be carried out between 5 SDRAM; Control by carrying out reading to SDRAM, can realize the dynamic dispatching management of virtual channel data, the protocol element data corresponding to multiple pseudo channel exported by 5 SDRAM carry out multiple connection, together with the empty frame data that infilled frame unit produces, generate the data code flow that has consolidation form

Wherein the concrete grammar of virtual channel data dynamic dispatching management is:

High-speed data multiplexer system, the outer SDRAM of corresponding 5 sheets, 5 formatted data RAM are set up in FPGA inside, be respectively used to the output data writing every sheet SDRAM, formatted data RAM writes the working clock frequency that clock frequency equals SDRAM, under the output speed determination condition of data multiplexing device system, formatted data RAM reads clock RCLK, its frequency is determined, what can produce formatted data RAM with this frequency reads sequential, every 256 RCLK clocks are that an AOS form code stream exports the cycle, the poll of SDRAM is read, namely read with the sequential poll between 5 formatted data RAM of reading produced, when 5 formatted data RAM all do not meet read data condition, namely when the buffer data size of 5 formatted data RAM is all less than 1 virtual channel data length, now reading the empty frame inserting the generation of infilled frame unit in sequential, to keep the continuity exporting data (AOS form code stream), RCLK produce read sequential under, virtual channel data is read from 5 formatted data RAM, when there is interval between the virtual channel data exported (gap length is the integral multiple of 256 clock cycle), insert the empty frame that infilled frame unit produces, with this formed one with 256 clocks be the cycle, data bit width is the AOS form code stream of 32.

Channel coding module: the AOS form code stream that above-mentioned 4th module is exported, first bit width conversion is carried out, forming a data bit width is 8, accompanying clock frequency 4 is doubly to the form code stream of RCLK (this accompanying clock is designated as AOS_CLK), corresponding 1 byte data of accompanying clock in this form code stream, every 1024 bytes are called frame data, after bit width conversion, by setting up FIFO in FPGA inside, employing local clock is isolated, eliminate the shake that high frequency clock is introduced in process and transmitting procedure, afterwards VCDU data cell (see Fig. 4) is encrypted by byte, and carry out RS/LDPC coding, data scrambling, RS (255 is selected during RS coding, 223) or RS (255, 239), (8160 are selected during LDPC coding, 7136) shorten code, RS/LDPC coding time produce check character replace virtual channel data be partially filled byte (the checking symbol territory in Fig. 4 frame format), parallel scrambling mode is adopted during data scrambling, to realize the high-speed data process of G bit-level.

A kind of spaceborne high-speed data multiplexer system and implementation method, comprise the steps:

(1) receive 30 tunnel inhomogeneity multi-source datas, divide into groups according to the strategy of transmission priority or equilibrium criterion amount, every 6 circuit-switched data are one group, are divided into 5 groups;

(2) for 6 circuit-switched data often organized, 6 segment data RAM and 6 segment information RAM of FPGA inside are used to realize the generation of data subpackage and protocol element data, subpackage refers to and a complete data packet (data that in Fig. 5, the t1 time period is corresponding) of every road information source is divided into some segment datas, when subpackage, each segment data is buffered in the corresponding address section of corresponding segment data RAM, and by fragment counter, BPDU top guide is buffered in the corresponding address section of corresponding segment information RAM, the method can realize comprising large burst length and the fractionation of the packet of variable-length packet, reading under segment data RAM sequential, frame alignment word, spacecraft identifier, virtual channel identifier, fragment counter, BPDU top guide are added to the segment data front portion that segment data RAM exports, at adding portion, segment data rear portion byte of padding, protocol element data can be formed,

(3) to the protocol element data generated in step (2), under SDRAM working clock frequency, through a data multiplexing, be combined into one group of protocol element data, data are write, 5 groups of corresponding 5 groups of protocol element data of data as the outer memory cell SDRAM of a sheet;

(4) 5 groups of corresponding 5 SDRAM of protocol element data, according to the buffer size of data transmission frames format characteristic and data multiplexing, the control of SDRAM is optimized, be reduced to 3 fundamental modes such as write operation, read operation, do-nothing operation, and under write operation pattern, complete the G bit-level high-speed cache to 5 groups of data;

(5) according to the output speed of data multiplexing device system, carry out selection to the data of 5 SDRAM to read, 5 formatted data RAM are set up in FPGA inside, with SDRAM work clock for writing clock, respectively the output data of 5 SDRAM are written to 5 corresponding formatted data RAM, clock RCLK is read with the output speed computation scheme data RAM of data multiplexing device system, with this frequency produce formatted data RAM read sequential, RCLK produce read sequential under, virtual channel data is read from 5 formatted data RAM, when there is interval between the virtual channel data exported, insert the empty frame that infilled frame unit produces, one is formed with 256 clocks for the cycle with this, data bit width is the AOS form code stream of 32.

(6), after bit width conversion, clock isolation, error correction coding, parallel scrambling being carried out to the AOS form type code stream in step (5), the data transmission frames of data multiplexing device system is formed, at Same Physical channel,

Realize the time sharing transmissions of 30 road multi-source datas.

Fig. 4 is implementation method flow chart of the present invention, and flow process of the present invention can be divided into multi-source data grouping, data subpackage, protocol element data genaration, a multiple connection, SDRAM optimal control, infilled frame generation, pseudo channel dynamic management, chnnel coding totally 8 parts.

Specific implementation process is as follows:

(1) 30 road multi-source data is input to data multiplexing device, and the strategy according to transmission priority or equilibrium criterion amount is divided into 5 groups;

(2) for the 6 tunnel different pieces of informations often organized, after data subpackage, protocol element data genaration, a data multiplexing, 1 group of protocol element data is combined into, 5 groups of corresponding 5 groups of protocol element data of data;

(3) under SDRAM written request signal, 1 group of protocol element data carries out buffer memory as the data of writing of a slice SDRAM;

(4) according to the output speed of data multiplexing device system, calculate and generate the reading request signal of SDRAM, under reading request signal, from 5 SDRAM sense datas;

(5) when SDRAM exports without valid data, empty frame is produced by infilled frame unit;

(6) virtual channel schedule management is carried out to the empty frame that virtual channel data and the infilled frame unit of 5 SDRAM outputs produce, generate AOS form code stream;

(7) chnnel coding is carried out to AOS form type code stream, form the data transmission frames being used for Same Physical channel.

Fig. 5 is the transfer of data frame format that data multiplexing device of the present invention exports, and each explanation of field is as follows:

(1) synchronization character, 16 ary codes 1ACFFC1D, synchronous for receiving terminal achieve frame;

(2) virtual channel identifier, for distinguishing 30 road multi-source datas and empty frame data;

(3) VCDU counting, i.e. fragment counter, for identifying the correspondence position relation of protocol Data Unit in these information source data of subpackage Hou Mei road information source;

(4) BPDU top guide, for identifying the byte number of valid data in this data transmission frames BPDU bit stream data territory;

(5) BPDU bit stream data territory, deposits segment data, when segment data is less than this data field length, inserts padding data, without (5 output RAM are all countless according to when exporting) during valid data, is empty frame data;

(6) VCDU error control territory, for deposit CRC check and;

(7) checking symbol territory, for depositing the check digit that channel coding module produces.

Fig. 6 is the input data mode of a certain information source of the present invention, input signal corresponding to information source comprises synchronised clock, with gate, data, wherein data bit width is indefinite, general in 1bit ~ 32bit scope, with the high level mark valid data of gate, namely need the data processing and transmit, with the low level mark invalid data of gate, the data that namely can abandon, also can identify valid data with the low level of gate in actual use, with the high level mark invalid data with gate; The duration of one bag data is t, comprise t1 time and t2 time, the t1 time is valid data transmission time of information source, a complete data packet of a t1 time tranfer information source, i.e. bag valid data of the corresponding information source of t1, the t2 time is invalid data transmission time of information source, i.e. retrace interval, t, t1, t2 are all variable, and wherein the length range of t1 is that a few K clock cycle is to tens clock cycle.

Fig. 7 is the fractionation of the present invention's a certain information source one bag data and the generation schematic diagram of protocol element data.Multi-source data is transmit with the data transmission frames form shown in Fig. 4 in physical channel, bag valid data in Fig. 5, and the data division that namely the t1 time is corresponding, transmits in actual physics passage for carrier with BPDU bit stream data territory in Fig. 4 data transmission frames; Length due to bag data is far longer than the length in BPDU bit stream data territory, therefore a bag Data Division is some sections, and the supplementary (frame alignment word, virtual channel identifier, fragment counter, BPDU top guide) necessary to the interpolation of each segment data forms protocol element data, for follow-up data processing and transmission.

Specific implementation process is as follows:

(1) set up two RAM to every road information source data in FPGA inside, one is segment data RAM, and for each segment data of buffer memory, one is segment information RAM, for buffer memory segmentation supplementary, comprises fragment counter, BPDU top guide;

(2) capacity of segment data RAM can buffer memory 4 segment datas, divide in packet procedures in data, in 4 address fields of the write segment data RAM that each segment data is circulated, under the reading request signal of segment data RAM, from the sense data of 4 address field circulations of segment data RAM;

(3) corresponding with segment data RAM, the capacity of segment information RAM can the supplementary of buffer memory 4 segment datas, divide in packet procedures in data, in 4 address fields of the write segment information RAM that the supplementary of each segment data is circulated, when reading the data of a certain address field of segment data RAM, read the supplementary of segment information RAM appropriate address section;

(4) in the segment data front portion that segment data RAM exports, add frame alignment word, spacecraft identifier, and to should the virtual channel identifier of road information source, segment information the RAM fragment counter, the BPDU top guide that export, and reserve error control territory, position, checking symbol territory at rear portion, namely form protocol element data;

(5) the corresponding 1 tunnel protocol element data of single information source, one group of multi-source data comprises 6 tunnel protocol element data, according to the work clock of SDRAM, 6 tunnel protocol element data is carried out a data multiplexing, form one group of protocol element data, write data as 1 SDRAM.

Fig. 8 is the state machine diagram of SDRAM optimal control of the present invention.Use SDRAM as sheet External Registers, 1 SDRAM buffer memory, 1 group of protocol element data (6 tunnel protocol element data are called 1 group of protocol element data), the control of SDRAM is optimized, after electricity and initialization complete on the sdram, write operation, read operation and do-nothing operation 3 kinds are reduced to its operation.

Specific implementation process is as follows:

(1) SDRAM carries out initialization operation after powering on, initialization operation comprises 200us and to power on wait, 1 preliminary filling order PRE, more than 8 refresh command REF, 1 mode register set command MRS and multiple null command NOP, when wherein mode register is arranged, SDRAM is set for read and write with page unit;

(2) after initialization operation completes, use the work clock of SDRAM, generate the counter that one-period is 280 clocks, produce Control timing sequence with this cycle counter, write operation, read operation or do-nothing operation are carried out to SDRAM;

(3) after the written request signal of SDRAM sends, and receive the protocol Data Unit of front end input, perform write operation, a write operation comprises 1 line activating order ACT, 1 write order WRITE, 1 preliminary filling order PRE, 1 refresh command REF, 276 null command NOP;

(4) after the reading request signal receiving SDRAM send, and the protocol Data Unit number of buffer memory is greater than 1 in SDRAM, perform read operation, a read operation comprises 1 line activating order ACT, 1 read command READ, 1 preliminary filling order PRE, 1 refresh command REF, 276 null command NOP;

(5) when the write condition of SDRAM does not all meet with condition of reading, perform do-nothing operation, a do-nothing operation comprises 1 refresh command REF, 279 null command NOP.

Fig. 9 is pseudo channel dynamic dispatching management procedure chart of the present invention, comprises 5 formatted data RAM, 1 infilled frame generation unit, 1 virtual channel schedule unit.

Specific implementation process is as follows:

(1) 5 formatted data RAM are set up in FPGA inside, as the output buffer of 5 SDRAM;

(2) according to the output speed of data multiplexing device system, AOS formatting clock AOS_CLK is calculated;

(3) take AOS_CLK as clock, generate the counter in 256 cycles, and produce formatted data RAM with this counter read Control timing sequence, between 5 formatted data RAM, read each virtual channel data;

(4) when the data buffer storage amount of 5 formatted data RAM is lower than 2 virtual channel data, send and read SDRAM request signal, independently from each self-corresponding SDRAM, read data;

(5) all countless according in output situation at 5 formatted data RAM, export empty frame by infilled frame generation unit;

(6) the empty frame that the virtual channel data of 5 formatted data RAM and infilled frame generation unit export is carried out secondary data multiple connection, form AOS form code stream.

Figure 10 is the schematic diagram of channel coding module of the present invention, this module is isolated by bit width conversion, FIFO, data frame format arranges, encrypt and 5 parts such as chnnel coding, scrambling form, wherein latter two part difference with the prior art is to adopt multidiameter delay processing method, is conducive to the processing speed promoting data multiplexing device.

Specific implementation process is as follows:

(1) AOS form code stream after carrying out bit width conversion, follow-up data processes by each clock byte is received;

(2) set up FIFO in FPGA inside, AOS form code stream writes FIFO with its synchronised clock (accompanying clock), reads data with local clock from FIFO, for eliminating the shake that high frequency clock is introduced in process and transmitting procedure;

(3) data structure for making above-mentioned FIFO isolation not affect AOS form code stream, carries out frame format arrangement to the data read from FIFO, recovers its data structure;

(4) there is frequency departure in the accompanying clock of AOS form code stream and local clock, and infilled frame generation unit exports empty frame, is inserted in formatted data if desired, to ensure the continuity of formatted data;

(5), after chnnel coding, scrambling being carried out to AOS formatted data, data transmission frames is exported.

The above; be only the embodiment of the best of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in technical scope provided by the invention; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.

The content be not described in detail in specification of the present invention belongs to the known technology of professional and technical personnel in the field.

Claims (7)

1. a spaceborne high-speed data multiplexer system, it is characterized in that comprising: packet module, data subpackage module, SDRAM optimal control module, virtual channel schedule module, channel coding module, this system with FPGA and SDRAM for implementation platform, in the logic function of above-mentioned each module and sheet, buffer memory is realized by FPGA, the outer buffer memory of sheet is realized by SDRAM, wherein:
Packet module: receive 30 tunnel information source data, be divided into 5 groups, often organize 6 circuit-switched data according to the strategy of transmission priority or equilibrium criterion amount, inputs as data subpackage module;
Data subpackage module: the 5 groups of data receiving packet module, every Zu Zhongmei road information source number according to this packet is unit input, described packet is split, form some segment datas, produce some segment informations in split process simultaneously, segment information comprises fragment counter and BPDU top guide, segment information and segment data are organized, generate protocol element data, 5 groups of corresponding 5 groups of protocol element data of data, as the input of SDRAM optimal control module;
SDRAM optimal control module: the 5 groups of protocol element data receiving data subpackage module, write 5 SDRAM respectively and carry out buffer memory, under the reading request signal of virtual channel schedule module, read 5 SDRAM data, form 5 groups of virtual channel data, as the input of virtual channel schedule module;
Virtual channel schedule module: the 5 groups of virtual channel data receiving SDRAM optimal control module, and produce 1 group of empty frame by infilled frame unit, dynamic dispatching management and multiple connection are carried out to above-mentioned 5 groups of virtual channel data, is combined into 1 road form code stream, as the input of channel coding module;
Channel coding module: the 1 road form code stream receiving virtual channel schedule module, isolated by local clock and FIFO, eliminate the shake that high frequency clock is introduced in process and transmitting procedure, to the form code stream parallel encoding after isolation and scrambling, generate 1 circuit-switched data transmission frame, as the output of data multiplexing device system.
2. one according to claim 1 spaceborne high-speed data multiplexer system, it is characterized in that: described packet module is implemented as: when dividing into groups according to transmission priority, according to inhomogeneity information source data to the difference of requirement of real-time, information source data the highest for requirement of real-time are divided at the 1st group, the like, information source data minimum for requirement of real-time are divided at the 5th group; When dividing into groups according to the strategy of equilibrium criterion amount, add up the valid data amount of 30 tunnel information source data, according to average amount principle, 30 tunnel information source data are divided into 5 groups of data.
3. one according to claim 1 spaceborne high-speed data multiplexer system, is characterized in that: described data subpackage module is implemented as:
(1) the corresponding every road information source data often organizing data, when the packet of these information source data is split, the segment data formed and segment information need buffer memory in sheet, set up two RAM in FPGA inside respectively and realize buffer memory in sheet, i.e. segment data RAM and segment information RAM, wherein segment data RAM is used for buffer memory segment data, segment information RAM is used for buffer memory segment information, segment information comprises fragment counter, for the BPDU top guide of the byte length of identified segments data, when carrying out buffer memory in sheet, segment data and segment information are write each self-corresponding RAM respectively,
(2) synchrodata reading is carried out to two RAM, when namely reading the data of a certain address field of segment data RAM, read the data of segment information RAM appropriate address section simultaneously, the data of reading are organized, and add frame alignment word, virtual channel identifier, form protocol element data;
(3) 5 groups of data form 5 groups of protocol element data.
4. one according to claim 1 spaceborne high-speed data multiplexer system, is characterized in that: SDRAM optimal control module concrete grammar is:
(1) correspondence often organizes protocol element data, uses 1 SDRAM as the outer buffer memory of sheet;
(2) on the sdram after electric initialization, by the control and optimize of SDRAM for writing process, read procedure and null process, according to refresh cycle of SDRAM, operating frequency and protocol data unit length, determine a work period, above-mentionedly writing process, switching between read procedure and null process;
(3) perform when meeting SDRAM write condition and write process, by protocol element data write SDRAM, meet when SDRAM reads condition and perform read procedure, read SDRAM data genaration virtual channel data, when not meeting the write condition of SDRAM or read condition, perform null process;
(4) 5 groups of protocol element data form 5 groups of virtual channel data.
5. one according to claim 1 spaceborne high-speed data multiplexer system, is characterized in that: described virtual channel schedule module is implemented as:
(1) correspondence often organizes virtual channel data, need buffer memory in sheet when dynamic dispatching management, set up 1 formatted data RAM in FPGA inside, for the digital independent frequency of the outer buffer memory of trimmer, and reading data are carried out buffer memory in sheet, 5 groups of corresponding 5 formatted data RAM of virtual channel data;
(2) carry out Read-write Catrol according to the buffer data size of formatted data RAM to form data RAM, read-write operation is independent, produces 5 groups of formatted datas when reading 5 formatted data RAM;
(3) 1 group of empty frame is produced by infilled frame unit;
(4) 5 groups of formatted datas and 1 group of empty frame are carried out data multiplexing, be combined into 1 road AOS form code stream.
6. one according to claim 1 spaceborne high-speed data multiplexer system, is characterized in that: described channel coding module is implemented as:
(1) 1 road AOS form code stream is received, FIFO is set up in FPGA inside, with the synchronised clock of form code stream by AOS form code stream write FIFO, FIFO is read with local clock, for eliminating the shake that high frequency clock is introduced in process and transmitting procedure, and improve the stability of interface adaptability and system;
(2) data structure for making above-mentioned FIFO isolation not affect AOS form code stream, carries out frame format arrangement to the formatted data read from FIFO, recovers its data structure;
(3) chnnel coding and scrambling are carried out to formatted data, generate data transmission frames.
7. a spaceborne high-speed data multiplexer implementation method, is characterized in that performing step is as follows:
(1) receive 30 tunnel information source data, be divided into 5 groups according to the strategy of transmission priority or equilibrium criterion amount, often organize 6 circuit-switched data;
(2) 5 groups of data of packet module are received, every Zu Zhongmei road information source number according to this packet is unit input, described packet is split, form some segment datas, produce some segment informations in split process simultaneously, segment information and segment data are organized, generates protocol element data, 5 groups of corresponding 5 groups of protocol element data of data;
(3) receive 5 groups of protocol element data of data subpackage module, write 5 SDRAM respectively and carry out buffer memory, under reading request signal, read 5 SDRAM data, form 5 groups of virtual channel data;
(4) receive 5 groups of virtual channel data, and produce 1 group of empty frame by infilled frame unit, dynamic dispatching management and multiple connection are carried out to above-mentioned 5 groups of virtual channel data, is combined into 1 road form code stream;
(5) 1 road form code stream is received, isolated by local clock and FIFO, eliminate the shake that high frequency clock is introduced in process and transmitting procedure, to the form code stream parallel encoding after isolation and scrambling, generate 1 circuit-switched data transmission frame, as the output of data multiplexing device system.
CN201210375466.0A 2012-09-29 2012-09-29 Satellite-borne high-speed data multiplexer system and realizing method thereof CN102932696B (en)

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