CN106776357A - A kind of fifo controller of multichannel read-write multicapacity selection - Google Patents
A kind of fifo controller of multichannel read-write multicapacity selection Download PDFInfo
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Abstract
The invention discloses a kind of fifo controller of multichannel read-write multicapacity selection, belong to the technical field of digital integrated electronic circuit.Controller includes：Fifo control circuit, user SRAM read-write control circuits, address decoding circuitry, multiplexer circuit, SRAM memory bank circuits.The controller distributes current FIFO capacity according to system input capacity selection signal, carry out dividing the data space for obtaining the similar FIFO operations of each user equipment to removing the SRAM memory banks circuit after FIFO takes up room, the similar FIFO operations of the read-write operation of FIFO and system selected user equipment according to selected by the selection signal completion system that address decoding circuitry is exported, it is optional FIFO capacity to be realized using same Large Copacity SRAM, and with the unappropriated SRAM address spaces of miscellaneous equipment share and access FIFO, incorporate full chip SRAM memory banks, improve resource utilization.
Description
Technical field
The invention discloses a kind of fifo controller of multichannel read-write multicapacity selection, belong to the technology of digital integrated electronic circuit
Field.
Background technology
FIFO（First In First Out）, i.e. the abbreviation of push-up storage, in system design, in order to increase
Data transmission problems between message transmission rate, mass disposal data flow, solution different clocks domain system, it is usually used
FIFO memory.
Common FIFO memory typically has two kinds of constituted modes：One kind is made up of shift register array, another
It is to be made up of the two-port RAM with reading and write address pointer.According to the clock zone that FIFO works, again can be by FIFO memory
It is divided into synchronization fifo and the class of asynchronous FIFO two, synchronization fifo refers to read clock and write clock for same clock, and asynchronous FIFO
Refer to that reading clock is two clocks independent mutually with clock is write.The use of FIFO widely, wherein again constituted with by SRAM
The more compact practicalities of FIFO, the present invention proposes to improve primarily directed to the FIFO that is made up of SRAM.
In realization is typically designed, one piece of SRAM is only used for realizing a FIFO that the capacity of monolithic SRAM is generally used for
The capacity of the FIFO of caching is much bigger, then, the SRAM of Large Copacity only realizes that a FIFO can waste remaining depositing
Storage space.When especially SRAM application demands are more or need the design requirements such as multiple capacity different FIFO, multiple SRAM are remained
Remaining waste of storage space is more serious, and resource utilization is also than relatively low.
The content of the invention
Goal of the invention of the invention is directed to the deficiency of above-mentioned background technology, there is provided a kind of multichannel read-write multicapacity selection
Fifo controller, realize FIFO capacity be adjusted flexibly and SRAM residues memory bank space makes full use of, solve
One piece of SRAM is only used to realize that a FIFO has the low technical problem of resource utilization.
The present invention is adopted the following technical scheme that for achieving the above object：
A kind of fifo controller of multichannel read-write multicapacity selection, including：
Fifo control circuit, current FIFO capacity is distributed according to system input capacity selection signal, is adjusted current FIFO and is read address
Signal and current FIFO writing address signals,
User's SRAM read-write control circuits, receive the current FIFO capacity indication signal of fifo control circuit output, according to SRAM
The residual capacity that memory bank circuit removes after current FIFO capacity is the read/write address of the similar FIFO operations of each user equipment allocation,
Address decoding circuitry, the selection of current FIFO and user equipment according to selected by system equipment address signal exports sign system
Signal,
Multiplexer circuit, the current FIFO for receiving fifo control circuit output reads address signal and current FIFO write addresses letter
Number, the read/write address of the similar FIFO operations of each user equipment of user SRAM read-write control circuits output, address decoding circuitry it is defeated
The selection signal for going out, the similar FIFO operations of the read-write operation and system selected user equipment of current FIFO selected by completion system,
And,
SRAM memory bank circuits, with the current FIFO memory banks space and each user equipment that are divided according to current FIFO capacity
The data back space of similar FIFO operations.
As multichannel read-write multicapacity select fifo controller further prioritization scheme, be similar to FIFO operation include but
It is not limited to RAM read-write operations, stack manipulation.
The further prioritization scheme of the fifo controller selected as multichannel read-write multicapacity, fifo control circuit includes：
FIFO Capacity Selection circuits, the system input capacity selection signal received according to its input and SRAM memory bank circuits
The threshold value in middle different bank space selects current FIFO capacity,
Current length signal generating circuit, the numerical relation of value according to current length signal and current FIFO capacity, FIFO write
Data enable signal, FIFO and read data enable signal, and current length signal is adjusted with empty principle is read according to Writing overflow is prevented
Value,
Read address signal produce circuit, during FIFO read operations are carried out, according to current FIFO read address signal with it is current
The numerical relation of FIFO capacity adjusts the value that current FIFO reads address signal, and,
Writing address signal produces circuit, and address signal sum and current FIFO capacity are read according to current length signal and current FIFO
Numerical relation adjust current FIFO writing address signals.
Further, the FIFO Capacity Selections circuit in the fifo controller of multichannel read-write multicapacity selection passes through multichannel
Selector realizes that the threshold value in different bank space in the input input SRAM memory bank circuits of MUX, multichannel is selected
The selection terminating systems input capacity selection signal of device is selected, MUX exports current FIFO capacity.
Further, the current length signal generating circuit in the fifo controller of multichannel read-write multicapacity selection：
FIFO write data enable signal effectively and current length signal value in current FIFO ranges of capacity when, to current length signal
Value add one and carry out FIFO write operations, otherwise, read that data enable signal effectively and the value of current length signal is more than zero in FIFO
When subtract one to the value of current length signal and carry out FIFO read operations.
Further, the current length signal generating circuit bag in the fifo controller of multichannel read-write multicapacity selection
Include：Two alternative data selectors and d type flip flop,
First alternative data selector, its selection end input FIFO reads data enable signal reading data and enables signal effectively and work as
Logic discriminant of the preceding length signals value more than 0, the value that its 1 input input current length signal subtracts,
Second alternative data selector, its selection end input FIFO write enable signal is effective and current length signal value is current
Logic discriminant in FIFO ranges of capacity, the value that its 1 input input current length signal adds, its 0 input termination first
The output end of alternative data selector,
D type flip flop, the output end of its input the second alternative data selector of termination, its output termination the first alternative data choosing
Select 0 input of device.
Further, the reading address signal in the fifo controller of multichannel read-write multicapacity selection produces circuit：
Read data enable signal effectively in FIFO and current length signal is more than in the case of 0：Current FIFO reads address signal and exists
When in current FIFO ranges of capacity, reading address signal to current FIFO is carried out plus an operation, until current FIFO reads address signal
During beyond current FIFO ranges of capacity, reading address signal to current FIFO carries out rezero operation；Kept in the case of remaining current
It is constant that FIFO reads address signal.
Further, the reading address signal generation circuit in the fifo controller of multichannel read-write multicapacity selection includes：
Two alternative data selectors and d type flip flop,
First alternative data selector, its selection end is input into current FIFO and reads the logic that address signal is equal to current FIFO capacity
Discriminate, its 0 input is input into current FIFO and reads the value that address signal adds, and its 1 input is input into 0,
Second alternative data selector, its selection end input FIFO reads data enable signal effectively and current length signal is more than
0 logic discriminant, the output end of its 1 input the first alternative data selector of termination,
D type flip flop, the output end of its input the second alternative data selector of termination, its output termination the second alternative data choosing
Select 0 input of device.
Further, the writing address signal in the fifo controller of multichannel read-write multicapacity selection produces circuit：
When current length signal reads address signal sum in current FIFO ranges of capacity with current FIFO, with current length signal
With current FIFO read address signal and be current FIFO writing address signals,
When current length signal reads address signal sum beyond current FIFO ranges of capacity with current FIFO, by current length signal
The value for reading to be subtracted again after address signal is cumulative current FIFO capacity with current FIFO assigns current FIFO writing address signals.
Further, the writing address signal in the fifo controller of multichannel read-write multicapacity selection produces circuit to pass through one
Alternative data selector realizes that selection end input current length signal and the current FIFO of the alternative data selector read ground
Location signal sum is more than the logic discriminant of current FIFO capacity, and the 0 input input of the alternative data selector is current long
Degree signal and current FIFO read address signal sum, the alternative data selector 1 input input current length signal and
Current FIFO reads to subtract the value of current FIFO capacity after address signal is cumulative again.
The present invention uses above-mentioned technical proposal, has the advantages that：FIFO capacity is distributed by fifo control circuit
And be system current FIFO operation distribution SRAM read/write address, by user SRAM read-write control circuits and address decoding circuitry
Design realizes other user equipment share and access unappropriated SRAM address spaces of FIFO, and sram chip storage can be adjusted flexibly
The division in body space simultaneously makes full use of the SRAM address spaces not taken by FIFO, has effectively integrated SRAM memory banks, improves
Resource utilization.
Brief description of the drawings
Fig. 1 is the system block diagram of fifo controller of the present invention.
Fig. 2 is the block diagram of FIFO Capacity Selection circuits.
Fig. 3 is to read the block diagram that address signal produces circuit.
Fig. 4 is the block diagram of current length signal generating circuit.
Fig. 5 is the block diagram that writing address signal produces circuit.
Label declaration in figure：101st, fifo control circuit, 102, user's SRAM read-write control circuits, 103, address decoding electricity
Road, 104, multiplexer circuit, 105, SRAM memory bank circuits.
Specific embodiment
The technical scheme invented is described in detail below in conjunction with the accompanying drawings.
The fifo controller of multichannel of the present invention read-write multicapacity selection as shown in figure 1, including：Fifo control circuit
101st, user SRAM read-write control circuits 102, address decoding circuitry 103, multiplexer circuit 104 and SRAM memory bank circuits
105。
Fifo control circuit 101：Current FIFO capacity is selected according to system input capacity selection signal fifo_size, is held
Amount instruction signal is depth, output capacity indication signal depth to user SRAM read-write control circuits 102；FIFO is write into number
According to wr_din outputs to fifo_din；FIFO is write into data and enables signal wr_en outputs to fifo_wr；FIFO readings data are made
Fifo_rd is arrived in the rd_en outputs of energy signal；In addition, fifo control circuit 101 exports the reading address signal fifo_raddr to SRAM
（I.e. current FIFO reads address signal）With writing address signal fifo_waddr（I.e. current FIFO writing address signals）.The above 5 is defeated
Go out signal and export multiplexer circuit 104.
User SRAM read-write control circuits 102, are made up of multiple User Defined SRAM read-write control circuits, are input into FIFO
The capacity indication signal depth that control circuit 101 is produced.Herein according to SRAM remaining space sizes, expansible N number of SRAM read-writes
Control submodule user1_ctr1 to userN_ctr1, first submodule output write-in data user1_din, read address signal
User1_raddr, writing address signal user1_waddr, read data and enable signal user1_rd, write data and enable signal user1_
wr.The like, n-th submodule output write-in data userN_din reads address signal userN_raddr, writing address signal
UserN_waddr, reads data and enables signal userN_rd, writes data and enables signal userN_wr.Above signal exports many
Road selection circuit 104.
Address decoding circuitry 103, it is system equipment address signal dev_addr to be input into, to system equipment address signal dev_
Addr address decodings treatment after output multi-channel selection signal sel to multiplexer circuit 104, the multi-path choice characterization system
Selected current FIFO and user equipment.
Multiplexer circuit 104, is input into 5 tunnel control signals, the user SRAM read-write controls for the output of fifo control circuit 101
The N roads signal of the output of circuit processed 102 and the multi-path choice signal sel of the output of address decoding circuitry 103, meanwhile, export SRAM
Write data signal din, SRAM read address signal raddr, and SRAM write address signal waddr, SRAM read data and enable signal rd,
SRAM write data enable signal wr, the tunnel signal output of the above 5 to SRAM memory banks circuit 105.
SRAM memory banks circuit 105 is according to current FIFO capacity and the similar FIFO read-writes of user SRAM read-write control circuits
The memory bank space of address distribution, is input into as SRAM write data-signal din, SRAM of the output of multiplexer circuit 104 read address
Signal raddr, SRAM write address signal waddr, SRAM read data and enable signal rd, SRAM write data enable signal wr, output
It is SRAM reading data signals dout.Fifo space are current FIFO memory banks space, user1 space to userN space
It is the data back space of the similar FIFO operations of each user equipment, similar FIFO operations include RAM read-write operations, storehouse behaviour
Make etc..
Fifo control circuit 101 produces circuit, current length signal to produce by FIFO Capacity Selections circuit, reading address signal
Circuit and writing address signal produce circuit to constitute.
FIFO Capacity Selections circuit according to system input capacity selection signal fifo_size as shown in Fig. 2 determine current
The capacity depth of FIFO.FIFO Capacity Selections circuit can realize that the input of MUX is input into by a MUX
The threshold value Threshold_1 to Threshold_n in different bank space in SRAM memory banks circuit 105, MUX
Selection terminating systems input capacity selection signal fifo_size, MUX exports current FIFO capacity depth.
Reading address signal produces circuit as shown in Figure 3：When FIFO reading data enable signals rd_en is effective, current length letter
Number len_addr reads current FIFO address letter more than zero and when current FIFO reads address signal r_addr and is not equal to depth-1
Number r_addr adds one carries out read operation, until FIFO reads address signal r_addr when being equal to depth-1, FIFO reads address signal r_
Addr is zeroed out；FIFO reading address signals r_addr keeps constant in the case of other.Reading address signal produces the circuit specifically can be by
Two alternative data selectors and d type flip flop realization, the selection end input logic discriminate of the first alternative data selector：
R_addr==(depth-1), the 0 input input r_addr+1 of the first alternative data selector, the choosing of the first alternative data
Select the 1 input input 0 of device, the selection end input logic discriminate of the second alternative data selector：rd_en&&(len_
addr>0), the output end of 1 input the first alternative data selector of termination of the second alternative data selector, d type flip flop
The output end of input the second alternative data selector of termination, the 0 of the output second alternative data selector of termination of d type flip flop
Input.
Current length signal generating circuit is as shown in Figure 4：When FIFO writes, data enable signal wr_en is effective and FIFO is current
When length signals len_addr is less than current FIFO capacity depth, FIFO current length signals len_addr adds one；Otherwise, when
When FIFO reading data enable signals rd_en is effectively and FIFO current length signals len_addr is more than zero, FIFO current lengths letter
Number len_addr subtracts one.Current length signal generating circuit specifically realized by two alternative data selectors and d type flip flop, the
The selection end input logic discriminate of one alternative data selector：rd_en&&(len_addr>0), the first alternative data choosing
Select the 1 input input len_addr-1 of device, the selection end input logic discriminate of the second alternative data selector：wr_
en&&( len_addr<Depth), the 1 input input len_addr+1 of the second alternative data selector, the second alternative
The output end of 0 input the first alternative data selector of termination of data selector, the input of d type flip flop terminates the second alternative
The output end of data selector, 0 input of the output first alternative data selector of termination of d type flip flop.
Writing address signal produces circuit as shown in Figure 5：When FIFO current length signals len_addr is plus reading address signal
When r_addr is more than depth-1, FIFO write addresses w_addr is equal to FIFO current length signals len_addr and reads ground plus FIFO
Location signal r_addr's and subtract FIFO and currently select capacity depth；Otherwise, FIFO write addresses w_addr is currently long equal to FIFO
Degree signal len_addr reads the sum of address signal r_addr plus FIFO.Writing address signal generation circuit specifically can be by one or two choosings
The realization of one data selector, the selection end input logic discriminate of the alternative data selector：len_addr>( depth-1-
R_addr), 0 input of the alternative data selector is input into len_addr+ r_addr, the 1 of the alternative data selector
Input input len_addr+ r_addr-depth.
Read-write operation control and the control of read/write address for fifo control circuit 101 to SRAM memory banks above
Journey, read-write operation control of the user SRAM read-write control circuits 102 to SRAM memory banks can be accessed directly.If by user
Submodule example inside SRAM read-write control circuits 102 turns to fifo control circuit, then the achievable multiple FIFO of the present invention is total to
Same SRAM is used, this scheme can be considered a kind of expansion deformation scheme of the invention, other similar expansion deformation schemes should also be answered
Put protection scope of the present invention under.
Claims (10)
1. the fifo controller that a kind of multichannel read-write multicapacity is selected, it is characterised in that including：
Fifo control circuit（101）, current FIFO capacity is distributed according to system input capacity selection signal, adjust current FIFO and read
Address signal and current FIFO writing address signals,
User's SRAM read-write control circuits（102）, receive fifo control circuit（101）The current FIFO capacity of output indicates letter
Number, according to SRAM memory bank circuits（105）The residual capacity after current FIFO capacity is removed for each user equipment allocation is similar
The read/write address of FIFO operations,
Address decoding circuitry（103）, current FIFO and user equipment according to selected by system equipment address signal exports sign system
Selection signal,
Multiplexer circuit（104）, receive fifo control circuit（101）The current FIFO of output reads address signal and current FIFO
Writing address signal, user's SRAM read-write control circuits（102）The read/write address of the similar FIFO operations of each user equipment of output,
Location decoding circuit（103）The selection signal of output, the read-write operation and system selected user of current FIFO selected by completion system set
Standby similar FIFO operations, and,
SRAM memory bank circuits（105）, with the current FIFO memory banks space divided according to current FIFO capacity and each use
The data back space of the similar FIFO operations of family equipment.
2. the fifo controller that a kind of multichannel read-write multicapacity is selected according to claim 1, it is characterised in that described similar
FIFO is operated including but not limited to RAM read-write operations, stack manipulation.
3. the fifo controller that a kind of multichannel read-write multicapacity is selected according to claim 1, it is characterised in that FIFO is controlled
Circuit（101）Including：
FIFO Capacity Selection circuits, the system input capacity selection signal received according to its input and SRAM memory bank circuits
（105）The threshold value in middle different bank space selects current FIFO capacity,
Current length signal generating circuit, the numerical relation of value according to current length signal and current FIFO capacity, FIFO write
Data enable signal, FIFO and read data enable signal, and current length signal is adjusted with empty principle is read according to Writing overflow is prevented
Value,
Read address signal produce circuit, during FIFO read operations are carried out, according to current FIFO read address signal with it is current
The numerical relation of FIFO capacity adjusts the value that current FIFO reads address signal, and,
Writing address signal produces circuit, and address signal sum and current FIFO capacity are read according to current length signal and current FIFO
Numerical relation adjust current FIFO writing address signals.
4. a kind of fifo controller that multichannel read-write multicapacity is selected according to claim 3, it is characterised in that the FIFO
Capacity Selection circuit realizes that the input of MUX is input into SRAM memory bank circuits by MUX（105）In not
With the threshold value in memory bank space, the selection terminating systems input capacity selection signal of MUX, MUX output is worked as
Preceding FIFO capacity.
5. the fifo controller that a kind of multichannel read-write multicapacity is selected according to claim 3, it is characterised in that described current
Length signals produces circuit：Data enable signal is write in FIFO effectively and the value of current length signal is in current FIFO ranges of capacity
When interior, adding one to the value of current length signal carries out FIFO write operations, and otherwise, reading data in FIFO, to enable signal effectively and current
Subtracting one to the value of current length signal when the value of length signals is more than zero carries out FIFO read operations.
6. the fifo controller that a kind of multichannel read-write multicapacity is selected according to claim 5, it is characterised in that described current
Length signals generation circuit includes：Two alternative data selectors and d type flip flop, the first alternative data selector, its choosing
Select end input FIFO and read data enable signal effectively and logic discriminant of the current length signal value more than 0, the input of its 1 input
The value that current length signal subtracts one,
Second alternative data selector, its selection end input FIFO write enable signal is effective and current length signal value is current
Logic discriminant in FIFO ranges of capacity, the value that its 1 input input current length signal adds, its 0 input termination first
The output end of alternative data selector,
D type flip flop, the output end of its input the second alternative data selector of termination, its output termination the first alternative data choosing
Select 0 input of device.
7. a kind of fifo controller that multichannel read-write multicapacity is selected according to claim 3, it is characterised in that the reading ground
Location signal generating circuit：
Read data enable signal effectively in FIFO and current length signal is more than in the case of 0：Current FIFO reads address signal and exists
When in current FIFO ranges of capacity, reading address signal to current FIFO is carried out plus an operation, until current FIFO reads address signal
During beyond current FIFO ranges of capacity, reading address signal to current FIFO carries out rezero operation；Kept in the case of remaining current
It is constant that FIFO reads address signal.
8. a kind of fifo controller that multichannel read-write multicapacity is selected according to claim 7, it is characterised in that the reading ground
Location signal generating circuit includes：Two alternative data selectors and d type flip flop,
First alternative data selector, its selection end is input into current FIFO and reads the logic that address signal is equal to current FIFO capacity
Discriminate, its 0 input is input into current FIFO and reads the value that address signal adds, and its 1 input is input into 0,
Second alternative data selector, its selection end input FIFO reads data enable signal effectively and current length signal is more than
0 logic discriminant, the output end of its 1 input the first alternative data selector of termination,
D type flip flop, the output end of its input the second alternative data selector of termination, its output termination the second alternative data choosing
Select 0 input of device.
9. the fifo controller that a kind of multichannel read-write multicapacity is selected according to claim 3, it is characterised in that described to write ground
Location signal generating circuit：
When current length signal reads address signal sum in current FIFO ranges of capacity with current FIFO, with current length signal
With current FIFO read address signal and be current FIFO writing address signals,
When current length signal reads address signal sum beyond current FIFO ranges of capacity with current FIFO, by current length signal
The value for reading to be subtracted again after address signal is cumulative current FIFO capacity with current FIFO assigns current FIFO writing address signals.
10. the fifo controller that a kind of multichannel read-write multicapacity is selected according to claim 9, it is characterised in that described to write
Address signal produces circuit to be realized by an alternative data selector, and the selection end input of the alternative data selector is current
Length signals reads logic discriminant of the address signal sum more than current FIFO capacity, alternative data selection with current FIFO
0 input input current length signal and the current FIFO of device read address signal sum, 1 input of the alternative data selector
End input current length signal and current FIFO read to subtract the value of current FIFO capacity after address signal is cumulative again.
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| CN109271333A (en) * | 2017-07-17 | 2019-01-25 | 深圳市中兴微电子技术有限公司 | A kind of SRAM control method and controller, control system |
| CN109960664A (en) * | 2019-03-19 | 2019-07-02 | 西安微电子技术研究所 | A kind of FIFO control that the capacity that multimode is shared is distributed unitedly and independently used |
| CN111722827A (en) * | 2020-05-28 | 2020-09-29 | 江苏方天电力技术有限公司 | Efficient DDR access method and application |
| CN113485672A (en) * | 2021-09-07 | 2021-10-08 | 苏州浪潮智能科技有限公司 | Information generation method, device, equipment and medium based on FIFO memory |
| CN113760795A (en) * | 2021-08-30 | 2021-12-07 | 浪潮电子信息产业股份有限公司 | Asynchronous FIFO memory read-write control method, device and equipment |
| CN113900975A (en) * | 2021-12-08 | 2022-01-07 | 苏州浪潮智能科技有限公司 | Synchronous FIFO |
| CN115857806A (en) * | 2022-11-30 | 2023-03-28 | 深圳市亿诚伟业电子有限公司 | Integrated circuit system of multifunctional memory and control method thereof |
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| CN113900975B (en) * | 2021-12-08 | 2022-03-08 | 苏州浪潮智能科技有限公司 | Synchronous FIFO |
| CN113900975A (en) * | 2021-12-08 | 2022-01-07 | 苏州浪潮智能科技有限公司 | Synchronous FIFO |
| WO2023103337A1 (en) * | 2021-12-08 | 2023-06-15 | 苏州浪潮智能科技有限公司 | Synchronous fifo |
| CN115857806A (en) * | 2022-11-30 | 2023-03-28 | 深圳市亿诚伟业电子有限公司 | Integrated circuit system of multifunctional memory and control method thereof |
| CN115857806B (en) * | 2022-11-30 | 2023-10-20 | 深圳市亿诚伟业电子有限公司 | Integrated circuit system of multifunctional memory and control method thereof |
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