CN102169425B - First-in first-out (FIFO) buffer circuit having four operating modes - Google Patents
First-in first-out (FIFO) buffer circuit having four operating modes Download PDFInfo
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- CN102169425B CN102169425B CN 201010114384 CN201010114384A CN102169425B CN 102169425 B CN102169425 B CN 102169425B CN 201010114384 CN201010114384 CN 201010114384 CN 201010114384 A CN201010114384 A CN 201010114384A CN 102169425 B CN102169425 B CN 102169425B
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Abstract
The invention relates to a first-in first-out (FIFO) buffer circuit having four operating modes. The circuit comprises a dual-port static random access memory (SRAM), an access mode switching control logic unit, a written address 0 generation logic unit, a read address 0 generation logic unit, a written address 1 generation logic unit, a read address 1 generation logic unit and an FIFO state generation logic unit. The FIFO buffer circuit provided by the invention has the four operating modes, and when data transmission is switched dynamically among the four operating modes, supporting of four data transmission modes by only one FIFO can be realized, and circuit design of a system is simplified effectively, so the FIFO buffer circuit provided by the invention is applied to complicated environments.
Description
Technical field
The present invention designs a kind of FIFO buffer circuit, relates in particular to a kind of FIFO buffer circuit with four kinds of mode of operations.
Background technology
FIFO (first in first out, first-in first-out) buffer memory is circuit structure commonly used in the Design of Digital Circuit, and its main function comprises: the difference of coupling reading and writing speed, the data path of isolation different clock-domains.
The memory bank of FIFO buffer memory is generally the SRAM (Static Random AccessMemory, static RAM) of dual-port, and a port is as write port, and another port is as read port.The structured flowchart of common FIFO as shown in Figure 2, the port in SRAM left side is used for read operation, the port on SRAM right side is used for write operation, fifo status produces logical block and indicates and other state for generation of " expire " sign, " sky " of FIFO.
When the clock 0 among Fig. 2 and clock 1 were in different clock-domains, fifo status produces logical block need carry out respective handling to the signal of cross clock domain.When having from clock zone 1 to clock zone 2 and clock zone 2 to clock zone 1 data transmission time the one of (transmission direction for the two) in the system simultaneously, the design of fifo circuit will adjust accordingly.Two FIFO are adopted in the design that has, and are respectively applied to the data transmission of both direction; The design that has is put into a clock zone with FIFO, but need to another clock zone read enable, write enable, signal such as read data carries out cross clock domain and handles.These processing modes have increased the waste of design circuit and the complexity of circuit design in the circuit system.
Summary of the invention
The object of the invention provides a kind of FIFO buffer circuit with four kinds of mode of operations, can realize the data transmission of four kinds of patterns, can reach system's designing requirement with the FIFO of lesser amt, can simplify the design of system's cross clock domain circuit simultaneously.
A kind of FIFO buffer circuit with four kinds of mode of operations comprises dual-port SRAM, access module switch control logic unit, write address 0 formation logic unit, reads 0 formation logic unit, address, write address 1 formation logic unit, reads 1 formation logic unit, address and fifo status generation logical block.
Dual-port SRAM is used for store data;
Access module switch control logic unit, when being used for the access module switching, the switching of control reading, writing address;
Write address 0 formation logic unit is used for generating write address 0;
Read 0 formation logic unit, address, be used for generating and read address 0;
Write address 1 formation logic unit is used for generating write address 1;
Read 1 formation logic unit, address, be used for generating and read address 1;
Fifo status produces logical block, is used for generating the status signal of FIFO.
The data transmission of the present invention in clock zone 0 and clock zone 1 comprises four kinds of patterns:
Pattern one: data transmission is from clock zone 0 to clock zone 1;
Pattern two: data transmission is from clock zone 1 to clock zone 0;
Pattern three: data transmission is from clock zone 0 to clock zone 0;
Pattern four: data transmission is from clock zone 1 to clock zone 1.
The clock 1 that relates in the content of the present invention and clock 2 not only can but also can be asynchronous clock for synchronous clock, and when clock 1 and clock 2 when being asynchronous, fifo status produces that logical block needs to read the address and writing address signal is encoded to Gray code.
Adopt a kind of FIFO buffer circuit with four kinds of mode of operations provided by the present invention, when data transmission (arbitrary moment has only a kind of pattern) when dynamically switching between above-mentioned four kinds of patterns, only can realize finishing support to four kinds of data-transmission modes with a FIFO, effectively simplified the circuit design of system, made FIFO buffer memory provided by the present invention be suitable for complex environment and use.
Description of drawings
Fig. 1 has the FIFO buffer circuit block diagram of four kinds of mode of operations
FIFO buffer circuit block diagram during Fig. 2 uses usually
Specific embodiments
Below in conjunction with accompanying drawing content provided by the present invention is described in detail:
Table 1 has provided the concrete implementation content of FIFO buffer circuit provided by the present invention in four kinds of patterns are switched:
Four kinds of patterns are respectively: pattern one, data transmission are from clock zone 0 to clock zone 1; Pattern two, data transmission are from clock zone 1 to clock zone 0; Pattern three, data transmission are from clock zone 0 to clock zone 0; Pattern four, data transmission are from clock zone 1 to clock zone 1.
| The pattern switching mode | The specific implementation operation |
| One to two | Write and enable to enable 0 and switch to write and enable 1 from writing; Read to enable to switch to and read to enable 0 from reading to enable 1; Write address switches to write address 1 from write address 0, and the value of write address 0 is composed to write address 1; Read the address and switch to and read address 0 from reading address 1, and the value of reading address 1 is composed to reading address 0. |
| One to three | Write and enable still to enable 0 for writing; Read to enable to switch to and read to enable 0 from reading to enable 1; Write address still is write address 0; Read the address and switch to and read address 0 from reading address 1, and the value of reading address 1 is composed to reading address 0. |
| One to four | Write and enable to enable 0 and switch to write and enable 1 from writing; Read to enable still for reading to enable 1; Write address switches to write address 1 from write address 0, and the value of write address 0 is composed to write address 1; Read the address still for reading address 1. |
| Two to one | Write and enable to enable 1 and switch to write and enable 0 from writing; Read to enable to switch to and read to enable 1 from reading to enable 0; Write address switches to write address 0 from write address 1, and the value of write address 1 is composed to write address 0; |
| Read the address and switch to and read address 1 from reading address 0, and the value of reading address 0 is composed to reading address 1. | |
| Two to three | Write and enable to enable 1 and switch to write and enable 0 from writing; Read to enable still to enable 0 for writing; Write address switches to write address 0 from write address 1, and the value of write address 1 is composed to write address 0.Read the address still for reading address 1; |
| Two to four | Write and enable still to enable 1 for writing; Read to enable can 0 to switch to from write-read and read to enable 1; Write address still is write address 1.Read the address and switch to and read address 1 from reading address 0, and the value of reading address 0 is composed to reading address 0; |
| Three to one | Write and enable still to enable 0 for writing; Read to enable to switch to and read to enable 1 from reading to enable 0; Write address is by still being write address 0; Read the address and switch to and read address 1 from reading address 0, and the value of reading address 0 is composed to reading address 0. |
| Three to two | Write and enable to enable 0 and switch to write and enable 1 by writing; Read to enable still for reading to enable 0; Write address switches to write address 1 by write address 0, and the value of write address 0 is composed to write address 1; Read the address still for reading address 0; |
| Three to four | Write and enable to enable 0 and switch to write and enable 1 by writing; Read to enable to switch to and read to enable 1 by reading to enable 0; Write address switches to write address 1 by write address 0, and the value of write address 0 is composed to write address 1; Read the address and switch to and read address 1 by reading address 0, and the value of reading address 0 is composed to reading address 1; |
| Four to one | Write and enable to enable 1 and switch to write and enable 0 by writing; Read to enable still for reading to enable 1; Write address switches to write address 0 by write address 1, and the value of write address 1 is composed to write address 0; Read the address still for reading address 1. |
| Four to two | Write and enable still to enable 1 for writing; Read to enable to switch to and read to enable 0 by reading to enable 1; Write address still is write address 1; |
| Read the address and switch to and read address 0 by reading address 1, and the value of reading address 1 is composed to reading address 0. | |
| Three to four | Write and enable to enable 1 and switch to write and enable 0 by writing; Read to enable to switch to and read to enable 0 by reading to enable 1; Write address switches to write address 0 by write address 1, and the value of write address 1 is composed to write address 0; Read the address and switch to and read address 0 by reading address 1, and the value of reading address 1 is composed to reading address 0; |
Table 1
The generation of the fifo status under four kinds of mode of operations describing in the table 1 is as shown in table 2:
| Pattern | The method of the generation of fifo status |
| One | Compare write address 0 and read address 1 |
| Two | Compare write address 1 and read address 0 |
| Three | Compare write address 0 and read address 0 |
| Four | Compare write address 1 and read address 1 |
Table 2
In specific embodiments, clock 1 and clock 2 not only can but also can be asynchronous clock for synchronous clock.When if clock 0 and clock 1 be asynchronous clock, then need when the comparison read/write address, the address will be read, write address is encoded to Gray code and compares.
Claims (3)
1. FIFO buffer circuit with four kinds of mode of operations, comprise dual-port SRAM, fifo status generation logical block, write address 0 formation logic unit, read 0 formation logic unit, address, write address 1 formation logic unit, read 1 formation logic unit, address, it is characterized in that: also comprise access module switch control logic unit, dynamic switching between four kinds of mode of operations of access module switch control logic unit controls, four kinds of mode of operations are: pattern one, data transmission are from clock zone 0 to clock zone 1; Pattern two, data transmission are from clock zone 1 to clock zone 0; Pattern three, data transmission are from clock zone 0 to clock zone 0; Pattern four, data transmission are from clock zone 1 to clock zone 1.
2. a kind of FIFO buffer circuit with four kinds of mode of operations as claimed in claim 1 is characterized in that: clock 1 and clock 2 are for synchronous clock or be asynchronous clock.
3. a kind of FIFO buffer circuit with four kinds of mode of operations as claimed in claim 2 is characterized in that: described clock 1 and clock 2 be during for asynchronous clock, and fifo status produces that logical block will be read the address and writing address signal is encoded to Gray code.
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| CN 201010114384 CN102169425B (en) | 2010-02-26 | 2010-02-26 | First-in first-out (FIFO) buffer circuit having four operating modes |
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| CN 201010114384 CN102169425B (en) | 2010-02-26 | 2010-02-26 | First-in first-out (FIFO) buffer circuit having four operating modes |
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| CN104794087B (en) * | 2015-04-09 | 2017-10-03 | 北京时代民芯科技有限公司 | Processing unit interface circuit in a kind of polycaryon processor |
| CN107577623A (en) * | 2017-07-19 | 2018-01-12 | 成都华微电子科技有限公司 | Cross clock domain asynchronous fifo and data processing method |
| CN111177048A (en) * | 2018-11-09 | 2020-05-19 | 珠海格力电器股份有限公司 | AHB bus equipment and data stream transmission method thereof |
| CN110825344A (en) * | 2019-11-12 | 2020-02-21 | 天津飞腾信息技术有限公司 | Asynchronous data transmission method and structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7230858B2 (en) * | 2005-06-28 | 2007-06-12 | Infineon Technologies Ag | Dual frequency first-in-first-out structure |
| CN101183303A (en) * | 2007-11-28 | 2008-05-21 | 北京中星微电子有限公司 | FIFO control circuit and control method |
| CN101477833A (en) * | 2009-01-08 | 2009-07-08 | 西安电子科技大学 | Clock controlled asynchronous FIFO memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7230858B2 (en) * | 2005-06-28 | 2007-06-12 | Infineon Technologies Ag | Dual frequency first-in-first-out structure |
| CN101183303A (en) * | 2007-11-28 | 2008-05-21 | 北京中星微电子有限公司 | FIFO control circuit and control method |
| CN101477833A (en) * | 2009-01-08 | 2009-07-08 | 西安电子科技大学 | Clock controlled asynchronous FIFO memory |
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