CN110825344A - Asynchronous data transmission method and structure - Google Patents

Asynchronous data transmission method and structure Download PDF

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Publication number
CN110825344A
CN110825344A CN201911100628.8A CN201911100628A CN110825344A CN 110825344 A CN110825344 A CN 110825344A CN 201911100628 A CN201911100628 A CN 201911100628A CN 110825344 A CN110825344 A CN 110825344A
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fifo memory
data
asynchronous
synchronous
asynchronous fifo
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Inventor
胡权
刘艳丽
张璐
张旭
冯彦朝
朱青山
徐华丽
江南
谢文俊
郭御风
张明
马卓
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Tianjin Feiteng Information Technology Co Ltd
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Tianjin Feiteng Information Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Abstract

The invention discloses an asynchronous data transmission method and a structure, when data needs to be written, the data is firstly written into a synchronous FIFO memory, when the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full, a logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, and transmits the data written into the synchronous FIFO memory into the asynchronous FIFO memory until the synchronous FIFO memory is empty or the asynchronous FIFO memory is full; when data needs to be read, the data is directly read from the asynchronous FIFO; the valid data entries of the current FIFO memory are known by querying the synchronous FIFO memory. The invention combines the synchronous FIFO memory and the asynchronous FIFO memory for use, thereby not only meeting the requirement of data cross-clock transmission, but also obtaining the effective data items in the current FIFO memory, reducing the logic complexity to the utmost extent, and solving the technical problem of poor reliability caused by uncertain relation between the continuous period of the read/write signal and the clock used by the FIFO memory in the prior art.

Description

Asynchronous data transmission method and structure
Technical Field
The present invention relates to the field of data transmission technologies, and in particular, to an asynchronous data transmission method and structure.
Background
In the design of a digital circuit, data transmission between different clock domains is generally realized by an asynchronous First In First Out (FIFO) storage mode; data transmission between the same clock domains is generally realized by adopting a synchronous FIFO storage mode. As shown in fig. 1, the basic interface signal of a conventional asynchronous FIFO memory includes two clock inputs, which are used as clocks for read/write control, respectively, and includes a full signal and an empty signal output for indicating the empty/full status of the current FIFO memory. The asynchronous FIFO can realize data transmission between two clock domains, and the correctness of data transmission is ensured. As shown in fig. 2, the basic interface signal of the conventional synchronous FIFO memory only includes a clock input, and both the read and write data signals are synchronous with the clock, compared to the asynchronous FIFO, because of the implementation characteristics of the synchronous FIFO, the basic interface signal includes a counter output for indicating the actual number of valid data entries in the current FIFO memory.
Synchronous FIFO and asynchronous FIFO can be selected according to actual application scenarios, but under some special application situations, not only needs to realize asynchronous transmission of data, but also needs to know current valid data entries, for example, data exchange across clocks, and data transmission is realized by adopting asynchronous FIFO. In order to meet the requirement of data cross-clock transmission and obtain effective data items in the current FIFO memory, the prior art adopts a synchronous FIFO memory as a buffer, synchronizes an input read/write enable signal to an FIFO clock domain, performs edge detection, and determines the empty and full state and the transmission result of the current FIFO according to the detection result.
Disclosure of Invention
In view of the above, the present invention provides an asynchronous data transmission method and structure with high reliability, which can not only satisfy the data cross-clock transmission, but also obtain the valid data entry in the current FIFO memory, and solve the technical problem of poor reliability caused by the uncertain relationship between the read/write signal duration period and the clock used by the FIFO memory in the prior art.
The invention provides an asynchronous data transmission method, which comprises the following steps:
1) when data needs to be written in, the data is firstly written in the synchronous FIFO memory, when the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full, the logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, and the data written in the synchronous FIFO memory is transmitted to the asynchronous FIFO memory until the synchronous FIFO memory is empty or the asynchronous FIFO memory is full;
2) when data needs to be read, the data is directly read from the asynchronous FIFO memory;
3) the valid data entry of the current FIFO memory is obtained by querying the count signal of the synchronous FIFO memory.
Optionally, the logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, sends a behavior of reading data of the synchronous FIFO memory and writing data of the asynchronous FIFO memory once at a clock edge of the asynchronous FIFO memory, transfers the data written into the synchronous FIFO memory into the asynchronous FIFO memory, and if the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full at this time, the logic module continues to enable the read signal of the synchronous FIFO memory and the write signal of the asynchronous FIFO memory, and sends a behavior of reading data of the synchronous FIFO memory and writing data of the asynchronous FIFO memory once at a clock edge of the asynchronous FIFO memory until the synchronous FIFO memory is empty or the asynchronous FIFO memory is full.
Optionally, after the data in the asynchronous FIFO memory is read, if the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full, the logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, sends a behavior of reading data of the synchronous FIFO memory and writing data of the asynchronous FIFO memory once at a clock edge of the asynchronous FIFO memory, transfers the data written into the synchronous FIFO memory to the asynchronous FIFO memory, and ensures that valid data can be continuously read.
Optionally, the asynchronous FIFO memory implements a data asynchronous function, the data depth is small, the synchronous FIFO memory implements a function of storing and providing valid data entries, and a proper depth is selected according to actual applications.
The invention also provides an asynchronous data transmission structure, comprising: the synchronous FIFO storage device comprises a synchronous FIFO storage device, a logic module and an asynchronous FIFO storage device, wherein the logic module is connected between the synchronous FIFO storage device and the asynchronous FIFO storage device, when data need to be written in, the data are firstly written in the synchronous FIFO storage device, when the synchronous FIFO storage device is not empty and the asynchronous FIFO storage device is not full, the logic module enables a read signal of the synchronous FIFO storage device and a write signal of the asynchronous FIFO storage device, and the data written in the synchronous FIFO storage device are transmitted to the asynchronous FIFO storage device until the synchronous FIFO storage device is empty or the asynchronous FIFO storage device is full; when data needs to be read, the data is directly read from the asynchronous FIFO memory; the valid data entry of the current FIFO memory is obtained by querying the count signal of the synchronous FIFO memory.
Optionally, the logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, sends a behavior of reading data of the synchronous FIFO memory and writing data of the asynchronous FIFO memory once at a clock edge of the asynchronous FIFO memory, transfers the data written into the synchronous FIFO memory into the asynchronous FIFO memory, and if the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full at this time, the logic module continues to enable the read signal of the synchronous FIFO memory and the write signal of the asynchronous FIFO memory, and sends a behavior of reading data of the synchronous FIFO memory and writing data of the asynchronous FIFO memory once at a clock edge of the asynchronous FIFO memory until the synchronous FIFO memory is empty or the asynchronous FIFO memory is full.
Optionally, after the data in the asynchronous FIFO memory is read, if the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full, the logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, sends a behavior of reading data of the synchronous FIFO memory and writing data of the asynchronous FIFO memory once at a clock edge of the asynchronous FIFO memory, transfers the data written into the synchronous FIFO memory to the asynchronous FIFO memory, and ensures that valid data can be continuously read.
Optionally, the asynchronous FIFO memory implements a data asynchronous function, the data depth is small, the synchronous FIFO memory implements a function of storing and providing valid data entries, and a proper depth is selected according to actual applications.
Compared with the prior art, the technical scheme of the invention has the following advantages: the asynchronous data transmission method of the invention adds a logic module between a synchronous FIFO memory and an asynchronous FIFO memory, when data is required to be written, the data is firstly written into the synchronous FIFO memory, when the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full, the logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, and transmits the data written into the synchronous FIFO memory into the asynchronous FIFO memory until the synchronous FIFO memory is empty or the asynchronous FIFO memory is full; when data needs to be read, the data is directly read from the asynchronous FIFO, and the effective data entry of the current FIFO memory is known by inquiring the synchronous FIFO memory. The invention combines the synchronous FIFO memory and the asynchronous FIFO memory for use, not only can satisfy the cross-clock transmission of data, but also can obtain the effective data items in the current FIFO memory, and furthest reduces the complexity of logic, and simultaneously solves the technical problem of poor reliability caused by uncertain relation between the continuous period of read/write signals and the clock used by the FIFO memory in the prior art.
Drawings
FIG. 1 is a schematic diagram of prior art asynchronous FIFO memory interface signals;
FIG. 2 is a schematic diagram of prior art synchronous FIFO memory interface signals;
FIG. 3 is a diagram of an asynchronous data transmission structure according to the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to only these embodiments. The invention is intended to cover alternatives, modifications, equivalents and alternatives which may be included within the spirit and scope of the invention.
In the following description of the preferred embodiments of the present invention, specific details are set forth in order to provide a thorough understanding of the present invention, and it will be apparent to those skilled in the art that the present invention may be practiced without these specific details.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the drawings are in simplified form and are not to precise scale, which is only used for convenience and clarity to assist in describing the embodiments of the present invention.
The asynchronous data transmission method comprises the following steps:
1) when data needs to be written in, the data is firstly written in the synchronous FIFO memory, when the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full, the logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, and the data written in the synchronous FIFO memory is transmitted to the asynchronous FIFO memory until the synchronous FIFO memory is empty or the asynchronous FIFO memory is full;
2) when the data needs to be read, the data is directly read out from the asynchronous FIFO memory,
3) during the process of reading data and writing data, the effective data entry of the current FIFO memory is obtained by inquiring the counting signal of the synchronous FIFO memory.
Specifically, the logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, and sends out a behavior of reading data of the synchronous FIFO memory and writing data of the asynchronous FIFO memory once at a clock edge of the asynchronous FIFO memory, and transfers the data written into the synchronous FIFO memory into the asynchronous FIFO memory, if the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full at the moment, the logic module continues to enable the read signal of the synchronous FIFO memory and the write signal of the asynchronous FIFO memory, and sends out a behavior of reading data of the synchronous FIFO memory and writing data of the asynchronous FIFO memory once at the clock edge of the asynchronous FIFO memory until the synchronous FIFO memory is empty or the asynchronous FIFO memory is full.
Furthermore, after the data in the asynchronous FIFO memory is read, if the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full, the logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, and sends a behavior of reading data of the synchronous FIFO memory and writing data of the asynchronous FIFO memory once at a clock edge of the asynchronous FIFO memory, and transfers the data written into the synchronous FIFO memory to the asynchronous FIFO memory, thereby ensuring that valid data can be continuously read.
The asynchronous FIFO memory realizes the function of data asynchronization, the depth of data is very small, the synchronous FIFO memory realizes the functions of storing and providing effective data items, and the proper depth is selected according to the practical application.
The invention also provides an asynchronous data transmission structure, comprising: the synchronous FIFO storage device comprises a synchronous FIFO storage device, a logic module and an asynchronous FIFO storage device, wherein the logic module is connected between the synchronous FIFO storage device and the asynchronous FIFO storage device, when data need to be written in, the data are firstly written in the synchronous FIFO storage device, when the synchronous FIFO storage device is not empty and the asynchronous FIFO storage device is not full, the logic module enables a read signal of the synchronous FIFO storage device and a write signal of the asynchronous FIFO storage device, and the data written in the synchronous FIFO storage device are transmitted to the asynchronous FIFO storage device until the synchronous FIFO storage device is empty or the asynchronous FIFO storage device is full; when data needs to be read, the data is directly read from the asynchronous FIFO memory; the valid data entry of the current FIFO memory is obtained by querying the count signal of the synchronous FIFO memory.
Specifically, the logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, and sends out a behavior of reading data of the synchronous FIFO memory and writing data of the asynchronous FIFO memory once at a clock edge of the asynchronous FIFO memory, and transfers the data written into the synchronous FIFO memory into the asynchronous FIFO memory, if the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full at the moment, the logic module continues to enable the read signal of the synchronous FIFO memory and the write signal of the asynchronous FIFO memory, and sends out a behavior of reading data of the synchronous FIFO memory and writing data of the asynchronous FIFO memory once at the clock edge of the asynchronous FIFO memory until the synchronous FIFO memory is empty or the asynchronous FIFO memory is full.
Furthermore, after the data in the asynchronous FIFO memory is read, if the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full, the logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, and sends a behavior of reading data of the synchronous FIFO memory and writing data of the asynchronous FIFO memory once at a clock edge of the asynchronous FIFO memory, and transfers the data written into the synchronous FIFO memory to the asynchronous FIFO memory, thereby ensuring that valid data can be continuously read.
The asynchronous FIFO memory realizes the function of data asynchronization, the depth of data is very small, the synchronous FIFO memory realizes the functions of storing and providing effective data items, and the proper depth is selected according to the practical application.
Fig. 3 illustrates a schematic diagram of an asynchronous data transmission architecture of the present invention. The asynchronous data transmission structure includes: the synchronous FIFO memory comprises a synchronous FIFO memory, a logic module and an asynchronous FIFO memory, wherein the logic module is connected between the synchronous FIFO memory and the asynchronous FIFO memory, when data need to be written, a full signal is detected to be 0, which indicates that the synchronous FIFO memory is not full, namely, an effective space is contained to store the data, therefore, the written data firstly enters the synchronous FIFO memory, if the logic module detects that neither an event signal nor an if signal is 1, namely, the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full, the logic module pulls up a read signal sync _ read of the synchronous FIFO memory and a write signal async _ write of the asynchronous FIFO memory, and sends out an action of reading the data of the synchronous FIFO memory and writing the data of the asynchronous FIFO memory once at the rising edge or the falling edge of a clock of the asynchronous FIFO memory clk1, and if the event signal and the if the event signal are both non-1 at the moment after the operation is finished, the logic module continues to pull up async _ write and sync _ read and continues to move data in the synchronous FIFO memory to the asynchronous FIFO memory on the rising or falling edge of the clk1 clock. If the event or the ifull signal is changed into 1, the logic module pulls down async _ write and sync _ read, and stops the data transfer between the synchronous FIFO memory and the asynchronous FIFO memory;
when data needs to be read, it is detected that an empty signal is 0, the data is directly read from the asynchronous FIFO memory, after the data is read, if the synchronous FIFO memory still contains data and the asynchronous FIFO memory is not full, namely neither an iempty signal nor an ifull signal is 1, the logic module raises signals of async _ write and sync _ read after the data is read, and writes effective data in one synchronous FIFO memory into the asynchronous FIFO memory on the rising edge or the falling edge of clk1, so that the effective data can be continuously read.
The entry of valid data currently present in the FIFO can be known by querying the count signal counter of the synchronous FIFO memory.
In the invention, the asynchronous FIFO realizes the function of data asynchronization, the data depth can be very small, the synchronous FIFO mainly has the functions of storing and providing effective data items, and the proper depth is selected according to the practical application.
By applying the method disclosed by the invention, the cross-clock transmission of data is realized through the asynchronous FIFO, the correctness of the transmission between asynchronous data can be effectively ensured, and the current effective data entry information can be obtained; and the invention is based on the module design of the existing synchronous FIFO memory and asynchronous FIFO memory, does not need to increase the fussy logic, and reduces the logic complexity to the utmost extent.
Although the embodiments have been described and illustrated separately, it will be apparent to those skilled in the art that some common techniques may be substituted and integrated between the embodiments, and reference may be made to one of the embodiments not explicitly described, or to another embodiment described.
The above-described embodiments do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the above-described embodiments should be included in the protection scope of the technical solution.

Claims (8)

1. An asynchronous data transmission method, comprising:
1) when data needs to be written in, the data is firstly written in the synchronous FIFO memory, when the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full, the logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, and the data written in the synchronous FIFO memory is transmitted to the asynchronous FIFO memory until the synchronous FIFO memory is empty or the asynchronous FIFO memory is full;
2) when data needs to be read, the data is directly read from the asynchronous FIFO memory;
3) the valid data entry of the current FIFO memory is obtained by querying the count signal of the synchronous FIFO memory.
2. Asynchronous data transmission method according to claim 1, characterized in that: the logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, sends a behavior of reading data of the synchronous FIFO memory and writing data of the asynchronous FIFO memory once at a clock edge of the asynchronous FIFO memory, transfers the data written into the synchronous FIFO memory into the asynchronous FIFO memory, and if the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full at the moment, the logic module continues to enable the read signal of the synchronous FIFO memory and the write signal of the asynchronous FIFO memory, and sends a behavior of reading data of the synchronous FIFO memory and writing data of the asynchronous FIFO memory once at the clock edge of the asynchronous FIFO memory until the synchronous FIFO memory is empty or the asynchronous FIFO memory is full.
3. Asynchronous data transmission method according to claim 1, characterized in that: after the data in the asynchronous FIFO memory is read, if the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full, the logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, sends out a behavior of reading the data of the synchronous FIFO memory and writing the data of the asynchronous FIFO memory once at the clock edge of the asynchronous FIFO memory, transmits the data written into the synchronous FIFO memory into the asynchronous FIFO memory, and ensures that effective data can be continuously read.
4. Asynchronous data transmission method according to claim 1, characterized in that: the asynchronous FIFO memory realizes the function of data asynchronization, the depth of data is very small, the synchronous FIFO memory realizes the functions of storing and providing effective data items, and the proper depth is selected according to the practical application.
5. An asynchronous data transmission structure, comprising: the synchronous FIFO storage device comprises a synchronous FIFO storage device, a logic module and an asynchronous FIFO storage device, wherein the logic module is connected between the synchronous FIFO storage device and the asynchronous FIFO storage device, when data need to be written in, the data are firstly written in the synchronous FIFO storage device, when the synchronous FIFO storage device is not empty and the asynchronous FIFO storage device is not full, the logic module enables a read signal of the synchronous FIFO storage device and a write signal of the asynchronous FIFO storage device, and the data written in the synchronous FIFO storage device are transmitted to the asynchronous FIFO storage device until the synchronous FIFO storage device is empty or the asynchronous FIFO storage device is full; when data needs to be read, the data is directly read from the asynchronous FIFO memory; the valid data entry of the current FIFO memory is obtained by querying the count signal of the synchronous FIFO memory.
6. Asynchronous data transmission structure according to claim 5, characterized in that: the logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, sends a behavior of reading data of the synchronous FIFO memory and writing data of the asynchronous FIFO memory once at a clock edge of the asynchronous FIFO memory, transfers the data written into the synchronous FIFO memory into the asynchronous FIFO memory, and if the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full at the moment, the logic module continues to enable the read signal of the synchronous FIFO memory and the write signal of the asynchronous FIFO memory, and sends a behavior of reading data of the synchronous FIFO memory and writing data of the asynchronous FIFO memory once at the clock edge of the asynchronous FIFO memory until the synchronous FIFO memory is empty or the asynchronous FIFO memory is full.
7. Asynchronous data transmission structure according to claim 5, characterized in that: after the data in the asynchronous FIFO memory is read, if the synchronous FIFO memory is not empty and the asynchronous FIFO memory is not full, the logic module enables a read signal of the synchronous FIFO memory and a write signal of the asynchronous FIFO memory, sends out a behavior of reading the data of the synchronous FIFO memory and writing the data of the asynchronous FIFO memory once at the clock edge of the asynchronous FIFO memory, transmits the data written into the synchronous FIFO memory into the asynchronous FIFO memory, and ensures that effective data can be continuously read.
8. Asynchronous data transmission structure according to claim 5, characterized in that: the asynchronous FIFO memory realizes the function of data asynchronization, the depth of data is very small, the synchronous FIFO memory realizes the functions of storing and providing effective data items, and the proper depth is selected according to the practical application.
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Application publication date: 20200221