CN107832249B

CN107832249B - System and method for three-wire realization and communication with peripheral equipment with SPI interface

Info

Publication number: CN107832249B
Application number: CN201711028851.7A
Authority: CN
Inventors: 王郁昕; 何宁; 李红豫
Original assignee: Beijing Union University
Current assignee: Beijing Union University
Priority date: 2017-10-29
Filing date: 2017-10-29
Publication date: 2020-07-03
Anticipated expiration: 2037-10-29
Also published as: CN107832249A

Abstract

A system and a method for realizing communication between three wires and peripheral equipment with an SPI interface belong to the field of three-wire SPI communication. The three-wire SPI communication system comprises a master control device and a plurality of slave devices. The master device is generally provided with a CPU, and the slave device is often a data acquisition device or a D/A output device. The master control equipment and the slave equipment are provided with standard SPI interfaces, and the master control equipment is connected with other slave equipment through a three-wire SPI interface control system through a clock wire SCLK, a data input wire MDI and a data output wire MDO of the SPI interfaces. The invention eliminates all chip selection circuits in the SPI, and reduces the number of communication circuits to 3, thereby greatly simplifying the physical connection between the master equipment and the slave equipment. The cost of isolation and driving between the master device and the slave device is greatly reduced due to the reduction of the number of communication lines between the master device and the slave device. The invention has better compatibility, has no special requirement on the slave equipment module, and can access the system by the chip or the module meeting the SPI interface, so that the chip or the module becomes the slave equipment of the system.

Description

System and method for three-wire realization and communication with peripheral equipment with SPI interface

Technical Field

The invention belongs to the field of three-wire SPI communication.

Background

A serial bus is often used by the main control device to exchange data with the peripheral device, and spi (serial peripheral interface) is a widely used serial interface and is supported by multiple chip manufacturers. The interface consists of a starting line, a clock line, two data lines and a plurality of selection lines. When exchanging data with a plurality of peripheral devices, the main control device firstly selects one device which the main control device wants to communicate with through the chip selection signal, then sends and receives data through the data line under the control of the clock signal on the clock line, and the main control device controls the whole communication process. The number of buses for serial communication depends on the number of system peripherals, if N peripherals adopt address decoding measure, 4+ is needed

(upper round) bus. For example, 7 buses are required to communicate with 8 peripheral devices, of which 3 are address lines, and 8 devices can be selected after decoding.

Reducing the number of buses connecting peripheral devices reduces the complexity of the system and simplifies the design of the system, which is the primary reason why serial buses are widely used. More importantly, in some applications, it is desirable to add long line drivers or isolators to the bus to enhance the remote communication capability or reliability of the system. It would clearly be of interest if the number of buses for serial communication could be further reduced.

Disclosure of Invention

Aiming at some applications which are not sensitive to the communication speed but have long-line driving or electrical appliance isolation requirements, the patent provides a method for realizing communication with a peripheral with an SPI interface by using three lines. The method can output the decodable address through the data line, and further saves the starting line through the self-recovery clock controller, so that the method can be communicated with the peripheral with the SPI interface only by three lines, namely one clock line and two data lines, and has no special requirement on the peripheral with the SPI interface, so the method has good compatibility.

The technical scheme adopted by the invention is as follows:

the three-wire SPI communication system comprises a master control device and a plurality of slave devices. The master device is generally provided with a CPU, and the slave device is often a data acquisition device or a D/A output device. The master control equipment and the slave equipment are provided with standard SPI interfaces, and the master control equipment is connected with other slave equipment through a three-wire SPI interface control system through a clock wire SCLK, a data input wire MDI and a data output wire MDO of the SPI interfaces. The system composition is shown in fig. 1.

The isolation module plays an isolation or driving role on the transmitted signals, does not change the logic properties of the signals, and can consider that the isolation module has no influence on the control logic of the SPI. The interface signals of the three-wire SPI interface control system facing the master control device are only three wires, namely a clock wire SCLK, a data input wire MDI and a data output wire MDO. The slave-oriented interface includes a slave data input line DI, a slave output line DO, a slave clock line SCLK and chip select lines CSi of several slaves (1 ≦ i ≦ N, N representing the number of slaves that can be decoded, N typically taking 8 or 16). When the communication system is formed, the clock line of the master control device is connected with the clock line of the slave device, the MDI is connected with the DO, the MDO is connected with the DI, and the CSi can be directly connected to the chip selection end of the slave device. The connection method conforms to the connection method of the standard SPI interface. The address information is output as data information, which follows the address information, i.e., the number of data bits per data transmission becomes long, in order to accommodate the address information. The validity of the chip select signal (CSi) is determined by the address length, i.e. the chip select signal is valid immediately after the address information is output. The invalidity is determined by a clock counter (divider) which expires when both address and data have been transferred and generates an output which negates the chip select signal.

Due to the adoption of the technical scheme, the invention has the following advantages:

1. the invention eliminates all chip selection circuits in the SPI, and reduces the number of communication circuits to 3, thereby greatly simplifying the physical connection between the master equipment and the slave equipment.

2. The cost of isolation and driving between the master device and the slave device is greatly reduced due to the reduction of the number of communication lines between the master device and the slave device.

3. The output of the three-wire SPI interface control module conforms to the protocol of the SPI interface, so that the system has better compatibility, has no special requirement on a slave device module, and can be accessed to the system by a chip or a module meeting the SPI interface to become slave equipment of the system.

4. The length of the address is not limited, and the address range can be set as required when the system is designed, so that the system requirements of different peripheral scales are met.

5. The control logic of the master device basically has no change, only address information needs to be added in front of the data information, if writing to the slave device, the extended data can be considered to be sent, and if reading, the address information needs to be written to the slave device first, and then the data information needs to be read from the slave device.

6. The master control device can synchronize the communication to the initial state through a synchronization control process.

Drawings

Fig. 1 is a block diagram of basic components of three-wire SPI communication system

Fig. 2 is a block diagram of the control system of three-wire SPI interface

FIG. 3 is a timing diagram of data communication

Fig. 4 timing diagram of frequency divider FD

FIG. 5 is a flow chart of data communication of the main control device

FIG. 6 Master clock synchronization flow diagram

FIG. 7 is a block diagram of a control system having multiple three-wire SPI interfaces

Detailed Description

The invention is described in detail below with reference to the figures and examples.

The three-wire SPI interface control system is composed of a frequency divider FD, a delay, an address counter, an address shift register, and a decoder, as shown in fig. 2. The data transmission of the three-wire SPI interface control system adopts a strategy that a data wire comprises address information, and the address information is transmitted first in each large data transmission period, and then the data is transmitted. The frequency divider FD is used to keep track of the large period of the entire data communication, which is called FD period. The address counter is used to record the period of address read-in, which is called address period. Its output CSE goes high to low after the address counter has expired. The communication timing sequence between the master device and the three-wire SPI control system is shown in fig. 3. At the beginning of communication, the SCLK clock signal is at high level, the chip select control signal CSE is at high level, and the FD is at low level. The transmission cycle of the address data depends on the size of the slave device, if the number of the slave devices is less than 8, 3-bit address bits are needed, if the number of the slave devices is more than 8 and less than 16, 4-bit address bits are needed, the three-wire SPI interface control system needs one-bit address bit for frequency divider synchronization, the address is 0, namely CS0 must be left for the interface control system to use, and cannot be used for selecting other slave devices. The master control equipment outputs address data at the falling edge of the SCLK, the high address bit is output first, and the low address bit is output later. The address counter is used to record the number of incoming bits of the address, outputting a low level on the rising edge CSE of SCLK when the address counter is full, e.g. 3 SCLK clocks are recorded. While the low level is reversed to turn off the address counter until the falling edge of FD turns it back on. The address shift register is in an effective state when the CSE is in a high level, and the data transmitted by the main control equipment through the MDO is shifted into the register at the falling edge of the SCLK clock until the CSE is in a low level, and then the shifting of the data is stopped. The CSE is also a control line of the address decoder, when the CSE is in a low state, the address decoder is effective, at the moment, the decoder can carry out N-to-1 decoding on the output of the address shift register, so that a certain output of the decoder is effective, and the signal is used as a standard chip selection signal of the SPI interface and is connected with a chip selection end of certain slave equipment. If a three bit address is transmitted, an 8-of-1 decoder is formed. If a four bit address is transmitted, a 16-to-1 decoder is formed. The design of the decoder is determined by the size of the addresses, which in turn is determined by the number of slave devices. The address size of the entire system cannot be changed once determined.

The frequency divider FD is used for recording the whole transmission period, the main function of the frequency divider FD is to record the number of SCLK clocks, when the clock is full, a high level with the duration of a half period of SCLK is output in the last half period of SCLK, and the signal is used as the output signal of FD after passing through a time delay. The function of the delayer is to ensure that the last period is compatible with the specification of the SPI, a small delay is carried out after the rising edge of the last period to restore the CSE to a high level, and the decoder is in a high impedance state or a high level state when the CSE is in the high state, that is, no slave device is selected. This small delay thus wins time for the read or write of the serial data for the last clock cycle, typically half the SCLK clock cycle. The timing diagram of the frequency divider FD is shown in fig. 4.

The process of the master device communicating via the three-wire SPI is described below with the aid of the flowchart in fig. 5. Firstly, the length of read-write data is set, and the general data length is between 8 bits and 16 bits and can be determined according to the precision of the slave device. The length of the read-write data of each three-wire SPI interface control system is fixed and can not be changed once being determined, and the length is determined by the length SIZE of the read-write data of the system. SCLK is then set to high level 1. Rin is a serial data input register for reading in serial data. Rout is a serial data output register for the output of serial data. The master control device adopts a mode of outputting data through an MDO terminal at the falling edge of an SCLK and reading data through an MDI terminal at the rising edge of the SCLK (the working principle of the opposite mode is similar to that, and is not described herein again), and the slave device reads data through a DI terminal (MDO) at the falling edge of the SCLK and outputs data through a DO terminal (MDI) at the rising edge of the SCLK. Initialization of Rin and Rout also includes writing output data to Rout for all locations 1 of Rin. The address of the slave device is then serially output via the MDO. The most significant bit of the chip select address is output first, a represents the address register, and i in a (i) represents the number of bits currently transferred. If the address range of the slave device is more than 8 and less than 16, i is less than or equal to 4; if the address range is less than 8, i is less than or equal to 3. I is decremented by 1 after each output of a bit address. If i is-1, the transmission of the address data can be judged to be finished. If i is greater than-1, then a cycle to cycle out the address is entered. In the period, firstly, SCLK is set to 0, then A is shifted to the left by one bit, i is subtracted by 1, then the highest bit of A is output to the MDO end, SCLK is set to 1 again, and finally, the judgment of i is returned, namely, whether the data in A are all output is judged. If not, continuing outputting the address information, and if outputting, entering a data output and data input period.

The highest bit in Rout is firstly sent to an MDO end, then whether the length of data output and input reaches SIZE or not is judged, if the length of read-write data reaches the length SIZE of the read-write data of the system, the whole data communication process is ended, otherwise, the data read-write cycle is controlled. The loop first places SCLK at 0, then Rout shifts left by 1 bit, with the highest bit of Rout output to the MDO side, ready for writing data from the device on the next falling clock edge. Next SCLK is set to 1, the current read-write data length is incremented by 1, Rin is shifted left by 1 bit and the MDI-side data is read to the lowest Rin bit. And finally, returning to the judgment of the SIZE.

The divider synchronization process is shown in fig. 6. And the MDO is always output as 0, and the master control equipment continuously reads the equipment from the MDI end. CS0 is discussed in two cases, if CS0 is selected, i.e., the address with input 0 is decoded, divider FD output is high on the falling edge of the last clock cycle, and MDI output is also high. Before the last cycle of the clock returns to high, the master reads in MDI, which if high can conclude that this is the initial state, and then returns the periodic signal to high. In the above process, other chip selection CS terminals are not selected, so that the influence on all slave devices is avoided. If CS0 is not selected, the MDI is always low. The master will keep the MDO output at 0 and continue to read in data on the falling edge of the clock until a high is read, which will conclude that this is the initial state and then restore the clock signal to high. Since MDO is always 0, it is always possible to wait until CS0 is active. A side effect of this procedure is that a 0 value may be input to a selected slave device via SDI, which may only be possible at initialization after power-up or at clock synchronization after fault recovery. The output logic of the synchronous data output monitor in fig. 2 is that the input and output are consistent when the enable terminal is active, i.e. its ENB is low; the output is low when the enable terminal is inactive, i.e., its ENB is high.

The solution of the scheme has two solutions for different slave devices with different data lengths. One approach is to introduce a control system with multiple three-wire SPI interfaces, the structure of which is shown in fig. 7. The number of clocks recorded by the frequency divider FD of each line SPI interface control system may be set to be different, e.g., T1 to 19 and T2 to 15. If the address bits of T1 and T2 are both 3 bits, then the data bit length of T1 is 16 and the data bit length of T2 is 12.

The second method is redundant transmission of serial data. Most slave devices with SPI interfaces latch the serially input data only when the chip select signal changes from active to inactive. The transmission of short data can be realized by adding some redundant bits to the high bits of serial data, for example, 12 bits of data are transmitted, and the clock for data transmission is 15 bits, and we can add 3 bits of data, for example, 3 0, before 12 bits of data to realize redundant transmission. The read data only takes the first 12 bits of data because the contents of the latch are written into the serial register when the chip select is active.

Claims

1. The three-wire SPI communication system is characterized by comprising a master control device and a plurality of slave devices; the master control equipment is provided with a CPU, and the slave equipment is data acquisition equipment or D/A output equipment; the master control equipment and the slave equipment are provided with standard SPI interfaces, and the master control equipment is connected with the slave equipment through a three-wire SPI interface control system through a clock wire SCLK, a data input wire MDI and a data output wire MDO of the SPI interfaces;

interface signals of the three-wire SPI interface control system facing the main control equipment only comprise three wires, namely a clock wire SCLK, a data input wire MDI and a data output wire MDO; the interface facing the slave device comprises a slave device data input line DI, a slave device output line DO, a slave device clock line SCLK and chip selection lines CSi of a plurality of slave devices, wherein i is more than or equal to 1 and less than or equal to N, and N represents the number of slave devices which can be decoded; the clock line of the master control device is connected with the clock line of the slave device, the MDI is connected with the DO, the MDO is connected with the DI, and the CSi is directly connected to the chip selection end of the slave device;

the three-wire SPI interface control system comprises a frequency divider FD, a delayer, an address counter, an address shift register and a decoder; the data transmission of the three-wire SPI interface control system adopts a strategy that a data wire comprises address information, and the address information is transmitted first and then the data is transmitted in each large data transmission period; the frequency divider FD is used for recording the large period of the whole data communication, and the period is called an FD period; the address counter is used for recording the period of reading in the address, and the period is called as an address period; the output CSE of the address counter is changed from high to low after the address counter is full; at the beginning of communication, SCLK clock signal is high level, chip select control signal CSE is high level, FD is low level; the transmission cycle of the address data is determined according to the scale of the slave device, if the number of the slave devices is less than 8, 3-bit address bits are needed, if the number of the slave devices is more than 8 and less than 16, 4-bit address bits are needed, the three-wire SPI interface control system needs one-bit address bit for frequency divider synchronization, the address is 0, namely CS0 must be reserved for the interface control system and cannot be used for selecting other slave devices; the master control equipment outputs address data at the falling edge of the SCLK, wherein a high address bit is output first, and a low address bit is output later; the address counter is used for recording the incoming bit number of the address, and when the address counter is full, a low level is output at the rising edge CSE of the SCLK; at the same time, the low level is reversed to turn off the address counter until the FD falls to turn on again; the address shift register is in an effective state when the CSE is in a high level, and the data transmitted by the main control equipment through the MDO is shifted into the register at the falling edge of the SCLK clock until the CSE is in a low level, and then the shifting of the data is stopped; the CSE is also a control line of the address decoder, when the CSE is in a low-time state, the address decoder is effective, at the moment, the decoder performs N-to-1 decoding on the output of the address shift register, so that a certain output of the decoder is effective, and the signal is used as a standard chip selection signal of the SPI and is connected with a chip selection end of certain slave equipment; the frequency divider FD is used for recording the whole transmission period, when the clock is full, a high level with the duration of a half period of the SCLK is output in the latter half period of the last period of the SCLK, and the signal passes through a time delay and then is used as an output signal of the FD; the delay unit makes the CSE return to high level after the rising edge of the last period, and the decoder is in high impedance state or high level state when the CSE is high, namely no slave device is selected.

2. A method of communicating using the system of claim 1, wherein: firstly, setting the length of read-write data, wherein the length is determined by the length SIZE of the read-write data of the system; SCLK is then set to high level 1; rin is a serial data input register for reading in serial data; rout is a serial data output register for the output of serial data; the master control equipment adopts a mode that data are output through an MDO end on the falling edge of an SCLK and read in through an MDI end on the rising edge of the SCLK, the slave equipment reads in data through a DI end on the falling edge of the SCLK and outputs the data through a DO end on the rising edge of the SCLK; the initialization work of Rin and Rout further comprises writing the output data into Rout at all positions 1 of Rin; the address of the slave device is serially output through the MDO; the most significant bit of the chip selection address is output firstly, A represents an address register, and i in A (i) represents the currently transmitted bit number; if the address range of the slave device is more than 8 and less than 16, i is less than or equal to 4; if the address range is less than 8, i is less than or equal to 3; subtracting 1 from i after each output of one bit address; if i is-1, judging that the transmission of the address data is finished; if i is larger than-1, entering a cycle of circularly outputting the address; in the period, firstly, SCLK is set to 0, then A is shifted to the left by one bit, i is subtracted by 1, then the highest bit of A is output to an MDO end, SCLK is set to 1 again, and finally, the judgment of i is returned, namely, whether the data in A are all output is judged; if the output is not finished, continuing to output the address information, and if the output is finished, entering a data output and data input period;

the highest bit in Rout is firstly sent to an MDO end, then whether the length of data output and input reaches SIZE or not is judged, if the length of read-write data reaches the read-write data length SIZE of the system, the whole data communication process is ended, otherwise, the data read-write cycle is controlled; circularly, firstly, SCLK is set to be 0, then Rout is shifted to the left by 1 bit, and the highest bit of Rout is output to an MDO end, so that preparation is made for writing data from the equipment at the next clock falling edge; next, SCLK is set to 1, the current read-write data length is added with 1, Rin is shifted left by 1 bit and the data at MDI end is read to the lowest Rin bit; and finally, returning to the judgment of the SIZE.

3. A method of communicating using the system of claim 1, wherein the divider synchronization process: the MDO is always output to be 0, and the master control equipment continuously reads in equipment from the MDI end; CS0 is discussed in two cases, if CS0 is selected, i.e., the address with input 0 is decoded, divider FD output is high on the falling edge of the last clock cycle, and MDI output is also high; before the last period of the clock is restored to high level, the master device reads in MDI, if the MDI is high, the master device judges that the MDI is in an initial state, and then the periodic signal is restored to high level; in the process, other chip selection CS terminals are not selected, so that all slave devices are not influenced; if CS0 is not selected, MDI is always at low level; the master device always outputs the MDO as 0, continuously reads in data on a clock falling edge until reading a high level, judges that the data is in an initial state as long as the data is read to the high level, and then restores the clock signal to the high level; since MDO is always 0, it must wait until CS0 is valid; the output logic of the synchronous data output monitor is that when the enabling end is effective, namely ENB is low level, the input and the output are consistent; the output is low when the enable terminal is inactive, i.e., its ENB is high.