CN107832249A - The system and method that three lines are realized and communicated with SPI interface peripheral hardware - Google Patents
The system and method that three lines are realized and communicated with SPI interface peripheral hardware Download PDFInfo
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- CN107832249A CN107832249A CN201711028851.7A CN201711028851A CN107832249A CN 107832249 A CN107832249 A CN 107832249A CN 201711028851 A CN201711028851 A CN 201711028851A CN 107832249 A CN107832249 A CN 107832249A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
Abstract
Three lines are realized and belong to three line SPI communication fields with the system and method that SPI interface peripheral hardware is communicated.Three line SPI communication systems include a main control device and multiple slave units.Main control device typically carries CPU, and slave unit is often data acquisition equipment or D/A output equipments.Main control device and slave unit all carry the SPI interface of standard, and main control device is connected by the clock line SCLK, Data In-Line MDI and DOL Data Output Line MDO of SPI interface through three line SPI interface control systems with other slave units.Invention removes all chip select line roads in SPI, communication line is reduced to 3, so that physical connection is greatly simplified between master-slave equipment.The isolation between master-slave equipment is caused to be greatly lowered with the cost driven due to the reduction of the communication line quantity between principal and subordinate.The present invention has preferable compatibility, does not have particular/special requirement to slave unit module, and the chip or module for meeting SPI interface can access the system, become the slave unit of system.
Description
Technical field
The invention belongs to three line SPI communication fields.
Background technology
Main control device is exchanging data with ancillary equipment often frequently with universal serial bus, SPI (Serial Peripheral
Interface it is) a kind of serial line interface being widely adopted, obtains the support of multiple chip producers.The interface is by a startup
Line, a clock line, two data lines and some chip select lines composition.Main control device is first when exchanging data with multiple ancillary equipment
The control of one of those equipment, the then clock signal on clock line wanting what to communicate can be selected by chip selection signal
Send by data wire down and receive data, main control device can control whole communication process.The bus number of serial communication depends on
In the number of system peripheral, if N platforms ancillary equipment needs 4+ if using address decoding measure(above take
It is whole) bar bus.Such as 7 buses are just needed with 8 ancillary equipment communications, wherein 3 are address wires, 8 can be selected after decoding
Platform equipment.
The quantity that reduction is connected bus with ancillary equipment can reduce system complexity, simplify the design of system, this is also
Universal serial bus obtains wide variety of first cause.What is more important needs to increase elongated line drive for bus in some application scenarios
Dynamic device or isolator are with the remote communications capability or reliability of strengthening system.If it can further reduce the total of serial communication
Line number amount undoubtedly will be significant.
The content of the invention
Less sensitive to communication speed for some but have the application of long distance driver or electrical equipment insulation request, this patent proposes
A kind of method realized using three line cans and communicated with SPI interface peripheral hardware.This method can pass through data
The address that line output can be decoded, further eliminates startup line, so only needing a clock by self- recoverage clock controller
This three line cans of line, two data lines and the peripheral hardware with SPI interface are communicated, and to outer with SPI interface
If without particular/special requirement, there is compatibility well in this way.
The technical solution used in the present invention is：
Three line SPI communication systems include a main control device and multiple slave units.Main control device typically carries CPU, from setting
Standby often data acquisition equipment or D/A output equipments.Main control device and slave unit all carry the SPI interface of standard, and master control is set
Standby clock line SCLK, Data In-Line MDI and DOL Data Output Line MDO by SPI interface through three line SPI interface control systems with
Other slave units are connected.System composition is as shown in Figure 1.
Isolation module plays isolation or driving effect to transmitted number, does not change the logic property of signal, it is believed that
SPI control logic is not influenceed.Three line SPI interface control systems only have clock line towards the interface signal of main control device
This three lines of SCLK, Data In-Line MDI and DOL Data Output Line MDO.Interface towards slave unit includes slave unit data input
Line DI, slave unit output line DO, (1≤i≤N, N are represented can by the chip select line CSi of slave unit clock line SCLK and some slave units
It is decoded the quantity of slave unit, General N takes 8 or 16).The clock line of main control device and the clock of slave unit when forming communication system
Line is connected, and MDI is connected with DO, and MDO is connected with DI, and CSi can be attached directly to the chip select terminal of slave unit.Above-mentioned connection method meets
The connection method of standard SPI interface.Address information is taken as data message to export, data out message follow closely address information it
Afterwards, i.e., the data bits of each data transfer is elongated, to accommodate address information.Chip selection signal (CSi) validity is grown by address
Degree determines that is, chip selection signal is effective immediately after the completion of address information output.Its ineffectivity is by a clock counter (frequency divider)
Determine, when address and data all end of transmission hour counter meters are expired and produce output, the output makes chip selection signal invalid.
For the present invention due to taking above technical scheme, it has advantages below：
1st, invention removes all chip select line roads, communication line in SPI to be reduced to 3, so that between master-slave equipment
Physical connection is greatly simplified.
2nd, because the reduction of the communication line quantity between principal and subordinate causes the cost of the isolation and driving between master-slave equipment
It is greatly lowered.
3rd, the output of three line SPI interface control modules meets the agreement of SPI interface, therefore has preferable compatibility, to from
EM equipment module does not have particular/special requirement, and the chip or module for meeting SPI interface can access the system, become system from
Equipment.
4th, the length of address is unrestricted, and address realm can be arranged as required in design system, so as to meet not
System with peripheral hardware scale needs.
5th, the control logic of main control device does not change substantially, only address information need to be added to before data message, such as
Fruit is write to slave unit, may be considered the data for sending and lengthening, if reading then to need first to slave unit write address information,
Then data message is read from slave unit.
6th, main control device can make communication be synchronized to original state by Synchronization Control process.
Brief description of the drawings
The basic comprising modules figure of the line SPI communication systems of Fig. 1 tri-
The comprising modules figure of the line SPI interface control systems of Fig. 2 tri-
The timing diagram of Fig. 3 data communications
Fig. 4 frequency dividers FD timing diagram
Fig. 5 main control device data communication flow charts
Fig. 6 main control device clock synchronization flow charts
Fig. 7 has the structure chart of multiple three lines SPI interface control systems
Embodiment
The present invention is described in detail with reference to the accompanying drawings and examples.
The compositions of three line SPI interface control systems as shown in Fig. 2 respectively by frequency divider FD, delayer, address counter,
Address shift register and decoder composition.The data transfer of three line SPI interface control systems includes address using data wire
The strategy of information, first information by reference, then passes data again in the large period of each data transfer.Frequency divider FD is used to record
The large period of whole data communication, the cycle are referred to as the FD cycles.Address counter is used for the cycle that recording address is read in, the cycle
Referred to as address cycle.CSE is exported by high step-down in address counter meter completely rear its.Main equipment and three line SPI interface control systems
Communication succession it is as shown in Figure 3.SCLK clock signals are high level when communicating initial, and it is high level that piece, which selects control signal CSE, FD
For low level.Depending on the transmission cycle of address date is according to the scale of slave unit, if slave unit is less than 8, it is necessary to 3 bit address
Position, if greater than 8 and less than 16, it is necessary to which 4 bit address positions, three line SPI interface control systems need a bit address position to be used for
Frequency divider is synchronous, and the address is 0, i.e. CS0 must leave interface control system use for, it is impossible to be used in select other slave units.It is main
Trailing edge output address data of the equipment in SCLK is controlled, upper address bits first export, and low address exports behind position.Address counter is used for
The incoming digit of recording address, when address counter counts are full, such as during 3 SCLK clocks of record, in SCLK rising edge CSE
Export low level.The low level in turn closes address counter simultaneously, until FD trailing edge reopens it.Address
Shift register is effective status when CSE is high level, transmits main control device by MDO in the trailing edge of SCLK clocks
Data move into register can just stop the immigration of data after CSE is low level.CSE is also the control line of address decoder,
When CSE is low, address decoder is effective, and now the output of address shift register can be carried out N and select 1 decoding by decoder, be made
Decoder some output it is effective, the signal using as the standard chip selection signal of SPI interface and with some slave unit chip select terminal
It is connected.If transmitting three bit address, 8 can be formed and select 1 decoder.If transmitting four bit address, 16 decodings for selecting 1 can be formed
Device.So the design of decoder is determined by address scale, and address scale is determined by the quantity of slave unit.Entirely
The address scale of system is once it is determined that cannot change.
Frequency divider FD is used for recording whole transmission cycle, and its major function is to record the number of SCLK clocks, when meter is full
When the second half of the cycle in last cycle of SCLK exports one, the high level of a length of SCLK half periods, the signal prolong through one
When device after output signal as FD.The effect of delayer is in order to ensure that last cycle is also compatible with SPI regulation, most
There is a bit of delay just CSE can be made to revert to high level after the rising edge in the latter cycle, decoder is high resistant shape when CSE is high
State or high level state, that is, do not have slave unit to be selected.Therefore this bit of delay is last clock cycle serial data
Read or write and won the time, generally delay duration is half of SCLK clock cycle.Frequency divider FD timing diagram such as Fig. 4 institutes
Show.
Below the process that main control device communicated by three line SPI is introduced by flow chart 5.It is that read-write number is set first
According to length, in general data length is between 8 to 16, can be depending on the precision of slave unit.Each three lines SPI interface
The read-write data length of control system is fixed, once it is determined that can not change, length by system read-write data length SIZE
Determine.SCLK is then set as high level 1.Rin is serial date transfer register, the reading for serial data.Rout
It is serial data output register, the output for serial data.Main control device uses the trailing edge in SCLK defeated by MDO ends
Go out data, SCLK rising edge by MDI ends read in data pattern (operation principle of reverse mode is similar therewith, here
Repeat no more), slave unit then reads in data in SCLK trailing edge by DI ends (MDO), passes through DO in SCLK rising edge
Hold (MDI) output data.Rin and Rout initial work is also included Rin all positions 1, and output data is write
Rout.Next the address of slave unit is subjected to Serial output through MDO.What is exported first is the highest order of chip select address, and A is represented
Address register, the i in A (i) represent currently transmitted digit.If slave unit address realm be more than 8 be less than 16 if i≤
4；I≤3 if address realm is less than 8.I subtracts 1 after often exporting a bit address.It may determine that address date passes if i is -1
It is totally lost complete.If i is more than -1, enter the cycle of circulation OPADD.The cycle first sets to 0 SCLK, and A then is moved to left into one
A highest order is output to MDO ends by position, i after subtracting 1, and SCLK is set to 1 again, finally returns to the judgement to i, that is, judges whether in A
Data all export and finish.Address information is continued to output if not exported, enters data output if output is over
With the data input cycle.
Highest order is first sent to MDO ends in Rout, then judges whether data output and the length of input have arrived at
SIZE, terminate whole process of data communication if the length of read-write data reaches the read-write data length SIZE of system, it is no
Then enter the circulation of control data read-write.Circulation first sets to 0 SCLK, and then Rout moves to left 1, and Rout highest orders are output to
MDO ends, this is to write data in next clock falling edge slave unit to be ready.Following SCLK is set to 1, current read-write
Data length adds 1, Rin to move to left 1 and reads the data at MDI ends to Rin lowest orders.Finally return to the judgement to SIZE.
Frequency divider synchronizing process is as shown in Figure 6.MDO exports as 0 all the time, and main control device is constantly from MDI ends reading device.
CS0 is discussed in two kinds of situation, if CS0 is selected, i.e. input is decoded for 0 address, under last cycle of clock
Drop is high level along frequency divider FD outputs, and MDI outputs are also high level.Reverted in last cycle of clock high level it
Before, main equipment reads in MDI, then can be concluded that at this moment be original state if height, and it is high level then to recover periodic signal.On
Process other chip selection cs ends are stated all without selected, so not influenceed on all slave units.If CS0 is not selected, MDI begins
It is in low level eventually.Main equipment will make MDO outputs be 0 always, and constantly read in data until reading high electricity in clock falling edge
It is flat, can conclude that at this moment be original state as long as reading high level, be then high level by recovering clock signals.Because MDO begins
It is 0 eventually, so necessarily can be at the time of CS0 is effective.The side effect of the process is possible selected from setting to some
It is standby to be worth by SDI inputs 0, it is possible to out when such case is only possible to initialize after the power-up or after fault recovery during clock synchronization
It is existing.The output logic of synchrodata output monitor in Fig. 2 is when Enable Pin is effective, i.e. its ENB is inputted when being low level
Output is consistent；When Enable Pin is invalid, i.e. output is low level when its ENB is high level.
The solution method that this programme has different data lengths to different slave units has two.Method one is that introducing is multiple
Three line SPI interface control systems, its structure chart are as shown in Figure 7.What the frequency divider FD of each line SPI interface control system was recorded
Clock number can be set to different, and 15 are set to as T1 is set to 19, T2.If T1 and T2 address bit is all 3, then T1 data
The data bit length that bit length is 16, T2 is 12.
Method two is the redundant transmission of serial data.Most of slave unit with SPI interface is in chip selection signal from effective
Just the data of serial input are latched when being changed into invalid.Some redundant digits can be added in a high position for serial data to realize short number
According to transmission, such as transmission 12 data, and the clock of data transfer be 15, we can add before 12 data
3 data, such as 30, it is possible to realize redundant transmission.Read in data and only take preceding 12 data, because effective in piece choosing
When latch in content just write in serial register.
Claims (5)
1. three line SPI communication systems, it is characterised in that including a main control device and multiple slave units；Main control device carries
CPU, slave unit are data acquisition equipment or D/A output equipments；Main control device and slave unit all carry the SPI interface of standard, main
Control equipment and controlled by the clock line SCLK, Data In-Line MDI and DOL Data Output Line MDO of SPI interface through three line SPI interfaces and be
System is connected with slave unit；
Three line SPI interface control systems only have clock line SCLK, Data In-Line MDI sums towards the interface signal of main control device
According to this three lines of output line MDO；Towards slave unit interface include slave unit Data In-Line DI, slave unit output line DO, from
Equipment clock line SCLK and chip select line CSi, 1≤i≤N, N of some slave units represent the quantity that can be decoded slave unit；It is main
The clock line of control equipment is connected with the clock line of slave unit, and MDI is connected with DO, and MDO is connected with DI, and CSi is attached directly to slave unit
Chip select terminal.
2. system according to claim 1, it is characterised in that three line SPI interface control systems include frequency divider FD, delay
Device, address counter, address shift register and decoder composition；The data transfer of three line SPI interface control systems uses number
Include the strategy of address information according to line, first information by reference, then passes data again in the large period of each data transfer；Point
Frequency device FD is used for the large period for recording whole data communication, and the cycle is referred to as the FD cycles；Address counter is read for recording address
The cycle entered, the cycle are referred to as address cycle；CSE is exported by high step-down in address counter meter completely rear its；When communicating initial
SCLK clock signals are high level, and it is high level that piece, which selects control signal CSE, and FD is low level；The transmission cycle of address date according to
Depending on the scale of slave unit, if slave unit is less than 8, it is necessary to 3 bit address positions, if greater than 8 and less than 16, it is necessary to
4 bit address positions, three line SPI interface control systems need a bit address position to be used for frequency divider synchronization, and the address is 0, i.e. CS0 is necessary
Leave interface control system use for, it is impossible to be used in select other slave units；Trailing edge OPADD number of the main control device in SCLK
According to upper address bits first export, and low address exports behind position；Address counter is used for the incoming digit of recording address, works as Address count
When device meter is full, low level is exported in SCLK rising edge CSE；The low level in turn closes address counter simultaneously, until
FD trailing edge reopens it；Address shift register is effective status when CSE is high level, under SCLK clocks
The data that main control device is transmitted by MDO are moved into register by drop edge can just stop the immigration of data after CSE is low level；
CSE is also the control line of address decoder, and when CSE is low, address decoder is effective, and now decoder deposits address shift
The output of device carries out N and selects 1 decoding so that some output of decoder is effective, and the signal selects letter using as the standard film of SPI interface
Number and be connected with some slave unit chip select terminal；Frequency divider FD is used for recording whole transmission cycle, when meter is full SCLK last
The high level of a length of SCLK half periods, the signal are used as FD after a delayer when second half of the cycle in individual cycle exports one
Output signal；Delayer has one section of delay just CSE can be made to revert to high level, CSE after the rising edge in last cycle
For it is high when decoder be high-impedance state or high level state, that is, do not have slave unit to be selected.
3. the method that the system of application such as claim 1 or 2 is communicated, it is characterised in that：It is that read-write data are set first
Length, length are determined by the read-write data length SIZE of system；SCLK is then set as high level 1；Rin is that serial data is defeated
Enter register, the reading for serial data；Rout is serial data output register, the output for serial data；Master control
Equipment uses the trailing edge in SCLK by MDO ends output data, in the mould that SCLK rising edge passes through MDI ends reading data
Formula, slave unit then read in data by DI ends in SCLK trailing edge, pass through DO ends output data in SCLK rising edge；
Rin and Rout initial work is also included Rin all positions 1, and output data is write into Rout；Next by slave unit
Address through MDO carry out Serial output；What is exported first is the highest order of chip select address, and A represents address register, in A (i)
I represents currently transmitted digit；I≤4 if the address realm of slave unit is more than 8 less than 16；If address realm is less than 8
Then i≤3；I subtracts 1 after often exporting a bit address；Judge address date end of transmission if i is -1；If i is more than -1, enter
Enter to circulate the cycle of OPADD；The cycle first sets to 0 SCLK, A then is moved to left into one, i is defeated by A highest order after subtracting 1
Go out to MDO ends, SCLK and be set to 1 again, finally return to the judgement to i, that is, judge whether all to export the data in A and finish；If
Do not export, continued to output address information, entered data output and data input cycle if output is over；
Highest order is first sent to MDO ends in Rout, then judges whether data output and the length of input have arrived at SIZE,
Terminate whole process of data communication if the length of read-write data reaches the read-write data length SIZE of system, otherwise enter
The circulation of control data read-write；Circulation first sets to 0 SCLK, and then Rout moves to left 1, and Rout highest orders are output to MDO ends, this
It is ready to write data in next clock falling edge slave unit；Following SCLK is set to 1, current read-write data length
Add 1, Rin to move to left 1 and read the data at MDI ends to Rin lowest orders；Finally return to the judgement to SIZE.
4. the method that the system of application such as claim 1 or 2 is communicated, it is characterised in that frequency divider synchronizing process：MDO begins
Output is 0 eventually, and main control device is constantly from MDI ends reading device；CS0 is discussed in two kinds of situation, if CS0 is selected, that is, is inputted
It is decoded for 0 address, is high level in the trailing edge frequency divider FD outputs in last cycle of clock, MDI outputs are also height
Level；Before last cycle of clock reverts to high level, main equipment reads in MDI, then concludes at this moment be first if height
Beginning state, it is high level then to recover periodic signal；Said process other chip selection cs ends all without selected, so to it is all from
Equipment does not influence；If CS0 is not selected, MDI is in low level all the time；Main equipment will make MDO outputs be 0 always, not
Break and read in data until reading high level in clock falling edge, conclude at this moment be original state as long as reading high level, then
It is high level by recovering clock signals；Because MDO is always 0, so necessarily can be at the time of CS0 be effective；Same step number
Output logic according to output monitor is when Enable Pin is effective, i.e. input and output are consistent when its ENB is low level；Work as Enable Pin
When invalid, i.e. output is low level when its ENB is high level.
5. the method that the system of application such as claim 1 or 2 is communicated, it is characterised in that have not to different slave units
The solution method of same data length has two；
Method one is to introduce multiple three lines SPI interface control systems, and the frequency divider FD of each line SPI interface control system is recorded
Clock number be set to different；
Method two is the redundant transmission of serial data, i.e., adds some redundant digits in a high position for serial data to realize short data
Transmission.
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| CN201711028851.7A CN107832249B (en) | 2017-10-29 | 2017-10-29 | System and method for three-wire realization and communication with peripheral equipment with SPI interface |
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| US11609877B1 (en) * | 2021-09-24 | 2023-03-21 | Qualcomm Incorporated | Systems and methods for chip operation using serial peripheral interface (SPI) without a chip select pin |
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| CN107832249B (en) | 2020-07-03 |
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