CN105224485B - A kind of method of reseptance and device of pervasive serial data - Google Patents
A kind of method of reseptance and device of pervasive serial data Download PDFInfo
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Abstract
Method and device provided by the invention, the serial data of the reception any physical layer protocol that differentiation is not added that can be pervasive, including synchronous serial data and asynchronous serial data, the serial data signal limited range enlargement for only needing to receive and delay, not complicated analog circuit, circuit structure is simple and reliable and is easily achieved, and the maximum clock frequency of flip-flop circuit is exactly the maximum data transmission rate, low cost, high-performance, universality allow to widely be used to high speed transmission data.
Description
Technical field
The present invention relates generally to the method for reseptance and device of serial data (0000), such as synchronous serial data (0001) is connect
Receiving method and device, asynchronous serial data (0002) method of reseptance and device etc., it is memory interface including computer system, outer
The method and device of the data receiver of portion's bus interface, external apparatus interface, wired network interface, fiber optic network interface etc..Tool
Say to body, the present invention relates to a kind of serial data of high speed (0000) received method and devices, it is based on this method and device,
The either synchronously or asynchronously serial data of low cost, high-performance, single channel or multi-channel, single-ended drive or differential driving etc. may be implemented
The interface arrangement of communication, pervasive meets the needs of high-speed data transfer.
Background technique
Serial data communication is one of the basic means for reducing data transmission cost, and the serial data communication of early stage is with low speed
Asynchronous serial data (0002) communication based on, tranmitting data register and receive clock difference on the frequency influence it is smaller, for improve data
Transmission rate, while synchronous serial data (0001) communication for transmitting clock and data is used, and is increased cost and is also difficult to completely
The data transfer demands of sufficient higher rate, clock insertion and recovery technology make synchronous serial communication no longer need to transmit clock,
Keep the message transmission rate of serial data communication higher, but needs persistently to transmit data and clock recovery circuitry is kept to be in work shape
State, more bit moduli converters using high sampling rate are also current one of the method for receiving serial data.
The present invention provides the method for reseptance and device of a kind of serial data (0000), and synchronous serial data both may be implemented
(0001) it receives, the asynchronous serial number for communicating same high message transmission rate with synchronous serial data (0001) also may be implemented
It is communicated according to (0002).
Detailed description of the invention
The attached drawing of description of the invention is simply introduced first below, then in conjunction with these attached drawings to the present invention
Each implementation example be introduced, illustrate principles and features of the present invention.
In the following figures:
Fig. 1 is preferred embodiment measured signal (0010) SI and postpones signal (0070) SD that the method according to the invention is realized
Frequency divider (0110) circuit and timing schematic diagram；
Fig. 2 be the preferred embodiment trigger (0200) realized of the method according to the invention to measured signal (0010) SI and
Synchronized sampling (0220) circuit of postpones signal (0070) SD and the schematic diagram of timing；
Fig. 3 is the defeated of the 3 bit SI PO shift register (0210) of preferred embodiment that the method according to the invention is realized
The time diagram of es1x (esMxP, es1xN) out；
Fig. 4 be the method according to the invention realize preferred embodiment synchronized sampling (0220) output es1x (es1xP,
Es1xN) the schematic diagram of the differentiation circuit (0240) of relative timing (0230).
Fig. 5 is a kind of signal of general central processing unit (CPU) of preferred embodiment that the method according to the invention is realized
Figure.
Fig. 6 is a kind of showing for asynchronous serial data interface memory chip of preferred embodiment that the method according to the invention is realized
It is intended to.
Fig. 7 is a kind of storage such as preferred embodiment DRAM/SDRAM or SRAM or FLASH that the method according to the invention is realized
The schematic diagram of device and module controller.
Fig. 8 is connecing for computer peripheral of the preferred embodiment based on UART physical layer that the method according to the invention is realized
The schematic diagram of mouth controller.
Fig. 9 is that the preferred embodiment that the method according to the invention is realized is relayed using the data transmission of USRT or UART physical layer
The schematic diagram of device.
Figure 10 is system domain of the preferred embodiment based on USRT or UART physical layer protocol that the method according to the invention is realized
The schematic diagram of the network switch.
Figure 11 is computer of the preferred embodiment based on USRT or UART physical layer protocol that the method according to the invention is realized
The schematic diagram of the network switch and/or router.
Figure 12 is communication network of the preferred embodiment based on USRT or UART physical layer protocol that the method according to the invention is realized
The schematic diagram of network interchanger and/or router.
Specific embodiment
Method and device of the invention is illustrated first below, then to the preferred reality of application the method for the present invention and device
Example is illustrated.
In the following description, arranging serial data (0000) signal received is measured signal (0010), with SI
(SIP, SIN) represents measured signal.
In the following description:
1, signal overturning (0020, transition) is a digital signal from low level (L) to high level (H) or from height
Level (H) arrive low level (L) quick variation, from low level (L) to the signal of high level (H) overturning be rise overturn (0026,
Rise transition), it is decline overturning (0028, fall from high level (H) to the overturning of the signal of low level (L)
transition)；
2, signal width (0030) refer to a digital signal be in low level (L) or in high level (H) it is lasting when
Between；
3, the signal period (0040) refer to a digital signal it is adjacent twice rise overturning (0026) or it is adjacent twice under
Time interval between drop overturning (0028)；
4, the signal referred in the present invention may each be single-ended signal or both-end differential signal, in whole supporting papers
It is not distinguish；
5, the title for indicating a specific meanings with boldface type (label) in the starting of each paragraph, then in same paragraph
In the titles of the specific meanings is only indicated with boldface type.
One, the method for reseptance and device of pervasive serial data
This section illustrates the method for reseptance and device of pervasive serial data (0000) of the invention.
The method and device of invention described below is suitable for the serial data (0000) that arbitrary form is sent, therefore not
The sending method and device of the serial data that it is related to are repeated again.
Tranmitting data register period (0050) is indicated with TXT, is indicated to receive clock cycle (0060) with RXT, receiving clock is four
Clock AK (AKP, AKN), BK (BKP, BKN), CK (CKP, CKN), DK (DKP, DKN), their period are all RXT, AK and
BK, BK and CK, CK and DK, DK and AK the delay time difference be all that RXT/4, TXT and RXT are approximately equal, TXT can dynamic change, TXT
RXT must also change therewith when variation.
Measured signal (0010) is also possible to photoelectric conversion and processing either directly receive and treated electric signal
Electric signal afterwards, by measured signal be processed into serial data signal SI (SIP, SIN) and its postpones signal (0070) SD (SDP,
SDN), SD has the delay of about RXT/8 relative to SI, ring divider (0110) difference constituted with latch (0100, latch)
SI and SD is divided, must guarantee that the frequency dividing output (0120) of SI and SD has and stablize the constant delay time difference (0130) about RXT/8, then
The 3 bit SI PO shift registers (0210, shift- constituted respectively with trigger (0200, flip-flop)
Register sampling (0220)) is synchronized to the frequency dividing output of SI and SD, respectively with four phase clocks to each of SI and SD points
Frequency output synchronizes sampling, and the selection of frequency division coefficient (0140) must guarantee that four phase clocks can be exported with synchronized sampling to frequency dividing
Each signal overturn (0020), frequency division coefficient is that 2 can meet the requirements under normal circumstances, but the serious Shi Zexu of signal distortion
Wanting frequency division coefficient is 4, and biggish frequency division coefficient has biggish cost of implementation and realizes difficulty, and introducing SD signal is in order to using four
Phase clock is synchronized sampling and obtains the equivalent result for being synchronized sampling using eight phase clocks.
Fig. 1 be realized by four latch (0100) to SI and SD carry out except 2 frequency dividings frequency divider (0110) circuit and
The schematic diagram of timing, the circuit carry out 2 frequency dividings to SI and SD respectively, at the same guarantee the output of two frequency dividers have stablize it is constant
Be delayed the time difference (0130) RXT/8, the signal RI (RIP, RIN) of the rising overturning (0026) of corresponding measured signal (0010), corresponding
The signal FI (FIP, FIN) of the decline overturning (0028) of measured signal, the signal of the rising overturning of corresponding postpones signal (0070)
RD (RDP, RDN), the signal FD (FDP, FDN) of the decline overturning of corresponding postpones signal, is concise description, measured signal SI is drawn
At with equal signal width (0030) and signal period (0040), the actually signal width of measured signal SI and signal week
The case where phase is often unequal and random variation, postpones signal SD is identical.
Fig. 2 is the circuit for synchronizing sampling (0220) to SI and SD with trigger (0200, flip-flop) of the invention
And time diagram, xK (xKP, xKN) indicate one of four phase clocks such as AK, BK, CK, DK, x A, B, C, D respectively indicate progress
The clock of sampling is AK, BK, CK, DK, and es (esP, esN) is one of signals such as RI, FI, RD, FD, and e R, F respectively indicate input
Signal is Rs, Fs etc., and it is eI, eD etc. that s I, D, which respectively indicate input signal, and trigger (0200/0:2) constitutes 3 bits and seals in simultaneously
Shift register (0210) out, parallel output signal are esMx (esMxP, esMxN) respectively, and M 0,1,2 respectively indicates displacement
3 outputs of register.
Fig. 3 is the timing signal of the output es1x (esMxP, es1xN) of 3 bit SI PO shift registers (0210)
Figure, the output es0x (es0xP, es0xN) of shift register is unstable, the output es2x (es2xP, es2xN) of shift register
It is respectively relative to es1x (es1xP, es1xN) and postpones 1 reception clock cycle RXT, be used to latch output data, shift LD
The digit of device increases by 1 or 2 synchronized sampling that can be more reliable.
Fig. 4 is sentencing for output es1x (es1xP, es1xN) relative timing (0230) of synchronized sampling (0220) of the invention
The schematic diagram of other circuit (0240), es1A and es1C are mutually sampled in rising edge and failing edge respectively, and es1B and es1D mutually divide
It is not sampled in rising edge and failing edge, table 1 is mutual sample states table, and wherein L/H and H/L is respectively indicating esUx and esDx just
The level of Xiang Duan/reverse side output, esUA and esUC, esUB and esUD, esDA and esDC, esDB and esDD etc. is always different,
0, other states except 1,2,3 states are error conditions.Also es2x (es2xP, es2xN) progress relative timing may be selected to sentence
Not.
The mutual sample states table of table 1, es1x (es1xP, es1xN) signal
It is equivalent to the synchronized sampling (0220) of eD signal since eD signal is relative to corresponding eI signal delay about RXT/8
In about RXT/8 in advance to the synchronized sampling of eI signal, thus RIUx and RDUx, FIUx and FDUx, RIDx and RDDx, FIDx and
FDDx etc. respectively constitute to RI rising edge, FI rising edge, RI failing edge, FI failing edge equivalent eight phase clocks synchronized sampling, use
A, B, C, D indicate RIUx, FIUx, RIDx, FIDx four phase clock relative timings (0230), with a, b, c, d indicate RDUx,
The four phase clock relative timings of FDUx, RDDx, FDDx, then the variation of eight phase clock relative timings be aAbBcCdD, AbBcCdDa,
BBcCdDaA, BcCdDaAb, cCdDaAbB, CdDaAbBc, dDaAbBcC, DaAbBcCd etc., table 2 give the present invention according to eight
Phase clock relative timing selects to stablize the list of sampling clock, since the delay time difference (0130) is an approximation and unstable,
Person in an intermediate position is as sampling clock is stablized using in A, B, C, D in list, if SD signal is ignored, is based on eIUx/
The time-sequencing of eIDx selects to stablize sampling clock, and one of two phase clock in an intermediate position can be randomly selected, can also be with
Increase settling time (set time) St and retention time (hold time) Ht alternatively condition of shift register, St >=
Ht then selects the position of two phase clock in the latter, and St < Ht then selects the position of two phase clock at the former.
Table 2 selects to stablize sampling clock list based on eight phase clock relative timings
Four free counters are set, four phase clocks are counted respectively, respectively with the rising edge of eI1x/eI2x signal under
Drop respectively indicates the rising edge of eI1x/eI2x signal under along the counting for sampling corresponding free counter, with eNUx and eNDx
Drop can also use independent counter, the bit number of counter, which must guarantee to count to overflow, not to be influenced to count along the counting obtained
As a result, obtaining the clock count between adjacent eI1x/eI2x signal overturning respectively, every phase clock is at each eI (eIP, eIN)
There are 4 clock counts (0260) in signal period (0250), in terms of 4 that FNDx, RNUx, FNUx, RNDx are each signal period
Several sequences, the serial number of signal period is indicated with k, and table 3 gives defeated based on sampling clock selection bit count (0270) is stablized
List out, each signal period export 4 bit counts, are low level, the height of the serial data (0000) received respectively
Level, low level, high level lasting bit number, bit count is exactly the string that method and device of the invention is received and exported
Row data (0000) are based on serial data communication protocol for system and do subsequent processing.
Es2x (es2xP, es2xN) is used to the synchronous relative timing (0230) and clock meter for latching (0280) four phase clock
Number (0260), esUT=es2A | es2B | es2C | es2D is that rising edge synch latches, and esUx is synchronized to lock in the rising edge of esUT
Output is deposited, eNUx is synchronized to latch output in the rising edge of eIUT, and esDT=es2A&es2B&es2C&es2D is that failing edge is synchronous
It latches, esDx is synchronized to latch output in the failing edge of esDT, and eNDx is synchronized to latch output in the failing edge of eIDT.
If be synchronized latch esUx and esDx in occur be not one of four states in table 1 abnormal conditions, can
It can be that SI and SD signal distortion is serious, improving input signal can make abnormal conditions disappear, it is also possible to differentiate circuit (0240)
It breaks down, improving input signal can not make abnormal conditions disappear.
Above-mentioned postpones signal (0070) is introduced for the system work work more reliable in maximum operating frequency,
When system work is in lower frequency, the importance of postpones signal is reduced and can be even ignored.
Table 3, based on stablize sampling clock selection bit count output list
Based on above description, the method for reseptance of pervasive serial data (0000) of the invention is had the following characteristics that
1, physical layer connection, including synchronous serial data communication and asynchronous string are provided for arbitrary serial data communication protocol
Row data communication, multiple channels can be combined into multichannel connection；
2, four phase clock AK, BK, CK, DK that the period is RXT are provided, when AK, BK, CK, DK successively have the delay of RXT/4
Difference, RXT is approximately equal with serial data tranmitting data register cycle T XT, TXT can dynamic change, TXT change when RXT must also become therewith
Change；
3, single-ended or difference measured signal is also possible to photoelectric conversion either directly receive and treated electric signal
And treated electric signal, measured signal is processed into serial data signal SI and its postpones signal SD, SD is identical as SI waveform
But postpone about RXT/8, the effect of SD is the work for keeping system relatively reliable near the minimum RXT value that can work, in biggish RXT
It can be ignored when working under value；
4, it is respectively obtained 1 or 2 corresponding SI and SD respectively by the frequency dividing of SI and SD signal 2 or 4 frequency dividings with latch and risen
The signals such as the signal FI and FD of the signal RI and RD of overturning, 1 or 2 corresponding SI and SD decline overturning, RI and RD, FI and FD
Overturning must keep having about RXT/8 delay as SI and SD, and the effect of frequency dividing is to ensure that AK, BK, CK, DK etc. can be collected
The overturning each time of the signals such as RI, RD, FI, FD；
5, it the signals such as RI, RD, FI, FD is carried out with four phase clocks respectively with SI PO shift register synchronizes to adopt respectively
Sample, choose the 2nd or 3 or 4 RIx, RDx of the parallel output of four phase clock sample shift registers of the same signal, FIx,
FDx carries out time-sequencing respectively, and x is that one of A, B, C, D indicate that corresponding respectively to synchronizing for one of AK, BK, CK, DK clock adopts
Sample is selected to stablize sampling clock based on time-sequencing, indicates the time-sequencing to RI, FI signal synchronized sampling with A, B, C, D, used
A, b, c, d indicate to be equivalent in advance about the synchronized sampling of RD, FD signal the time-sequencing of RD, FD signal synchronized sampling
The RXT/8 time to the synchronized sampling of RI, FI signal, that is, is equivalent to and carries out eight phase clock synchronized samplings to RI, FI signal, when eight phases
The time-sequencing of clock synchronized sampling have aAbBcCdD, AbBcCdDa, bBcCdDaA, BcCdDaAb, cCdDaAbB, CdDaAbBc,
Eight kinds of dDaAbBcC, DaAbBcCd etc. sequences, corresponding stable sampling clock is BK, CK, CK, DK, DK, AK, AK, BK etc., SD
When signal is ignored, the time-sequencing of four phase clock synchronized samplings has four kinds of ABCD, BCDA, CDAB, DABC etc. sequences, Ke Yisui
Machine selects one of two phase clock in an intermediate position as stablizing sampling clock, i.e. BK/CK, CK/DK, DK/AK, AK/BK etc.,
The settling time of shift register can also be increased and hold time as alternative condition, when settling time is greater than or equal to holding
Between when, respectively correspond selection CK, DK, AK, BK, settling time be less than the retention time when, respectively correspond selection BK, CK, DK, AK,
The overturning of each RI, FI signal has a corresponding stable sampling clock；
6, respectively obtain RIx overturning followed by FIx overturning between in-phase clock count value RNx, FIx overturning with
The in-phase clock count value FNx between RIx overturning followed by is based respectively on RI overturning and the corresponding stable sampling of FI overturning
Clock xK, select respectively corresponding RNx and FNx as output RNQ and FNQ, according to chronological order sequence alternate output RNQ and
The permanent High level bit number of the corresponding serial data received of FNQ, RNQ, continuing for the corresponding serial data received of FNQ are low
Level bit number.
Method and device based on aforementioned present invention, the serial data of any agreement of reception that differentiation is not added that can be pervasive
Including synchronous serial data (0001) and asynchronous serial data (0002) (0000), it is only necessary to by the serial number received it is believed that
Number limited range enlargement and delay, not no complicated analog circuit, circuit structure is simple and reliable and is easily achieved, trigger
(0200) maximum clock frequency of circuit is exactly the maximum data transmission rate, low cost, high-performance, universality etc., keeps it wide
General is used to high speed transmission data.
Two, the sending method and device of asynchronous serial data[1][2][3][4][5]
This section illustrates the sending method and device of asynchronous serial data of the invention (0002).
One transmission channel (2000) is that unit sends data with transmission frame (2010), can be inserted between adjacent transmission frame
Enter can be zero any number of idle bit (2020) and is followed by quantity transmission frame is by 1 initial bits (2022)
Variable N number of content bits (2024) are terminated by 1 stopping bit (2026), initial bits and the useful signal for stopping bit
Level is different, and idle bit is identical with the useful signal level of bit is stopped, and if initial bits are that high level is effective, then stops ratio
Special and idle bit is that low level is effective, if initial bits are that low level is effective, then stop bit and idle bit is high level
Effectively, the signal of transmission channel can be single-ended signal or both-end differential signal.
The intension of N number of content bits (2024) is any in transmission frame (2010), can be market bit (2030), data ratio
Special (2032), Command field bit (2034), check bit (2036), alignment bit (2038), exchange bit (2040) etc. are a variety of,
If defining the market bit of 1 bit, transmission frame (2010) be divided into not Command field bit data frame (2012) and
There is no the command frame (2014) of data bit, the bit number of other type content bits can be 0 or 1 or multiple, content bits
It can be original data or order, be also possible to that original data or order are scrambled, encrypt, encode etc. with processing
As a result, check bit allows data receiver to find error of transmission in real time, alignment bit is that periodic cycle adds a variation
It is aligned serial number (2050), is used to be aligned assembling combined frames (2016) by data receiver, exchange bit is in particular range
Destination address (2060) allows the realization exchange transmission (2070) that interchanger is simple and direct, and destination address can be subdivided into multiple
Hierarchical address (2062) is suitable for multistage exchange (2072) transmission.
Multiple transmission channels (2000) can form a combination channel (2100), and the multiple transmission channels for combining channel are same
When the transmission frame (2010) that sends time for reaching receiving end have delay variance (2110), it is therefore desirable to be aligned measure (2120) guarantor
Whole transmission frames in card combination channel can correctly be combined into a combined frames (2120), and of the invention is several alternative
Preferred alignment measure is as follows:
It 1, is the one transmission delay of each transmission channel (2000) setting for combining channel (2100) in data sending terminal
(2112), the hair of each transmission channel in combination channel is controlled and adjusted using the period of tranmitting data register or half period as chronomere
Delay is sent, keeps delay variance (2110) as small as possible, data receiver need to measure delay variance and inform data sender, data
Receiving end also needs to implement measures to ensure that delay variance not the correct combination for influencing combination packet.
2, with determining or uncertain time interval, data sending terminal sends the alignment comprising alignment bit (2038)
Command frame (2014), data receiver receive and realign data buffer zone according to alignment bit after alignment command frame (2014)
In transmission frame (2010).
3, the transmission channel (2000) that the method for item 1 is suitable for combining channel (2100) concentrates feelings on a single chip
Condition, the transmission channel that the method for item 2 is suitable for combining channel are distributed in the situation on multiple chips.
At regular intervals in continuously transmission data, a certain number of idle bits are inserted between transmission frame (2010)
(2020), the equipment for executing relaying transmission, such as repeater (repeater), interchanger (switch), can by increasing or
The quantity for reducing idle bit, to adapt to the tranmitting data register of data source and the frequency difference of data intended recipient clock, when making
The data buffer zone of the lower receiving device of clock frequency is from overflowing.
Three, the method for reseptance and device of asynchronous serial data[1][2][3][4][5]
This section illustrates the method for reseptance and device of asynchronous serial data of the invention (0002).
In this specification " sending method and device of asynchronous serial data " part, describe with initial bits (2022)
Start, content bits (2024) are placed in the middle, stop bit (2026) bring up the rear constitute transmission frame (2010), insertion can between transmission frame
Be zero any number of idle bit (2020) asynchronous serial data (0002) sending method, this specification can be used
Method receiving asynchronous serial data described in " method of reseptance and device of pervasive serial data " part provides this again herein
The method and device of the special receiving asynchronous serial data of invention.
In this section the following description, agreement initial bits (2022) significant level is low level L, stops bit (2026)
Be high level H, content bits (2024) number with idle bit (2020) significant level be variable Integer N, content bits from
Bit 0 starts to transmit, and initial bits, the significant level for stopping bit and idle bit are exchanged, and method of the invention will not be with
Change.
With this specification " method of reseptance and device of pervasive serial data " part, tranmitting data register week is indicated with TXT
Phase (0050), with RXT indicate receive clock cycle (0060), receive clock be four clock AK (AKP, AKN), BK (BKP,
BKN), CK (CKP, CKN), DK (DKP, DKN), their period are all RXT, AK and BK, BK and CK, CK and DK, DK and AK
Be delayed the time difference be all that RXT/4, TXT and RXT are approximately equal, TXT can dynamic change, TXT change when RXT must also change therewith.
Measured signal (0010) is also possible to photoelectric conversion and processing either directly receive and treated electric signal
Measured signal is processed into serial data (0000) signal SI (SIP, SIN) and its postpones signal (0070) SD by electric signal afterwards
(SDP, SDN), SD is identical as SI waveform but postpones about RXT/8.
It is different from the method for this specification " method of reseptance and device of pervasive serial data " part explanation, frequency dividing is not used
Method generate the signal for being synchronized sampling, but asynchronous serial data (0002) signal SI and its postpones signal to receive
(0070) initial bits (2022) of SD start M signal (3000) rxTask and intermediate delay (3010) dxTask, dxTask
Forward position postpone about RXT/8 relative to the forward position of rxTask, the forward position of rxTask originates the reception of a transmission frame (2010)
The significant level and inactive level of journey, rxTask and dxTask respectively with initial bits and stop bit (0226) significant level
Identical, rxStop signal effectively makes rxTask and dxTask return to inactive level, is ready to receive next transmission frame, rxStop
Significant level and inactive level it is identical as the significant level for stopping bit and initial bits respectively.
Table 4 is to generate to be synchronized sampling (0220) signal rxTask and dxTask when asynchronous serial data (0002) receives
Verilog coded description.
Table 4, the Verilog coded description for generating rxTask and dxTask signal
The SI PO shift register (0210) constituted respectively with trigger (0200, flip-flop) is right respectively
RxTask and dxTask carries out four phase clock synchronized samplings (0220), and XK (XKP, XKN) indicates four phase clocks such as AK, BK, CK, DK
One of, it is AK, BK, CK, DK that X A, B, C, D, which are respectively indicated and synchronized the clock of sampling, rxTaskX [3:0] and dxTaskX
[1:0] is the output of the synchronized sampling shift register of one of corresponding four phase clocks respectively, the series of shift register increase by 1 or
2 synchronized samplings that can be more reliable.Table 5 is when asynchronous serial data (0002) receives to rxTask and dxTask synchronized sampling
(0220) Verilog coded description.
The Verilog coded description of synchronized sampling when table 5, asynchronous serial data receive
Table 6 is to carry out four phase clock synchronized samplings to rxTask and dxTask signal when asynchronous serial data (0002) receives
(0220) the Verilog coded description that sampling time sequence differentiates, is based on sampling time ranking results, chooses and be in interposition
The corresponding sampling clock of sampling is set as stablizing sampling clock, the input data of phase sampling clock acquisition be exactly receive it is different
Walk serial data.
Since dxTask signal is relative to rxTask signal delay about RXT/8, to the synchronized sampling of dxTask signal
(0220) advanced about RXT/8 is equivalent to the synchronized sampling of rxTask signal, therefore rxTaskX and dxTaskX is constituted pair
The equivalent eight phase clocks synchronized sampling in the forward position of rxTask indicates the four phase clock relative timings in the forward position rxTask with A, B, C, D
(0230), the four phase clock relative timings in the forward position dxTask are indicated with a, b, c, d, then the variation of eight phase clock relative timings is
AAbBcCdD, AbBcCdDa, bBcCdDaA, BcCdDaAb, cCdDaAbB, CdDaAbBc, dDaAbBcC, DaAbBcCd etc..
Table 6 gives eight phase clock relative timings (0230) sequence of the invention and selects to stablize sampling clock
Verilog coded description, since the delay time difference (0130) is an approximation and unstable, to be in A, B, C, D in list
Middle position person is as sampling clock is stablized, if SD signal is ignored, the time-sequencing selection stabilization based on rxTadkX is adopted
Sample clock can be randomly selected one of two phase clock in an intermediate position, can also increase the settling time of shift register
Alternatively condition, St >=Ht then select the position of two phase clock to exist by (set time) St and retention time (hold time) Ht
The latter, St < Ht then select the position of two phase clock at the former.
RxOrder is relative timing (0230) sequence as a result, rxClock is the selection knot for stablizing sampling clock in table 6
Fruit, when rxClock is respectively 0,1,2,3, corresponding stable sampling clock is AK, BK, CK, DK respectively.
Stablize the Verilog coded description that sampling clock differentiates in when table 6, asynchronous serial data receive
Table 7 is the Verilog coded description of data sampling (3020) when asynchronous serial data (0002) receives, ginseng therein
Number rxBits is exactly the bit number N of content bits (2024), and parameter rxBnum is the bit number of content bits counter,
RxShiftX is the position the N+2 SI PO shift register (0210) of the data sampling of asynchronous serial data SI, the shift LD
The digit of device increases by 1 or 2 available more reliable data sampling, and rxBcntX is data sampling counter, and rxTcntX is several
According to sample count end signal, rxStopX is that transmission frame (2010) receive end signal, and rxTrigX is asynchronous serial data lock
Signal is deposited, between the rear edge of rxTrigX and the 2nd of the parallel output of synchronized sampling rxTask signal shift register forward position
Time interval be N+2 reception clock cycle, the time interval is also increase accordingly when the number of shift register bit increases, asynchronous
Serial data is latched on the rear edge of rxTrigX, and rxData is the content bits latched, and rxDssX is the stopping bit latching
(2026) and initial bits (2022), X are respectively that A, B, C, D etc. indicate data sampling corresponding with AK, BK, CK, DK isochronon.
RxStop is the end signal that a transmission frame (2010) finishes receiving, it resets rxTask and dxTask, quasi-
It gets ready and receives next transmission frame, rxDataX corresponding with reception clock XK is stablized is exactly the asynchronous serial data received
(0002) content bits (2024) rxData, stablizing the corresponding rxDssX of reception clock XK should be 2 ' b10, if not 2 '
B10 then indicates to receive synchronous error, and sending direction recipient continuously transmits the idle bit (2020) more than rxBits+2, i.e.,
Recipient can be made to restore normal synchronized state, sender is allowed to learn that recipient loses there are two types of synchronous preferred method: first is that
Receiving direction sender continuously transmits the idle bit (2020) more than rxBits+2, second is that receiving direction sender sends one
A status frames (3030) report mistake.
The Verilog coded description of data sampling when table 7, asynchronous serial data receive
Based on above description, asynchronous serial data of the invention (0002) method of reseptance is had the following characteristics that
1, multiple channels can be combined into multichannel connection, and data, transmission frame are transmitted in each channel as unit of transmission frame
Started with 1 initial bits, N number of content bits of dynamically changeable are placed in the middle, 1 stopping bit being brought up the rear and constituted, between transmission frame
Insertion can be zero any number of idle bit, and the significant level of initial bits is different with the significant level of bit is stopped,
The significant level of idle bit is identical as the significant level of bit is stopped, and the meaning of content bits is any, initial bits and stopping
The significant level of bit and idle bit is interchangeable, and continuously transmitting more than N+2 idle bit can be such that recipient regains together
Step at regular intervals in continuously transmission data is inserted into a certain number of idle bits between transmission frame, executes relaying and passes
The equipment sent, such as repeater, interchanger, can be by increasing or decreasing the quantity of idle bit, to adapt to data source
The frequency difference of tranmitting data register and data intended recipient clock, make the data buffer zone of the lower receiving device of clock frequency from
It overflows；
2, four phase clock AK, BK, CK, DK that the period is RXT are provided, when AK, BK, CK, DK successively have the delay of RXT/4
Difference, RXT is approximately equal with serial data tranmitting data register cycle T XT, TXT can dynamic change, TXT change when RXT must also become therewith
Change；
3, single-ended or difference measured signal is also possible to photoelectricity and turns either directly receive and treated electric signal
Change and treated electric signal, by measured signal be processed into serial data signal SI (SIP, SIN) and its postpones signal SD (SDP,
SDN), SD is identical as SI waveform but delay about RXT/8, the effect of SD are to make system that can work in minimum more may be used near RXT value
The work leaned on can be ignored when working under biggish RXT value；
4, M signal rxTask and dxTask are generated based on SI and SD signal, rxTask and dxTask are respectively in SI and SD
The forward position of the initial bits of signal is turned to initial bits significant level by stopping bit significant level, and rxTask and dxTask are same
When SI signal stopping bit arrive when by initial bits significant level be turned to stop bit significant level, rxTask and
The forward position overturning of dxTask must keep having about RXT/8 delay as SI and SD, and rxTask and the rear of dxTask must be protected along overturning
It demonstrate,proves after its overturning in stopping bit significant level until stopping bit terminating and do not influence it to follow initial bits next time
Forward position overturning；
5, rxTask with dxTask signal is carried out respectively respectively with SI PO shift register four phase clocks synchronize adopt
Sample, choose the 2nd or 3 or 4 of the parallel output of four phase clock sample shift registers of the same signal as rxTaskX and
DxTaskX carries out time-sequencing, and X is that one of A, B, C, D indicate that corresponding respectively to synchronizing for one of AK, BK, CK, DK clock adopts
Sample is selected to stablize sampling clock based on time-sequencing, indicates the time-sequencing to rxTask signal synchronized sampling with A, B, C, D,
The time-sequencing to dxTask signal synchronized sampling is indicated with a, b, c, d, and the synchronized sampling of dxTask signal is equivalent in advance
The about RXT/8 time to the synchronized sampling of rxTask signal, that is, be equivalent to rxTask signal carry out eight phase clock synchronized samplings, eight
The time-sequencing of phase clock synchronized sampling have aAbBcCdD, AbBcCdDa, bBcCdDaA, BcCdDaAb, cCdDaAbB,
Eight kinds of CdDaAbBc, dDaAbBcC, DaAbBcCd etc. sequence, corresponding stable sampling clock be BK, CK, CK, DK, DK, AK,
AK, BK etc., when SD signal is ignored, the time-sequencing of four phase clock synchronized samplings has four kinds of ABCD, BCDA, CDAB, DABC etc.
Sequence can be randomly selected one of two phase clock in an intermediate position and be used as and stablizes sampling clock, i.e. BK/CK, CK/DK, DK/
AK, AK/BK etc. can also increase the settling time of shift register and hold time as alternative condition, and settling time is greater than
Or when being equal to the retention time, respectively corresponds selection CK, DK, AK, BK and respectively correspond selection when settling time is less than the retention time
The forward position overturning of BK, CK, DK, AK, each rxTask have a corresponding stable sampling clock；
6, it carries out four phase clocks respectively to SI signal with N+2 bit SI PO shift register rxShiftX and synchronizes to adopt
Sample, the minimum N+2 bit of the parallel output of the shift register is in the parallel of the shift register with synchronized sampling rxTask
It is latched as rxDataX at the 2nd forward position overturning N+2 reception clock cycle of interval of output, the position of the shift register
Number increase by 1 or 2 can obtain more reliable data sampling and latch the time interval of rxDataX when the digit of shift register increases
Also it increase accordingly, based on the stabilization sampling clock XK that the forward position rxTask overturning synchronized sampling time-sequencing determines, selects corresponding
RxDataX is starting respectively as the asynchronous serial data rxData output received, the minimum and the highest-order bit of rxData
Bit and stop bit, between the minimum data between the highest-order bit is content bits in rxData.
Method and device based on aforementioned present invention, can be with the asynchronous serial data of any agreement of reception of minimum cost
(0002), synchronous serial data (0001) communication of any agreement can also be realized in an asynchronous manner, it is only necessary to by what is received
Serial data signal limited range enlargement and delay, not complicated analog circuit, circuit structure is simple and reliable and is easily achieved,
The maximum clock frequency of trigger (0200) circuit is exactly the maximum data transmission rate, the spies such as low cost, high-performance, universality
Point makes it that can widely be used to high speed transmission data.
Four, the application of Serial data receiving method and device[1][2][3][4][5]
This section illustrates the application of serial data (0000) transceiver realized based on method and device of the invention.
In the foregoing description, The present invention gives the method for reseptance and device of two kinds of serial datas (0000), serial numbers
It is relatively simple according to the method and device of transmission, and the method for Serial data receiving is then more complicated and is difficult to realize, this hair
The method and device of bright offer maximally simplifies the structure of Serial data receiving device, keeps its low in cost and is easy to
It realizes, and not only can satisfy high performance application demand, also can satisfy the application demand of low cost and low-power consumption.
For concise description, this specification is called with USRT (Universal Serial Receievr/Transmitter)
The serial data communication device that the method for " method of reseptance and device of pervasive serial data " part is realized, uses UART
(Universal Asynchronous Receiever/Transmitter) calls this specification " reception of asynchronous serial data
Method and device " part method realize serial data communication device.
Merogenesis is illustrated to the application of the method for the present invention below.
(1) the synchronous serial data communication on asynchronous serial data communication physical layer[1][2][3][4][5]
Using this specification " method of reseptance and device of asynchronous serial data " part description method and device, it can be achieved that
Asynchronous serial data (0002) communication of same high data rate is communicated with synchronous serial data (0001), therefore can be different
On the physical layer for walking serial data communication, realizes the data link layer and layer protocols of synchronous serial data communication, reduce
The power consumption and cost of interface, the feature of this method are as follows:
1, the method and device realization as described in this specification " method of reseptance and device of asynchronous serial data " part connects
Receive and send the physical layer protocol of asynchronous serial data；
2, content bits of the synchronous serial data of data link layer and protocol layer as the asynchronous serial data of physical layer
It sends；
3, the content bits of the asynchronous serial data of the physical layer received submit to the data of synchronous serial data communication
Link layer and protocol layer:
4, each port is made of one or a set of asynchronous serial data channel.
(2) a kind of general purpose computer central processing unit[1][4]
Current general purpose computer central processing unit (4200, CPU), there are many external interfaces, " pervasive using this specification
The method of reseptance and device of serial data " and/or " method of reseptance and device of asynchronous serial data " and/or " asynchronous serial number
According to the synchronous serial data communication on communication physical layer " etc. part description method and device, it can be achieved that only there are two types of (USRT
And UART) even only a kind of universal cpu of (UART) physical layer external interface of physical layer, Fig. 5 give using USRT and/or
The schematic diagram of the universal cpu of UART interface, in whole new definition or the case where using existing data link layer and layer protocols
Under, the physical layer protocol of CPU external interface is based on USRT or UART and defines, and physical layer protocol is based only on UART definition then more preferably,
The feature of this general central processor is as follows:
1, the inside structure of central processing unit is any, whole new definition framework or the existing framework of use；
2, such as this specification " method of reseptance and device of pervasive serial data " and/or " recipient of asynchronous serial data
Method and device " and/or the part description such as " synchronous serial data communication " on asynchronous serial data communication physical layer method
And device realizes the physical layer protocol for sending and receiving serial data of its one-way or bi-directional external interface；
3, whole new definition or data link layer and layer protocols using existing external interface；
4, the operational order of one way ports, write-in data, status data, reading data sharing a port, bidirectional port
Operational order and write-in data by input port input, status data and read data and exported by output port；
5, each port is made of one or a set of pervasive serial data channel or asynchronous serial data channel.
(3) a kind of memory of asynchronous serial data interface[1][4][5]
Current general external memory mainly has DRAM/SDRAM (4300), SRAM (4310), FLASH (4320) etc.,
All using parallel or serial data and control interface, using this specification " method of reseptance and device of asynchronous serial data "
Part description method and device, it can be achieved that UART physical layer interface single port or multiport DRAM/SDRAM, SRAM,
FLASH etc., can be directly general with a kind of one or more of this specification " general central processing unit (CPU) " part description
CPU is directly connected to, and Fig. 6 gives the schematic diagram using DRAM/SDRAM, SRAM, FLASH of UART interface etc., this memory
Feature it is as follows:
1, the framework of the inside of the memories such as DRAM/SDRAM or SRAM or FLASH is any, whole new definition framework or use
Existing framework；
2, the method and device as described in this specification " method of reseptance and device of asynchronous serial data " part is realized single
One-way or bi-directional physical layer protocol for sending and receiving asynchronous serial data of port or multiport:
3, whole new definition or use existing operational order and status information；
4, the operational order of one way ports, write-in data, status information, reading data sharing a port, bidirectional port
Operational order and write-in data by input port input, status information and read data and exported by output port；
5, each port is made of one or a set of asynchronous serial data channel.
(4) a kind of Memory Controller of asynchronous serial data interface[1][4][5]
Current general external memory mainly has DRAM/SDRAM (4300), SRAM (4310), FLASH (4320) etc.,
All using parallel or serial data and control interface, using this specification " method of reseptance and device of asynchronous serial data "
Part description method and device, it can be achieved that UART physical layer interface single port or multiport DRAM/SDRAM, SRAM,
The controller of the memories such as FLASH can be described directly with a kind of this specification " general central processing unit (CPU) " part
One or more universal cpus are directly connected to, and Fig. 7 gives to be stored using DRAM/SDRAM, SRAM, FLASH of UART interface etc.
The schematic diagram of device module and controller, Memory Controller inside modules connect DRAM/SDRAM and/or SRAM and/or
The memories such as FLASH, external-connected port are the UART interfaces of single port or multiport, and the feature of the controller of this memory is such as
Under:
1, any with the interface architecture of the memories such as DRAM/SDRAM or SRAM or FLASH, whole new definition framework or use
Existing framework；
2, the method and device as described in this specification " method of reseptance and device of asynchronous serial data " part is realized single
One-way or bi-directional physical layer protocol for sending and receiving asynchronous serial data of port or multiport；
3, whole new definition or use existing operational order and status information；
4, the operational order of one way ports, write-in data, status information, reading data sharing a port, bidirectional port
Operational order and write-in data by input port input, status information and read data and exported by output port；
5, each port is made of one or a set of asynchronous serial data channel.
(5) a kind of interface controller of computer peripheral[1][4][5]
Current general external apparatus interface mainly have synchronous serial, simultaneously and concurrently, asynchronous parallel, asynchronous serial etc., adopt
With this specification " method of reseptance and device of pervasive serial data " and/or " method of reseptance and device of asynchronous serial data "
And/or the method and device of " the synchronous serial data communication on asynchronous serial data communication physical layer " part description, it can be real
External apparatus interface now based on UART physical layer protocol, can directly with a kind of this specification " general computer central processing
Device " part description one or more universal cpus be directly connected to, Fig. 8 gives and sets outside the computer based on UART physical layer
The feature of the schematic diagram of standby interface controller, this computer external interface is as follows:
1, the inside structure of external apparatus interface controller is any, whole new definition framework or the existing framework of use；
2, such as this specification " method of reseptance and device of pervasive serial data " and/or " recipient of asynchronous serial data
Method and device " and/or the part description such as " synchronous serial data communication " on asynchronous serial data communication physical layer method
And device realizes the physics for sending and receiving serial data of device controller and the one-way or bi-directional connection of computer system
Layer protocol；
3, whole new definition or use existing data link layer and layer protocols；
4, the operational order of one way ports, write-in data, status information, reading data sharing a port, bidirectional port
Operational order and write-in data by input port input, status information and read data and exported by output port；
5, each port is made of one or a set of pervasive serial data channel or asynchronous serial data channel.
(6) a kind of relay of data transmission[1][2][3][4][5]
The method of any one transmission data, the maximum distance of transmission is restricted, if to transmit farther distance,
Trunking refile data are then needed, using this specification " method of reseptance and device of pervasive serial data " and/or " different
Walk the method for reseptance and device of serial data " and/or " synchronous serial data on asynchronous serial data communication physical layer is logical
Letter " etc. part description method and device, it can be achieved that being based on USRT or UART physical layer repeater, Fig. 9 gives using USRT
Or the schematic diagram of the data transmission relay of UART physical layer, original data link layer and agreement are being kept by trunk interface
In the case where layer protocol, original physical layer is replaced by USRT or UART, only more preferably by UART replacement, in this data transmission
It is as follows after device characteristic:
1, the framework of the data transfer interface relayed is any, whole new definition framework or the existing framework of use；
2, such as this specification " method of reseptance and device of pervasive serial data " and/or " recipient of asynchronous serial data
Method and device " and/or the part description such as " synchronous serial data communication " on asynchronous serial data communication physical layer method
And device realizes the physical layer protocol of data transmission relaying；
3, keep constant by the data link layer of trunk interface and layer protocols；
4, data transmission relaying is made of one or a set of pervasive serial data channel or asynchronous serial data channel.
(7) a kind of interchanger of system area network[1][3][4]
System area network is the data transport network inside high-performance computer system, and performance and power consumption are higher, rule
Data transport network inside the small server of as low as one uniprocessor of mould, scale have tens of thousands of a processors to one greatly
Data transport network inside supercomputer, in the computer system of multiprocessor, system area network interchanger is often
Indispensable core component, using this specification " method of reseptance and device of pervasive serial data " and/or " asynchronous serial number
According to method of reseptance and device " and/or parts such as " synchronous serial data communication " on asynchronous serial data communication physical layer
The method and device of description is, it can be achieved that the system area network interchanger based on USRT or UART physical layer, Figure 10, which gives, to be based on
The schematic diagram of the system area network interchanger of USRT or UART physical layer protocol, the feature of this system area network interchanger is such as
Under:
1, the inside structure of interchanger is any, whole new definition framework or the existing framework of use；
2, such as this specification " method of reseptance and device of pervasive serial data " and/or " recipient of asynchronous serial data
Method and device " and/or the part description such as " synchronous serial data communication " on asynchronous serial data communication physical layer method
And device realizes the physical layer protocol of system domain exchange network；
3, whole new definition or use existing data link layer and layer protocols；
4, each port is made of one or a set of pervasive serial data channel or asynchronous serial data channel.
(8) interchanger and/or router of a kind of computer network[1][2][3]
Computer network is the data transport network between computer, the data transfer network inside scale as low as one family
Network, for scale greatly to the data transport network for having tens of thousands of computers inside a university, Internet is then a global area
Computer network, interchanger and router are the necessary equipments of computer network, using this specification " pervasive serial data
Method of reseptance and device " and/or " method of reseptance and device of asynchronous serial data " and/or " asynchronous serial data communication physics
Layer on synchronous serial data communication " etc. part description method and device, it can be achieved that based on USRT or UART physical layer
Network switch for computer and/or router, Figure 11 give the friendship of the computer network based on USRT or UART physical layer protocol
It changes planes and/or the schematic diagram of router, the feature of this network switch for computer and/or router is as follows:
1, the inside structure of interchanger and/or router is any, whole new definition framework or the existing framework of use；
2, such as this specification " method of reseptance and device of pervasive serial data " and/or " recipient of asynchronous serial data
Method and device " and/or the part description such as " synchronous serial data communication " on asynchronous serial data communication physical layer method
And device realizes the physical layer protocol of network exchange and/or routing；
3, whole new definition or use existing data link layer and layer protocols；
4, each port is made of one or a set of pervasive serial data channel or asynchronous serial data channel.
(9) a kind of switch or router of communication network[1][2][3][4]
Communication network is the data transport network of global area, and interchanger and router are the indispensable portions of communication network
Part, using this specification " method of reseptance and device of pervasive serial data " and/or " method of reseptance and dress of asynchronous serial data
Set " and/or the part description such as " synchronous serial data communication " on asynchronous serial data communication physical layer method and device,
Can be achieved communication network switch and/or router based on USRT or UART physical layer, Figure 12 give based on USRT or
The communication network switch of UART physical layer protocol and/or the schematic diagram of router, this communication network switch and/or routing
The feature of device is as follows:
1, the inside structure of interchanger and/or router is any, whole new definition framework or the existing framework of use；
2, such as this specification " method of reseptance and device of pervasive serial data " and/or " recipient of asynchronous serial data
Method and device " and/or the part description such as " synchronous serial data communication " on asynchronous serial data communication physical layer method
And device realizes the physical layer protocol of network exchange and/or routing；
3, whole new definition or use existing data link layer and layer protocols；
4, each port is made of one or a set of pervasive serial data channel or asynchronous serial data channel.
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[3]InfinibandTMArchitecture Spacification, Volume 1, release 1.2,
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Layers and Power Management Elements.
Claims (9)
1. a kind of method of reseptance of pervasive serial data, comprising:
A) operable serial data communication protocol provides physical layer connection, including synchronous serial data communication and asynchronous serial number
According to communication, multiple channels can be combined into multichannel connection；
B) four phase clock AK, BK, CK, DK that the period is RXT are provided, AK, BK, CK, DK successively have the delay time difference of RXT/4, RXT
It is equal with serial data tranmitting data register cycle T XT but have minute differences, TXT can dynamic change, RXT also must be therewith when TXT changes
Variation；
C) single-ended or difference measured signal is also possible to photoelectric conversion and place either directly receive and treated electric signal
Measured signal is processed into serial data signal SI and its postpones signal SD, SD and SI waveform is identical but prolong by the electric signal after reason
Late it is RXT/8 but admits of error, the effect of SD is the work for keeping system relatively reliable when minimum can work RXT value, big
RXT value under can be ignored when working；
D) it is respectively obtained 1 or 2 corresponding SI and SD respectively by the frequency dividing of SI and SD signal 2 or 4 frequency dividings with latch and rises overturning
Signal RI and RD, 1 or 2 corresponding SI and SD decline overturning signal FI and FD, the overturning palpus of RI and RD, FI and FD signal
Holding has RXT/8 to postpone as SI and SD but admits of error, and the effect of frequency dividing is to ensure that AK, BK, CK, DK can be acquired
To the overturning each time of RI, RD, FI, FD signal；
E) four phase clock synchronized samplings are carried out respectively to RI, RD, FI, FD signal respectively with SI PO shift register, chosen
The the 2nd or 3 or 4 RIx, RDx, FIx, FDx of the parallel output of four phase clock sample shift registers of the same signal distinguish
Time-sequencing is carried out, x is that one of A, B, C, D indicate to correspond respectively to the synchronized sampling of one of AK, BK, CK, DK clock, when being based on
Between sequencing selection stablize sampling clock, the time-sequencing to RI, FI signal synchronized sampling is indicated with A, B, C, D, with a, b, c, d table
Show the time-sequencing to RD, FD signal synchronized sampling, RXT/8 in advance is equivalent to the synchronized sampling of RD, FD signal but admits of
The time of error to the synchronized sampling of RI, FI signal, that is, is equivalent to and carries out eight phase clock synchronized samplings, eight phases to RI, FI signal
The time-sequencing of clock synchronized sampling have aAbBcCdD, AbBcCdDa, bBcCdDaA, BcCdDaAb, cCdDaAbB,
Eight kinds of CdDaAbBc, dDaAbBcC, DaAbBcCd sequence, corresponding stable sampling clock be BK, CK, CK, DK, DK, AK, AK,
When BK, SD signal are ignored, the time-sequencing of four phase clock synchronized samplings has tetra- kinds of ABCD, BCDA, CDAB, DABC sequences, can
To randomly choose one of two phase clock in an intermediate position as stablizing sampling clock, i.e. BK/CK, CK/DK, DK/AK, AK/
BK can also increase the settling time of shift register and hold time as alternative condition, and settling time, which is greater than or equal to, protects
When holding the time, respectively correspond selection CK, DK, AK, BK, settling time be less than the retention time when, respectively correspond selection BK, CK, DK,
AK, the overturning of each RI, FI signal have a corresponding stable sampling clock；
F) RIx is obtained respectively to overturn in-phase clock count value RNx, the FIx overturning between FIx overturning followed by and follow closely
Thereafter the in-phase clock count value FNx between RIx overturning, is based respectively on RI overturning and FI overturns corresponding stable sampling clock
XK, selects corresponding RNx and FNx as output RNQ and FNQ respectively, exports RNQ and FNQ according to chronological order sequence alternate,
The permanent High level bit number of the corresponding serial data received of RNQ, the lasting low level of the corresponding serial data received of FNQ
Bit number.
2. a kind of general purpose computer central processing unit, comprising:
A) inside structure of operable central processing unit；
B) method as claimed in claim 1 realizes the physical layer protocol of the reception serial data of its one-way or bi-directional external interface；
C) data link layer and layer protocols of operable external interface；
D) operational order of one way ports, write-in data, status data, reading data sharing a port, the behaviour of bidirectional port
Make order and write-in data and is exported by input port input, status data and reading data by output port；
E) each port is made of one or a set of pervasive serial data channel or asynchronous serial data channel.
3. a kind of memory of asynchronous serial data interface, comprising:
A) inside structure of operable DRAM/SDRAM or SRAM or FLASH memory；
B) method as claimed in claim 1 realizes the physics of one-way or bi-directional receiving asynchronous serial data of single port or multiport
Layer protocol；
C) operable operational order and status information；
D) operational order of one way ports, write-in data, status information, reading data sharing a port, the behaviour of bidirectional port
Make order and write-in data and is exported by input port input, status information and reading data by output port；
E) each port is made of one or a set of asynchronous serial data channel.
4. a kind of Memory Controller of asynchronous serial data interface, comprising:
A) the operable interface architecture with DRAM/SDRAM or SRAM or FLASH memory；
B) method as claimed in claim 1 realizes the physics of one-way or bi-directional receiving asynchronous serial data of single port or multiport
Layer protocol；
C) operable operational order and status information；
D) operational order of one way ports, write-in data, status information, reading data sharing a port, the behaviour of bidirectional port
Make order and write-in data and is exported by input port input, status information and reading data by output port；
E) each port is made of one or a set of asynchronous serial data channel.
5. a kind of interface controller of computer peripheral, comprising:
A) inside structure of the interface controller of operable external equipment；
B) method as claimed in claim 1 realizes that device controller and the reception of the one-way or bi-directional connection of computer system are serial
The physical layer protocol of data；
C) operable data link layer and layer protocols；
D) operational order of one way ports, write-in data, status information, reading data sharing a port, the behaviour of bidirectional port
Make order and write-in data and is exported by input port input, status information and reading data by output port；
E) each port is made of one or a set of pervasive serial data channel or asynchronous serial data channel.
6. a kind of relay of data transmission, comprising:
A) framework of the operable data transfer interface relayed；
B) method as claimed in claim 1 realizes the physical layer protocol of data transmission relaying；
C) keep constant by the data link layer of trunk interface and layer protocols；
D) data transmission relaying is made of one or a set of pervasive serial data channel or asynchronous serial data channel.
7. a kind of interchanger of system area network, comprising:
A) inside structure of operable interchanger；
B) method as claimed in claim 1 realizes the physical layer protocol of system domain exchange network；
C) operable data link layer and layer protocols；
D) each port is made of one or a set of pervasive serial data channel or asynchronous serial data channel.
8. the interchanger and/or router of a kind of computer network, comprising:
A) inside structure of operable interchanger and/or router；
B) method as claimed in claim 1 realizes the physical layer protocol of network exchange and/or routing；
C) operable data link layer and layer protocols；
D) each port is made of one or a set of pervasive serial data channel or asynchronous serial data channel.
9. the interchanger and/or router of a kind of communication network, comprising:
A) inside structure of operable interchanger and/or router；
B) method as claimed in claim 1 realizes the physical layer protocol of network exchange and/or routing；
C) operable data link layer and layer protocols；
D) each port is made of one or a set of pervasive serial data channel or asynchronous serial data channel.
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| CN201410313411.6A CN105224485B (en) | 2014-07-03 | 2014-07-03 | A kind of method of reseptance and device of pervasive serial data |
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| CN201410313411.6A CN105224485B (en) | 2014-07-03 | 2014-07-03 | A kind of method of reseptance and device of pervasive serial data |
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| CN106326158B (en) * | 2016-08-18 | 2019-05-07 | 长沙丰灼通讯科技有限公司 | The method for generating clock output with asynchronous bus |
| CN109885525B (en) * | 2019-03-19 | 2021-02-12 | 西安联飞智能装备研究院有限责任公司 | UART receiving method, device, electronic equipment and readable storage medium |
| CN112311405B (en) * | 2019-08-01 | 2022-06-14 | 円星科技股份有限公司 | Integrated circuit in physical layer of receiver and physical layer of receiver |
| CN111142785B (en) * | 2019-11-28 | 2023-05-09 | 北京遥测技术研究所 | Processing method and processor for influence data transmission of tail flame of high-speed aircraft |
| CN113078980A (en) * | 2019-12-18 | 2021-07-06 | 华为技术有限公司 | Data transmission method and device |
| CN117389928A (en) * | 2023-10-27 | 2024-01-12 | 中科驭数（北京）科技有限公司 | Data transmission method, device, equipment and storage medium |
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