CN112311405B - Integrated circuit in physical layer of receiver and physical layer of receiver - Google Patents

Abstract

An integrated circuit in a physical layer of a receiver and a physical layer of a receiver are disclosed. The integrated circuit comprises a multi-channel interface, a channel selection circuit and N sampling circuits. The multi-channel interface has N channels. The channel selection circuit is coupled to the multi-channel interface, and is configured to select M channels of the N channels as M clock channels and output M signals on the M clock channels, respectively. M is a positive integer less than N. The remaining (N-M) channels are used as (N-M) data channels. The N sampling circuits are coupled to the multi-channel interface and the channel selection circuit. (N-M) of the N sampling circuits are coupled to the (N-M) data channels, respectively. Each of the (N-M) sampling circuits samples a signal on a data channel of the (N-M) data channels according to one of the M signals. The integrated circuit is capable of supporting different channel configurations on the transmit side.

Description

Integrated circuit in physical layer of receiver and physical layer of receiver

Technical Field

The present invention relates to a clock forwarding interface (clock forwarding interface), and more particularly, to an integrated circuit (ic) having a channel interchangeably used between a clock and a data channel in a clock forwarding interface receiver (clock forwarding interface receiver), and a physical layer (physical layer) of the clock forwarding interface receiver.

Background

Some communication systems utilize a clock forwarding scheme (clock forwarding scheme) to provide high speed data transmission between a transmitter and a receiver. In this clock forwarding scheme, a clock signal is transmitted from a transmitter to a receiver along with one or more data signals. For example, the receiver may include a clock forwarding interface having a clock lane (clock lane) and a plurality of data lanes (data lanes). A clock signal on the clock channel is forwarded (forwarded) from the transmitter to the receiver along with data signals on the data channels. Thus, the receiver may capture the plurality of data signals using the clock signal forwarded by the transmitter. Depending on the physical layer (PHY) specification used, each channel (i.e., clock channel or data channel) in the clock-forwarding interface may be a point-to-point (point-to-point), two-wire (two-wire), or three-wire (three-wire) interface for clock or data transfer.

Disclosure of Invention

Embodiments of the present application disclose an integrated circuit having channels interchangeably usable between clock and data channels in a clock forwarding interface receiver, and an associated physical layer.

Certain embodiments of the present application disclose an integrated circuit of a physical layer of a receiver. The integrated circuit comprises a multi-channel interface, a channel selection circuit and N sampling circuits. N is an integer greater than 1. The multi-channel interface has N channels. The channel selection circuit is coupled to the multi-channel interface, and is configured to select M channels of the N channels as M clock channels and output M signals on the M clock channels, respectively. M is a positive integer less than N. The remaining (N-M) channels are used as (N-M) data channels. The N sampling circuits are coupled to the multi-channel interface and the channel selection circuit. (N-M) of the N sampling circuits are coupled to the (N-M) data channels, respectively. Each of the (N-M) sampling circuits is configured to sample a signal on a data channel of the (N-M) data channels according to one of the M signals on the M clock channels.

Certain embodiments of the present application disclose an integrated circuit of a physical layer of a receiver. The integrated circuit comprises a multi-channel interface, N sampling circuits and a channel selection circuit. N is an integer greater than 1. The multi-channel interface has N channels. The N sampling circuits are coupled to the multi-channel interface. Each of the N sampling circuits has a clock input and a data input. The channel selection circuit is configured to select M of the N channels as M clock channels by coupling the M channels to N clock inputs of the N sampling circuits. M is a positive integer less than N. The remaining (N-M) channels are used as (N-M) data channels. In one mode, one of the N channels is selected as a clock channel coupled to one or more of the N clock inputs. In another mode, the selected one of the N channels serves as a data channel coupled to one of the N data inputs of the N sampling circuits but not to the N clock inputs.

Certain embodiments of the present application disclose a physical layer of a receiver. The physical layer includes a physical medium attachment layer (PMA) and a Physical Coding Sublayer (PCS). The physical medium connection layer is configured to output M clock signals respectively associated with M different clock domains. M is an integer greater than 1. The physical coding sublayer has N channels and is coupled to the physical medium connection layer. N is an integer greater than M. The physical coding sublayer is configured to select M channels of the N channels as M clock channels, and receive the M clock signals through the M clock channels. One or more of the remaining (N-M) of the N lanes are used as one or more data lanes.

The physical layer of the receiving side can support different channel configurations (lane configuration) of the transmitting side by at least one channel that can be used interchangeably between the clock channel and the data channel. For example, the physical layer may be divided into a plurality of physical interfaces to support (support) a plurality of transmitters. In addition, a clock/data lane may be selected based on its lane identifier to facilitate clock/data lane selection.

Drawings

Fig. 1 is a functional block diagram of an illustrative multi-channel communication system according to some embodiments of the present application.

Fig. 2A-2C are schematic diagrams of different modes of the receiver shown in fig. 1 according to some embodiments of the present application.

FIG. 3 is a schematic diagram of an implementation of the integrated circuit shown in FIG. 1 according to some embodiments of the present application.

Fig. 4A-4C are schematic diagrams illustrating operation of the integrated circuit shown in fig. 3 according to some embodiments of the present application.

Fig. 5A-5C are schematic diagrams of other implementations of the integrated circuit shown in fig. 1 according to some embodiments of the present application.

FIG. 6 is a schematic diagram of another implementation of the integrated circuit shown in FIG. 1, according to some embodiments of the present application.

FIG. 7 is a schematic diagram of another implementation of the integrated circuit shown in FIG. 1, according to some embodiments of the present application.

FIG. 8 is a schematic diagram of another implementation of the integrated circuit shown in FIG. 1, according to some embodiments of the present application.

FIG. 9 is a schematic diagram of the operation of the state machine shown in FIG. 7 according to some embodiments of the present application.

FIG. 10 is a schematic diagram of a particular implementation of a channel identifier for the multiple channels shown in FIG. 7, according to some embodiments of the present application.

Fig. 11 is a functional block diagram of an exemplary receiver according to some embodiments of the present application.

FIG. 12 is a schematic diagram of an embodiment of an integrated circuit in the physical coding sublayer shown in FIG. 11, according to some embodiments of the present application.

FIG. 13 is a schematic diagram of another embodiment of an integrated circuit in the physical coding sublayer shown in FIG. 11, according to some embodiments of the present application.

Fig. 14 is a functional block diagram of an exemplary multi-channel communication system according to some embodiments of the present application.

Detailed Description

The following disclosure discloses various embodiments or illustrations that can be used to implement various features of the present disclosure. Specific examples of parameter values, components, and configurations are described below to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled or intervening elements may be present.

The physical layer of a receiver employing a clock forwarding interface may use a dedicated clock lane (dedicated clock lane) to receive a clock signal transmitted through a clock lane of the transmit side (transmitter side). However, in applications where the clock channel and multiple data channels of the transmitter are used interchangeably with each other to meet certain communication requirements, such a receiver would no longer be suitable. For example, the number of transmission devices located on the transmission side may vary. For another example, a transmitting device on the transmitting side may use a clock channel and a data channel interchangeably in some operational scenarios.

An exemplary integrated circuit having interchangeable channels in a clock forwarding interface receiver is disclosed. In some embodiments, the exemplary integrated circuit may be implemented in a sublayer (sublayer) of the physical layer of the clock-forwarding interface receiver, such as a physical media attachment layer (PMA) or a Physical Coding Sublayer (PCS). With the exemplary integrated circuit, the clock forwarding interface receiver can accommodate the use of interchanges between clock lanes and data lanes, supporting different lane configurations on the transmit side.

FIG. 1 is a functional block diagram of an exemplary multi-lane communication system according to some embodiments of the present application. The multi-channel communication system 100 includes K transmitters TX [0] -TX [ K-1] at a transmit side TS and a receiver 104 at a receive side RS, where K is a positive integer. Each of the K transmitters TX [0] -TX [ K-1] may include a multi-channel interface (i.e., one of K multi-channel interfaces TF [0] -TF [ K-1 ]) to transmit clock information and data information. Each of the K multi-channel interfaces TF [0] -TF [ K-1] may include at least one clock channel and at least one data channel (not shown in FIG. 1).

The receiver 104 is configured to communicate with each of the K transmitters TX [0] -TX [ K-1] via a communication link 106. A physical layer 108 of the receiver 104 may employ a clock forwarding scheme to receive clock information and data information transmitted over the communication link 106. Thus, at least one clock signal can be forwarded from the transmitting side TS to the receiving side RS together with at least one data signal. The physical layer 108 includes an integrated circuit 110, which may be disposed at a physical media connection layer or a physical coding sublayer of the physical layer 108. The integrated circuit 110 may be adapted to a variety of channel configurations (lanes) of the transmit side TS. For example, the integrated circuit 110 may operate in a mode to communicate with the transmit side TS, where the transmit side TS uses a single channel as a clock channel to transmit a clock signal. The integrated circuit 110 may operate in another mode to communicate with the transmit side TS, which has the plurality of channels as a plurality of clock channels to transmit a plurality of clock signals.

In this embodiment, the integrated circuit 110 includes, but is not limited to, a multi-lane interface (multi-lane interface)114, a lane selection circuit (lane selection circuit)120, and N sampling circuits RX [0] -RX [ N-1], where N is an integer greater than 1. The multi-channel interface 114 is connected to each of the K multi-channel interfaces TF [0] -TF [ K-1] via the communication link 106. The multi-channel interface 114 includes N channels LA [0] -LA [ N-1 ]. At least one of the N channels LA [0] -LA [ N-1] may be commonly used for an (interchangeable between) clock channel and a data channel, i.e., the at least one channel may be used interchangeably between a clock channel and a data channel.

The channel selection circuit 120 is coupled to the multi-channel interface 114 for selecting N channels LA [0]]-LA[N-1]M channels are selected as M clock channels, where M is a positive integer less than N. In addition, the channel selection circuit 120 can be used to output M signals CK on the M clock channels respectively₀-CK_(M-1)(i.e., M clock signals). The remaining (N-M) channels may be referred to as (N-M) data channels, respectively. At least one data in the (N-M) data channelsThe channel may carry a data signal transmitted from the transmission side TS. In this embodiment, the M clock signals may be combined with (N-M) data signals (i.e., the (N-M) signals DA on the (N-M) lanes₀-DA_(N-M-1)) Forward so that each data channel can carry a data signal. It is noted that the channel selection circuit 120 can select N channels LA [0]]-LA[N-1]Is selected as the clock channel. N channels LA [0]-LA[N-1]Each channel in (1) can be commonly used for a clock channel and a data channel.

In this embodiment, the channel selection circuit 120 includes, but is not limited to, a plurality of selection stages (selection stages) 122 and 124. The select stage 122 has an input side S1 and an output side S2. Input side S1 is coupled to multi-channel interface 114. The select stage 122 is used for selecting M signals CK on the M clock channels₀-CK_(M-1)The input side S1 is coupled to the output side S2. The selection stage 124 is disposed at the output side S2 and N sampling circuits RX [0]]-RX[N-1]For transmitting M signals CK₀-CK_(M-1)Is coupled to N sampling circuits RX [0]]-RX[N-1]Of the sampling circuit. For example, the select stage 122 may be implemented as an N-to-M multiplexer (N-to-M multiplexer) that may couple N channels LA [0]]-LA[N-1]The M channels are coupled to the output side S2. The pick stage 124 may be implemented as M Clock Trees (CT) in which each clock tree may be used to output a clock signal (i.e., M signals CK₀-CK_(M-1)One of which) to more than one sampling circuit.

N sampling circuits RX [0]]-RX[N-1]The interface 114 and the channel selection circuit 120 are coupled to perform data sampling according to the clock information and the data information transmitted from the transmitting side TS. In this embodiment, N sampling circuits RX [0]]-RX[N-1]Each sampling circuit in the M clock channels is used for receiving M signals CK on the M clock channels₀-CK_(M-1)One of which. In addition, N sampling circuits RX [0]]-RX[N-1]The (N-M) sampling circuits are respectively coupled to the (N-M) data channels for receiving (N-M) signals DA on the (N-M) data channels₀-DA_(N-M-1). Each of the (N-M) sampling circuits is configured to sample the signal CK according to M signals₀-CK_(M-1)One of them, for (N-M) signals DA₀-DA_(N-M-1)One of which is sampled.

For example, but not limiting to the application, N sampling circuits RX [0]]-RX[N-1]Each sampling circuit in (a) may comprise a clock input terminal C_INAnd a data input terminal D_IN. Each sampling circuit using an input to a corresponding clock input terminal C_INTo the corresponding data input terminal D_INThe signal of (a) is sampled. By mixing N channels LA [0]]-LA[N-1]M channels in the circuit are coupled to N sampling circuits RX [0]]-RX[N-1]N clock input terminals C_INThe channel selection circuit 120 can select N channels LA [0]]-LA[N-1]The M channels in (a) are selected as the M clock channels. Each of the remaining (N-M) channels may be coupled to a data input terminal D_INIs not coupled to the N clock input terminals C_INThereby acting as a data channel. Thus, when each sampling circuit passes through the data input D it includes_INA clock input terminal C coupled to a data channel and included therethrough_INWhen coupled to a clock channel, the sampling circuit can sample the signal on the data channel by using the signal on the clock channel. In some embodiments, a clock channel may be coupled to the N clock input terminals C_INSuch that multiple sampling circuits may sample data according to the same clock signal.

N sampling circuits RX [0]]-RX[N-1]The output sampling result SR includes clock information and data information, which may be passed to an output circuit 140, including other functional blocks (not shown in fig. 1), of the integrated circuit 110 for further processing. For example, coupled to M signals CK simultaneously₀-CK_(M-1)One of which is associated with (N-M) signals DA₀-DA_(N-M-1)A sampling circuit for one of the signals may output a data signal which may be part of the sampling result SR. Coupled to the M signals CK₀-CK_(M-1)One of which is not coupled to the (N-M) signals DA₀-DA_(N-M-1)A sampling circuit ofA clock signal is output which can be another part of the sampling result SR. The output circuit 140 outputs M clock signals and (N-M) data signals according to the sampling result SR. In some embodiments, output circuit 140 may include an deserializer block (deserializer block). Each of the M clock signals and the (N-M) data signals output from the output circuit 140 may be a multi-bit parallel output signal (multi-bit parallel output signal).

In some embodiments, the transmitter may provide information to indicate which channel should be used as a clock channel. Based on the information provided by the transmitter, the receiver 104 may configure/configure the channel selection circuit 120 to select the appropriate channel as the clock channel. The receiver 104 may properly use the signals on the clock lanes to process the signals on one or more data lanes.

In some embodiments, the transmitter may generate a clock signal by repeating a particular bit pattern (bit pattern) to indicate which channel on the transmit side RS should be used as a clock channel. For example, the transmitter may repeatedly transmit a one-bit pattern "01", such as "01010101", as a clock signal. The receiver 104 can identify which channel can be used as the clock channel by checking whether a bit stream (bit stream) received by a channel has a repetitive bit pattern. That is, the receiver 104 configures/configures the channel selection circuit 120 according to the detection result of a predetermined repetitive bit pattern.

In some embodiments, a system application (not shown in FIG. 1) associated with the receiver 104 may determine which channel of the multi-channel interface 104 should be a clock channel. Based on instructions sent by the system application, the receiver 104 may configure/configure the channel selection circuit 120 to select the appropriate channel as the clock channel.

It should be noted that the foregoing is illustrative only and is not intended to limit the scope of the present application. In some embodiments, the channel selection circuit 120 shown in FIG. 1 may be implemented with a single selection stage or with more than two selection stages without departing from the scope of the present application. In some embodiments, at least one of the N sampling circuits RX [0] -RX [ N-1] shown in FIG. 1 may be implemented using a sampling circuit having more than one data output.

The physical layer 108 of the receiving side RS can support different channel configurations of the transmitting side TS by at least one channel that can be used interchangeably between the clock channel and the data channel. To further illustrate the lane interchange scheme (lane interchange scheme) of the receiving side RS, some embodiments of the lane configuration of the transmitting side TS are provided below. Those skilled in the art will appreciate that the channel interchange scheme of the receiving side RS can support other channel configurations of the transmitting side TS without departing from the scope of the present application.

Fig. 2A-2C are schematic diagrams of different modes of the receiver 104 shown in fig. 1 according to some embodiments of the present application. The receiver 104 can operate in different modes OP1-OP3 according to different channel configurations of the transmission side TS, respectively. In mode OP1 shown in FIG. 2A, receiver 104 may be configured to receive clock information and data information provided by a single transmitter. For illustrative purposes, the single transmitter may be represented by transmitter TX [0] shown in FIG. 1]To represent. Transmitter TX [0]]Multi-channel interface TF [0]]Includes multiple channels L0[ 0]]-L0[P]And P is a positive integer. Transmitter TX [0]]For connecting the passage L0[ P ]]Clock signal C0 on along with P lanes L0[ 0]]-L0[P-1]P data signals D0₀-D0_(P-1)And output together.

Receiver 104 is used to convert N channels LA [0]]-LA[N-1]One of the lanes is selected as a clock lane (i.e., M ═ 1) to receive clock signal C0 through communication link 106. P channels of the remaining (N-1) channels can be used as P data channels to receive P data signals D0₀-D0_(P-1). In this embodiment, the slave transmitter TX [0]]The sum of the number of data signals transmitted and the number of clock signals may equal the number of lanes of the multi-lane interface 114 (i.e., P +1 ═ N). Thus, N channels LA [0]-LA[N-1]Can be used to receive the TX [0] on the transmission side]The signal information provided. Receiver 104 may convert channel LA [ N-1]](i.e., channel L0[ P ]]The path of the clock signal C0 input) is selected as the clock pathAnd (4) performing track making. The remaining (N-1) channels LA [0]-LA[N-2]Can be used as (N-1) data channels to receive P data signals D0₀-D0_(P-1)。

In the mode OP2 shown in fig. 2B, the receiver 104 may be configured to receive clock information and data information provided by a plurality of transmitters, wherein a plurality of channels of the transmitting side TS may be used as a plurality of clock channels to carry a plurality of clock signals. For example, when operating in a forking mode (bifurcating mode), the physical layer 108 may be split into multiple physical layers that are different from each other to support the K transmitters TX [0] shown in FIG. 1]-TX[K-1]A plurality of transmitters. For convenience of illustration, in this embodiment, the plurality of transmitters may be composed of two transmitters TX [1]]And TX [2]]To represent. Transmitter TX [1]]Multi-channel interface TF [1]]Includes multiple channels L1[ 0]]-L0[Q]And Q is a positive integer. Transmitter TX [1]]For connecting a passage L1[ Q]Clock signal C1 on along with Q channels L1[ 0]]-L1[Q-1]Q data signals D1₀-D1_(Q-1)And output together. Transmitter TX [2]]Multi-channel interface TF [2]]Includes multiple channels L2[ 0]]-L2[R]And R is a positive integer. Transmitter TX [2]]For connecting the passage L2[ R ]]Clock signal C2 on along with R channels L2[ 0]]-L2[R-1]R data signals D2₀-D2_(R-1)And output together. Since both channels of the transmitting side TS are used as clock channels in the mode OP2, the channel configuration of the transmitting side TS in the mode OP2 is different from the channel configuration of the transmitting side TS in the mode OP1 (which uses a single channel as a clock channel).

In response to mode OP2, receiver 104 may convert N lanes LA [0]]-LA[N-1]Two clock channels (i.e., M ═ 2) are selected to receive the clock signals C1 and C2 transmitted by the transmitting side TS. The (Q + R) channels of the remaining (N-2) channels can be used as the (Q + R) data channels to receive the plurality of data signals D1₀-D1_(Q-1)And D2₀-D2_(R-1). In this embodiment, a plurality of transmitters TX [1]]And TX [2]]The sum of the number of data signals and the number of clock signals transmitted may be equal to the number of lanes of the multi-lane interface 114 (i.e., Q + R +2 ═ N). Thus, N lanes LA [0]]-LA[N-1]Can be used to receive a plurality of transmitters TX [1]]And TX [2]]The signal information provided. Is connected withThe receiver 104 can combine two channels LA [ J ]]And LA [ N-1](i.e., the paths on which the plurality of clock signals C1 and C2 are input) are selected as two clock paths. J is an integer between 0 and N-2. The remaining (N-2) channels may be used as (N-2) data channels to receive a plurality of data signals D1₀-D1_(Q-1)And D2₀-D2_(R-1). Due to the passage LA [ J]Can be used as a data channel in the mode OP1 and as a clock channel in the mode OP2, and thus the integrated circuit 110 can support not only a single transmitter but also multiple transmitters.

In some embodiments, one or more transmitters have channels that are interchangeably used between the data channel and the clock channel to provide different channel configurations at the transmit side TS. For example, in mode OP3 shown in FIG. 2C, receiver 104 may be used to receive transmitter TX [0]]Clock information and data information provided, wherein the transmitter TX [0]]Can be passed from passage L0[0]Transmitting a clock signal C0, and from P lanes L0[ 1]]-L0[P]Transmitting P data signals D0₀-D0_(P-1). Compared to mode OP1, transmitter TX [0]]Signals transmitted on the clock channel and on the data channel may be caused to interchange with one another. Thus, the channel L0[ 0] as a data channel in the mode OP1]Channel L0[ P ] which can be used as a clock channel in mode OP3 and as a clock channel in mode OP1]Can be used as a data channel in the mode OP 3. Receiver 140 may convert channel LA [0]]The clock channel is selected to receive the clock signal C0. The remaining (N-1) channels LA [1]]-LA[N-1]The P channels in the group can be used as P data channels to receive P data signals D0₀-D0_(P-1). By passing a channel LA [0]]And channel LA [ N-1]]For use interchangeably between data and clock channels, respectively, integrated circuit 110 may support a transmitter TX [0] capable of using clock and data channels interchangeably]。

To facilitate an understanding of the present application, some embodiments are provided below to further illustrate a clock forwarding interface receiver that employs a lane interchange scheme. Those skilled in the art will appreciate that other embodiments of the channel interchange scheme described based on the integrated circuit 110 or the receiver 104 shown in fig. 1 are within the scope of the present application in keeping with the spirit of the present application.

FIG. 3 is a schematic diagram of an implementation of the integrated circuit 110 shown in FIG. 1 according to some embodiments of the present application. The integrated circuit 310 is disposed in a physical layer of the receiver 300, such as a physical media connection layer, to receive clock information and data information transmitted by one or more transmitters on the transmit side. Integrated circuit 310 may be implemented as integrated circuit 110 of fig. 1 (which includes six channels, N-6, that may be commonly used for a clock channel and a data channel). In this embodiment, the integrated circuit 310 may include the sampling circuits RX [0] -RX [5], a multi-channel interface 314, and a channel selection circuit 320 shown in FIG. 1. The multi-channel interface 314 and the channel selection circuit 320 may be implemented as the multi-channel interface 114 and the channel selection circuit 120 shown in FIG. 1, respectively.

In this embodiment, each of the multiple channels LA [0] -LA [5] of the multi-channel interface 314 may be implemented using a two-wire channel (two-wire lane). The two-wire path is a differential path (differential lane) including a pair of signal pins (a pair of signal pins) and an amplifier. In some embodiments, each of the multiple lanes LA [0] -LA [5] may be implemented using other types of lanes, such as a single lane or a lane having more than two lines, without departing from the scope of the present application.

The channel selection circuit 320 is used to select multiple channels LA [0]]-LA[5]Is selected as one or more clock channels. The channel selection circuit 320 may include a plurality of selection stages 322 and 324, which may be implemented as the plurality of selection stages 122 and 124, respectively, shown in FIG. 1. In this embodiment, the select stage 322 may couple one or two channels to the select stage 324 in response to the mode of the integrated circuit 310. The selection stage 322 includes, but is not limited to, a plurality of channel selection units 322.0 and 322.1. The channel selection unit 322.0 selects a signal SEL according to a clock₀₀Multiple channels LA [0]]-LA[2]The input side S01 is coupled to the output side S02. The channel selection unit 322.1 is used for selecting a signal SEL according to a clock₀₁Multiple channels LA [3]]-LA[5]The input side S11 is coupled to the output side S12.

The select stage 324 may distribute signals on the channels selected by the select stage 322 to more than one channelA sampling circuit. The selection stage 324 includes, but is not limited to, a plurality of channel selection units 324.0-324.5. The plurality of channel selection units 324.0-324.5 may each select a channel according to a corresponding clock selection signal (i.e., a plurality of clock selection signals SEL)₁₀-SEL₁₅One of them) a plurality of output sides S02 and S12 are coupled to respective sampling circuits. Selecting signals SEL with respect to a plurality of clocks₀₀、SEL₀₁And SEL₁₀-SEL₁₅The description of which will be described later.

Multiple sampling circuits RX [0]]-RX[5]Respective clock input terminal C_INCoupled to respective output terminals of the plurality of channel selection units 324.0-324.5. Multiple sampling circuits RX [0]]-RX[5]Respective data input terminal D_INCoupled to multiple channels LA [0] respectively]-LA[5]. In this embodiment, a plurality of sampling circuits RX [0]]-RX[5]Each sampling circuit in (a) may be implemented with a flip-flop (such as a D-type flip-flop) to sample data. Those skilled in the art will appreciate that multiple sampling circuits RX 0]-RX[5]May be implemented using other types of sampling circuits without departing from the scope of this application.

Fig. 4A-4C are schematic diagrams illustrating operations of the integrated circuit 310 of fig. 3 according to some embodiments of the present application. In the embodiment shown in FIGS. 4A and 4B, the integrated circuit 310 operates in a mode similar to the mode OP1/OP3 shown in FIGS. 2A/2C to receive a single clock signal from the multi-channel interface 314. The channel selection circuit 320 may select one of the plurality of channels LA [0] -LA [5] as a clock channel to receive the clock signal. The channel selection circuit 320 is used to couple the signal (i.e., clock signal) on the clock channel to each of the plurality of sampling circuits RX [0] -RX [5 ]. In the embodiment shown in FIG. 4C, the integrated circuit 310 operates in a mode similar to the mode OP2 shown in FIG. 2B to receive a plurality of clock signals from the multi-channel interface 314. The channel selection circuit 320 may select two of the plurality of channels LA [0] -LA [5] as two clock channels to receive the plurality of clock signals. The channel selection circuit 320 is used to couple the signal on each clock channel to one or more of the plurality of sampling circuits RX [0] -RX [5 ].

Referring first to FIG. 4A, an integrated circuit 310 may support a "5D 1C" lane configuration in which a clock signal 5D _ CLK is input to a plurality of lanes LA [0]]-LA[2]One of the channels (in this embodiment, to input into channel LA [0]]For illustration purposes). Five data signals 5D₀-5D₄Input to the remaining five channels. The channel selection unit 322.0 selects a signal SEL according to a clock₀₀Will channel LA [0]Coupled to output side S02 to connect channel LA [0]]And is selected as the clock channel. Multiple channels LA [1]And LA 2]Not coupled to the output side S02. In addition, each of the plurality of channel selecting units 324.0-324.5 may couple the output side S02 of the channel selecting unit 322.0 to a corresponding sampling circuit according to a corresponding clock selecting signal. Thus, the clock signal 5D _ CLK may be transferred to a plurality of sampling circuits RX 0]-RX[5]Respective clock input terminal C_IN. Coupled to multiple channels LA [1 respectively]-LA[5]Multiple sampling circuits RX 1]-RX[5]Multiple data signals 5D can be generated according to the clock signal 5D _ CLK₀-5D₄Sampling is performed.

Referring to FIG. 4B, the integrated circuit 310 may support a "5D 1C" lane configuration in which a clock signal 5D _ CLK is input to a plurality of lanes LA [3]]-LA[5]One of the channels (in this embodiment, for input to channel LA [3]]For illustration purposes). A plurality of data signals 5D₀-5D₄Input to the remaining five channels. The channel selection unit 322.1 selects the SEL according to the clock₀₁Will channel LA [3]Coupled to output side S12 to connect channel LA [3]]And is selected as the clock channel. Each of the plurality of channel select units 324.0-324.5 may couple the output side S12 of the channel select unit 322.1 to a corresponding sampling circuit. Therefore, the channels LA [0] are coupled to]-LA[2]、LA[4]And LA [5]]Multiple sampling circuits RX [0]]-RX[2]、RX[4]And RX [5]]Multiple data signals 5D can be generated according to the clock signal 5D _ CLK₀-5D₄Sampling is performed.

Referring to FIG. 4C, the integrated circuit 310 may serve as two circuit interfaces, both of which may support a "2D 1C" lane configuration (two lanes for data and one lane for clock). In this embodiment, a clock signal 2D _ CLK0 is input to multipleStripe channel LA [0]-LA[2]One of the channels, such as channel LA [0]]. Correlated data signal 2D₀₀And 2D₀₁The remaining two channels may be input. In addition, a clock signal 2D _ CLK1 is input to a plurality of channels LA [3]]-LA[5]One of the passages, such as passage LA [3]]. Correlated data signal 2D₁₀And 2D₁₁The remaining two channels may be input.

The channel selection unit 322.0 selects a signal SEL according to a clock₀₀Will channel LA [0]Coupled to the output side S02. Each of the plurality of channel select units 324.0-324.2 is configured to couple the output side S02 to a corresponding sampling circuit according to a corresponding clock select signal. Therefore, are respectively coupled to a plurality of channels LA [1]]And LA 2]Multiple sampling circuits RX 1]And RX [2]]Multiple data signals 2D according to the clock signal 2D _ CLK0₀₀And 2D₀₁Sampling is performed. Similarly, the channel selection unit 322.1 is used to select the SEL according to the clock signal₀₁Will channel LA [3]Coupled to the output side S12. Each of the plurality of channel selection units 324.3-324.5 is configured to couple the output side S12 to a corresponding sampling circuit according to a corresponding clock selection signal. Therefore, are respectively coupled to a plurality of channels LA [4]]And LA [5]]Multiple sampling circuits RX 4]And RX [5]]Multiple data signals 2D according to the clock signal 2D _ CLK1₁₀And 2D₁₁Sampling is performed. Due to multiple clock selection signals SEL₁₀-SEL₁₂Each clock selection signal in (1) may be different from the signal level/value of the plurality of clock selection signals SEL₁₃-SEL₁₅So that the plurality of channel selection units 324.0-324.5 can distribute different clock signals 2D _ CLK0 and 2D _ CLK1 to the plurality of sampling circuits RX 0]-RX[5]。

Through the selection operations described with reference to fig. 4A and 4B, the selection stage 322 and the selection stage 324 shown in fig. 3 can be used as a 6-to-1multiplexer (6-to-1multiplexer) and a clock tree, respectively, to support the "5D 1C" channel configuration. Furthermore, the selection stage 322 shown in fig. 3 can be used as two 3-to-1 multiplexers (3-to-1 multiplexers) and the selection stage 324 shown in fig. 3 can be used as two clock trees by the selection operation described with reference to fig. 4C, thereby supporting the "2D 1C" channel configuration in the fork mode. Thus, the channel selection circuit 320 shown in FIG. 3 may support one or more transmitters by operating as 6-to-M multiplexers (6-to-M multiplexers) and M clock trees, where M may be equal to 1 or 2 (depending on the mode of the integrated circuit 310).

It should be noted that the circuit structure of the plurality of selection stages 322 and 324 shown in fig. 3 is only for the purpose of convenience of illustration and is not intended to limit the scope of the present application. In some embodiments, the selection stage 322 may be implemented by other circuit structures to provide operation of a multiplexer. In some embodiments, the pick stage 324 may be implemented by other circuit structures to construct one or more clock trees. In some embodiments, the signal (such as a clock signal) on each selected clock channel may not be coupled to the data input D of each sampling circuit_IN. For example, when the channel LA [0] is shown in FIG. 3]When selected as the clock channel, channel LA [0]]Can be not coupled to the data input end D of each sampling circuit_IN。

In some embodiments, a plurality of clock selection signals SEL₁₀-SEL₁₂May be implemented using the same clock select signal or may have the same signal value. In some embodiments, a plurality of clock selection signals SEL₁₃-SEL₁₅May be implemented using the same clock select signal or may have the same signal value. Such design modifications and variations are intended to fall within the scope of the present application following the spirit of the present application.

Fig. 5A-5C are schematic diagrams of other implementations of the integrated circuit 110 shown in fig. 1 according to some embodiments of the present application. Each of the plurality of integrated circuits 510A-510C shown in fig. 5A-5C may be implemented as an embodiment of integrated circuit 110 shown in fig. 1 (which includes six channels that may be commonly used for a clock channel and a data channel, N ═ 6). In these embodiments, the channel selection circuit 120 shown in fig. 1 may be implemented by using different clock tree groups (clock tree groups) to support different channel configurations on the transmission side. Each clock tree group comprises at least one clock tree circuit, and each clock tree circuit comprises a multiplexer and a clock tree.

Please first refer to fig. 5A. The structure of integrated circuit 510A is similar/identical to the structure of integrated circuit 310 shown in fig. 3, except for channel selection circuit 520A. The circuit operation provided by channel selection circuit 520A may be similar/identical to the circuit operation of channel selection circuit 320 described with reference to FIGS. 4A/4B. In this embodiment, the channel selection circuit 520A may be implemented by using a clock tree group G1. The clock tree group G1 has a clock tree circuit that includes a multiplexer 522A (i.e., a 6-to-1multiplexer) and a clock tree 524A. The multiplexer 522A selects the signal SEL according to a clock_AMultiple channels LA [0]]-LA[5]One of the channels is selected as a clock channel, so that from an output terminal T_5DAnd outputting the signal on the selected channel. The clock tree 524A may couple the output terminal T_5DThe signal on is distributed to a plurality of sampling circuits RX 0]-RX[5]Each of the sampling circuits in (1). Please note that the circuit structure of the selection stage 322 shown in FIG. 4A/4B can be implemented as the multiplexer 522A. Additionally, or alternatively, the circuit structure of the pick stage 324 shown in fig. 4A/4B may be implemented as a clock tree 524A. Since the details of the operation of the channel selection circuit 520A shown in fig. 5A in the channel configuration of "5D 1C" can be understood by those skilled in the art after reading the paragraphs associated with fig. 3, fig. 4A and fig. 4B, further description of the channel selection will not be repeated herein.

Please refer to fig. 5B. The structure of integrated circuit 510B is similar/identical to the structure of integrated circuit 310 shown in fig. 3, except for channel selection circuit 520B. The circuit operation provided by the channel selection circuit 520B may be similar/identical to the circuit operation of the channel selection circuit 320 described with reference to fig. 4C. In this embodiment, the channel selection circuit 520B may be implemented by using a clock tree group G2. The clock tree group G2 has two clock tree circuits, one including a multiplexer 522b.0 and a clock tree 524b.0, and the other including a multiplexer 522b.1 and a clock tree 524 b.1. The multiplexer 522B.0 (i.e., 3-to-1multiplexer) selects the signal SEL according to a clock_B0Multiple channels LA [0]]-LA[2]One of the channels is selected as a clock channel. Clock tree 524B.0 may couple output terminal T_2D0Signal onDistributed to a plurality of sampling circuits RX [0]]-RX[2]Each of the sampling circuits in (1). The multiplexer 522B.1 (i.e., 3-to-1multiplexer) selects the signal SEL according to a clock_B1Multiple channels LA [3]]-LA[5]One of the channels is selected as a clock channel. Clock tree 524B.1 may have an output T_2D1The signal on is distributed to a plurality of sampling circuits RX 3]-RX[5]Each of the sampling circuits in (1). It is noted that the circuit configuration of the selection stage 322 shown in FIG. 4C can be implemented as a plurality of multiplexers 522B.0 and 522 B.1. Additionally, or alternatively, the circuit structure of the pick stage 324 shown in fig. 4C may be implemented as a plurality of clock trees 524b.0 and 524 b.1. Since the details of the operation of the channel selection circuit 520B in the "2D 1C" channel configuration shown in fig. 5B can be understood by those skilled in the art after reading the paragraphs associated with fig. 3 and fig. 4C, further description of the channel selection will not be repeated herein.

Please refer to fig. 5C. The structure of integrated circuit 510C is similar/identical to the structure of integrated circuit 310 shown in fig. 3, except for channel selection circuit 520C. The channel selection circuit 520C may be implemented using a clock tree group G3. The clock tree group G3 has three clock tree circuits, and thus can support a transmission side where three clock lanes and their associated three data lanes are provided. In this embodiment, the channel selection circuit 520C includes a plurality of multiplexers 522C.0-522C.2 (i.e., a plurality of 2-to-1 multiplexers) and a plurality of clock trees 524C.0-524 C.2. The multiplexer 522C.0 selects the SEL signal according to a clock_C0Multiple channels LA [0]]And LA [1]]One of the channels is selected as a clock channel. The multiplexer 522C.1 can select the signal SEL according to a clock_C1Multiple channels LA 2]And LA [3]]One of the channels is selected as a clock channel. The multiplexer 522C.2 can select the signal SEL according to a clock_C2Multiple channels LA [4]]And LA [5]]One of the channels is selected as a clock channel. Clock tree 524C.0 may have output T_1D0The signal on is distributed to a plurality of sampling circuits RX 0]And RX [1]]Each of the sampling circuits in (1). Clock tree 524c.1 may have an output T_1D1The signal on is distributed to a plurality of sampling circuits RX 2]And RX [3]]Each of the sampling circuits in (1). Clock tree 524c.2 may have an output T_1D2The signal on is distributed to a plurality of sampling circuits RX 4]And RX 25]Each of the sampling circuits in (1).

For example, multiplexers 522C.0-522C.2 may select lanes LA [0], LA [2], and LA [4] as clock lanes. Thus, sampling circuit RX [1] may sample the signal on channel LA [1] from the signal on channel LA [0 ]. Sampling circuit RX [3] may sample the signal on channel LA [3] based on the signal on channel LA [2 ]. Sampling circuit RX [5] may sample the signal on channel LA [5] based on the signal on channel LA [4 ]. The integrated circuit 510C may be divided into three interfaces, each of which may support a "1D 1C" lane configuration (one lane may be a clock lane and another lane may be a data lane).

FIG. 6 is a schematic diagram of another implementation of the integrated circuit 110 shown in FIG. 1 in some embodiments of the present application. Integrated circuit 610 may be implemented as integrated circuit 110 of fig. 1 (which includes six channels, N6, that may be commonly used for a clock channel and a data channel). In this embodiment, the integrated circuit 610 may employ the plurality of clock tree groups G1-G3 shown in FIGS. 5A-5C to support different channel configurations. The integrated circuit 610 includes a channel selection circuit 620, as well as the multi-channel interface 314 and the plurality of sampling circuits RX [0] -RX [5] shown in FIG. 3. The channel selection circuit 620 may be implemented as the channel selection circuit 120 shown in FIG. 1 and may include a plurality of selection stages 622 and 624.

The selection stage 622 may include the multiplexer 522A of the clock tree group G1 shown in FIG. 5A, the multiplexers 522B.0 and 522B.1 of the clock tree group G2 shown in FIG. 5B, and the multiplexers 522C.0-522C.2 of the clock tree group G3 shown in FIG. 5C. The selection stage 624 may include a plurality of multiplexers 624.0-624.5. The multiplexer 624.0 is used for connecting a plurality of output terminals T_5D、T_2D0And T_1D0One output terminal of which is coupled to a sampling circuit RX [0]]Clock input terminal C of_IN. The multiplexer 624.1 is used to couple a plurality of output terminals T_5D、T_2D0And T_1D0One output terminal of which is coupled to a sampling circuit RX [1]]Clock input terminal C of_IN. The multiplexer 624.2 is used to couple a plurality of output terminals T_5D、T_2D0And T_1D1One output terminal of which is coupled to a sampling circuit RX 2]Clock input terminal C of_IN. The multiplexer 624.3 is used to couple a plurality of output terminals T_5D、T_2D1And T_1D1One output terminal of which is coupled to a sampling circuit RX [3]]Clock input terminal C of_IN. The multiplexer 624.4 is used to couple a plurality of output terminals T_5D、T_2D1And T_1D2One output terminal of which is coupled to a sampling circuit RX 4]Clock input terminal C of_IN. Multiplexer 624.5 for coupling a plurality of output terminals T_5D、T_2D1And T_1D2One output terminal of which is coupled to a sampling circuit RX [5]]Clock input terminal C of_IN。

In a mode in which the integrated circuit 610 is configured to support a "5D 1C" channel configuration, each of the plurality of multiplexers 624.0-624.5 is configured to couple the output terminal T_5DCoupled to the corresponding sampling circuit to enable the output terminal T_5DThe clock signal 5D _ CLK above may be distributed to the sampling circuits. For example, the multiplexer 522A selects the signal SEL according to the clock_AWill channel LA [0]Is coupled to the output end T_5D. The remaining plurality of channels LA [1]]-LA[5]Can be used as a data channel. Coupled to multiple channels LA [1 respectively]-LA[5]Multiple sampling circuits RX 1]-RX[5]The data sampling operation may be performed according to the clock signal 5D _ CLK. Please note that the multiplexers 624.0-624.5 capable of being a clock tree to distribute the clock signal 5D _ CLK can be used to implement the clock tree 524A in the group G1 of the clock tree shown in FIG. 5A.

In another mode of the integrated circuit 610 for supporting a "2D 1C" branch channel configuration (lane configurations with bifurcations), each of the multiplexers 624.0-624.2 is used to configure the output T_2D0Coupled to the corresponding sampling circuit to enable the output terminal T_2D0The clock signal 2D _ CLK0 on may be distributed to a plurality of sampling circuits RX 0]-RX[2]Each of the sampling circuits in (1). Each of the multiplexers 624.3-624.5 is used to connect the output terminal T_2D1Coupled to the corresponding sampling circuit to enable the output terminal T_2D1The clock signal 2D _ CLK1 on may be distributed to a plurality of sampling circuits RX 3]-RX[5]Each of the sampling circuits in (1). Multiple multiplexers 624.0-624.5 may be used to implement multiple clock trees 524b.0 and 524b.1 in the group of clock trees G2 shown in fig. 5B. Thus, a plurality of sampling circuits RX [0]]-RX[5]Two groups of sampling circuits can be divided. The physical layer in which the integrated circuit 610 resides is operable as two separate physical layers, one of which includes a plurality of channels LA [0]]-LA[2]And a plurality of sampling circuits RX [0]]-RX[2]The other physical layer includes multiple channels LA [3]]-LA[5]And a plurality of sampling circuits RX 3]-RX[5]。

In another mode of the integrated circuit 610 for supporting a "1D 1C" branch channel configuration, each of the multiplexers 624.0 and 624.1 is configured to couple the output terminal T to a corresponding one of the multiplexers_1D0Coupled to the corresponding sampling circuit to enable the output terminal T_1D0The clock signal 1D _ CLK0 on may be distributed to a plurality of sampling circuits RX 0]And RX [1]]Each of the sampling circuits in (1). Similarly, each of the multiplexers 624.2 and 624.3 is used to connect the output terminal T_1D1Coupled to the corresponding sampling circuit to enable the output terminal T_1D1The clock signal 1D _ CLK1 on may be distributed to a plurality of sampling circuits RX 2]And RX [3]]Each of the sampling circuits in (1). Each of the plurality of multiplexers 624.4 and 624.5 is configured to couple an output terminal T to a respective one of the plurality of multiplexers_1D2Coupled to the corresponding sampling circuit to enable the output terminal T_1D2The clock signal 1D _ CLK2 on may be distributed to a plurality of sampling circuits RX [4]]And RX [5]]Each of the sampling circuits in (1). Multiple multiplexers 624.0-624.5 may be used to implement multiple clock trees 524C.0-524c.2 in the clock tree group G3 shown in fig. 5C. Thus, a plurality of sampling circuits RX [0]]-RX[5]Three groups of sampling circuits can be used. The physical layer on which integrated circuit 610 resides may operate as three separate physical layers to support three transmitters.

The selection stage 622 may operate as 6 pairs of M multiplexers with a plurality of multiplexers 522A, 522b.0, 522b.1, and 522C.0-522c.2, where M may equal 1, 2, or 3 (depending on the mode of the integrated circuit 610). Furthermore, the selection stage 624 may be operable through a plurality of multiplexers 624.0-624.5 into M clock trees, where M may be equal to 1, 2, or 3 (depending on the mode of the integrated circuit 610). Thus, integrated circuit 610 may divide the lanes LA [0] -LA [5] into one or more lane groups (groups of lanes), where each lane group includes a clock lane and a data lane to support one or more transmitters.

The circuit configuration and operation described above with reference to figure 6 are for convenience of description only,and are not intended to limit the scope of the present application. In some embodiments, integrated circuit 610 may operate in a branching mode that supports both a "3D 1C" channel configuration and a "1D 1C" channel configuration. For example, a plurality of multiplexers 624.0-624.3 may be used to connect the output terminals T_5DCoupled to the corresponding sampling circuit to enable the output terminal T_5DThe clock signal 5D _ CLK on may be distributed to a plurality of sampling circuits RX 0]-RX[3]Each of the sampling circuits in (1). Each of the plurality of multiplexers 624.4 and 624.5 is configured to couple an output terminal T to a respective one of the plurality of multiplexers_1D2Coupled to the corresponding sampling circuit to enable the output terminal T_1D2The clock signal 1D _ CLK2 on may be distributed to a plurality of sampling circuits RX 4]And RX [5]]Each of the sampling circuits in (1). Thus, the physical layer on which integrated circuit 610 resides may operate as two separate physical layers to support two transmitters having different numbers of data lanes.

In some embodiments, it is possible to not use a channel as a data channel when data transmission is performed. For example, when used to support a "5D 1C" lane configuration, integrated circuit 610 may use five or fewer data lanes to receive data information communicated by the transmit side. The number of data channels used may depend on the number of data signals communicated to the multi-channel interface 314.

In some embodiments, the selection stage 622 may be implemented using other multiplexer circuits to select one or more channels in response to the mode of the integrated circuit 610. In some embodiments, the select stage 624 may be implemented using other clock tree structures to distribute one or more clock signals in response to the mode of the integrated circuit 610. Such design modifications and variations are intended to fall within the scope of the present application following the spirit of the present application.

FIG. 7 is a schematic diagram of another implementation of the integrated circuit 110 shown in FIG. 1 in some embodiments of the present application. Integrated circuit 710 may be implemented as integrated circuit 110 of fig. 1 (which includes six channels, N6, which may be commonly used for a clock channel and a data channel). In this embodiment, the integrated circuit 710 may be disposed at a physical media connection layer in the physical layer to perform serial-to-parallel conversion (serial-to-parallel conversion).

The integrated circuit 710 includes a channel selection circuit 720, a plurality of serial-to-parallel converters (hereinafter "S2P converters") 730.0-730.5, and the multi-channel interface 314 shown in FIG. 3. The channel selection circuit 720 may be implemented as the channel selection circuit 120 of FIG. 1 and may include a plurality of selection stages 722 and 724. The selection stage 722 may include a plurality of multiplexers 722.0 and 722.1. The multiplexer 722.0 is used for selecting the SEL signal according to a clock₇₀Multiple channels LA [0]]-LA[5]Is coupled to an output terminal T₇₀. The multiplexer 722.0 selects the SEL signal according to a clock₇₁Multiple channels LA [0]]-LA[5]Is coupled to an output terminal T₇₁. The selection stage 724 may be implemented to include a multiplexer 724.0 that selects the signal SEL according to a clock₇₂A plurality of output terminals T₇₀And T₇₁Is coupled to an output terminal T₇₂。

Each S2P converter of the S2P converters 730.0-730.5 is configured to output a multi-bit parallel output signal. The multi-bit parallel output signal may be a parallel data signal (parallel data signal), a byte data signal (byte data signal), a parallel clock signal (parallel clock signal), or a byte clock signal. In this embodiment, each S2P converter includes a sampling circuit and a deserializer (deserializer) (i.e., one of the sampling circuits RX [0] -RX [5] and one of the deserializers DS [0] -DS [5] shown in FIG. 3). The plurality of deserializers DS [0] -DS [5] may be provided as an output circuit 740 that may output one or more clock signals based on the sampling results SR of the plurality of sampling circuits RX [0] -RX [5 ].

In the mode of the integrated circuit 710 for supporting the "5D 1C" channel configuration, the multiplexer 724.0 is used to couple the output terminal T₇₀Is coupled to the output end T₇₂. When the multiplexer 722.0 connects multiple channels LA [0]]-LA[5]When one of the channels is selected as a clock channel, the signal on the clock channel can be coupled to the output end T₇₀And is distributed to a plurality of sampling circuits RX [0]]-RX[5]Respective clock input terminal C_IN. For example, multiplexer 722.0 can couple channel LA [0]]And is selected as the clock channel. Multiple sampling circuits RX 1]-RX[5]Can be based on the same clock signal (i.e., channel LA [0]]The above) to sample the data. Deserializer DS [0]]A clock signal (i.e., a parallel clock signal) may be output according to the sampling result SR. Note that in this mode, multiple multiplexers 722.0 and 724.0 can be used as an embodiment of the clock tree group G1 shown in fig. 5A.

In the mode of the integrated circuit 710 for supporting the "2D 1C" branch path configuration, the multiplexer 724.0 is used to couple the output terminal T₇₁Is coupled to the output end T₇₂. When the multiplexer 722.0 connects multiple channels LA [0]]-LA[5]When one of the channels is selected as a clock channel, the multiplexer 722.1 can connect multiple channels LA [0]]-LA[5]The other channel is selected as a clock channel. Thus, the signals on the remaining channels may be sampled according to the signal on the selected clock channel. Multiple deserializers DS [0]]-DS[5]Two of the deserializers may output two clock signals according to the sampling result SR. For example, multiplexer 722.0 can couple channel LA [0]]Selected as a clock channel, a plurality of sampling circuits RX [1]]And RX [2]]Each sampling circuit in (1) can be according to channel LA [0]]The signal above is data sampled. Multiplexer 722.1 can connect channel LA [3]]Selected as a clock channel, a plurality of sampling circuits RX 4]And RX [5]]Each sampling circuit in (1) can be according to channel LA [3]]The signal above is data sampled. Deserializer DS [0]]Outputable AND channel LA [0]]A parallel clock signal related to the signal on, and a plurality of deserializers DS [1]]And DS [2]]Can respectively output and multiple channels LA [1]And LA 2]A plurality of parallel data signals related to the respective signals. In addition, deserializer DS [3]]Output and channel LA [3]A parallel clock signal related to the signal on, and a plurality of deserializers DS [4]]And DS [5]]Can respectively output and multiple channels LA [4]And LA [5]]A plurality of parallel data signals related to the respective signals. In this mode, a plurality of multiplexers 722.0, 722.1 and 724.0 may be used as an embodiment of the clock tree group G2 shown in FIG. 5B.

The circuit structure and operation described above with reference to fig. 7 are not intended to limit the scope of the present application. For example, the channel selection circuit 720 can be implemented by the channel selection circuit 320 shown in FIG. 3 or the channel selection circuit 620 shown in FIG. 6Without departing from the scope of the application. For another example, the multiplexers 722.0, 722.1 and 724.0 in the channel selection circuit 720 may be arranged in the arrangement shown in fig. 8. Referring to fig. 8, the structure of the integrated circuit 810 is similar/identical to the structure of the integrated circuit 710 shown in fig. 7, except for the channel selection circuit 820. In this embodiment, the multiplexer 724.0 can select the signal SEL according to the clock₇₂Selecting a plurality of clock signals SEL₇₀And SEL₇₁One of which is coupled to the output terminal T₇₁. Multiplexer 722.1 can output multiple channels LA [0] according to the signal outputted from multiplexer 724.0]-LA[5]Is coupled to the output terminal T₇₁. Since the operation details of the channel selection circuit 820 can be understood by those skilled in the art after reading the paragraphs related to fig. 1 to fig. 7, further description on the channel selection will not be repeated herein.

It is noted that, for the convenience of channel selection, a clock selection signal used in the clock forwarding scheme disclosed herein may have a signal value/signal pattern (signal pattern) that is mapped to a channel identifier (lane identifier) of a clock channel to be selected. The channel selection circuit can select the clock channel according to the clock selection signal. In some embodiments, the channel identifier may be a channel name (lane name) of the selected clock channel, a pin name (pin name) of a signal pin (signal pin) located in the selected clock channel, or a pin number (pin number) of the signal pin. For example, the channel identifier may be marked on a circuit board on which an integrated circuit having the selected clock channel is disposed, or on a package (package) that encapsulates the integrated circuit. For another example, the channel identifier may be marked or described in a data sheet (datasheet), a data book (data book), or a device specification (device specification) of the integrated circuit. In some embodiments, the channel identifier may be identification information carried by the selected clock channel. The integrated circuit may determine which channel should be selected as the clock channel by detecting the identification information.

Please refer to fig. 7 again. The integrated circuit 710 further includes a controlA circuit 750 for generating a plurality of clock selection signals SEL₇₀-SEL₇₂To control the channel selection circuit 720. When the clock selects the signal SEL₇₀/SEL₇₁With mapping to multiple channels LA [0]]-LA[5]The channel selection circuit 720 selects a channel according to the clock signal SEL when the channel identifier of the channel has a signal value₇₀/SEL₇₁Selecting multiple channels LA [0]]-LA[5]The channel of (a). In this embodiment, multiple channels LA [0]]-LA[5]Each channel identifier may include a numeric symbol (numeric symbol) and a plurality of channels LA [0]]-LA[5]The plurality of numeric symbols included in the respective channel identifiers indicate a group of consecutive numbers. For example, but not limited to, a pin name corresponding to a channel may be used as a channel identifier of the channel. Channel LA [0]]The pair of signal pins in (1) can be named as "dp 0" and "dn 0", channel LA [1]]The pair of signal pins of (a) may be named "dp 1" and "dn 1", and so on. The number symbols (i.e., "0" - "5") of each of the plurality of pin names dp0-dp5 may indicate a set of consecutive numbers (0-5).

IN this embodiment, the control circuit 750 is responsive to a control input IN_CT7Generating a plurality of clock selection signals SEL₇₀-SEL₇₂Wherein the control input IN_CT7Information indicating a channel identifier of the selected clock channel. Control input IN_CT7May include, but is not limited to, a mode select signal mss, a channel select signal cks0, and a channel select signal cks 1. The mode select signal mss may indicate the mode of the integrated circuit 710. For example, the mode select signal mss may include a bit to indicate whether the integrated circuit 710 is operating in a "1C" mode or a "2C" mode. The integrated circuit 710 operates in a "1C" mode to receive a single clock signal through the multi-channel interface 314. The integrated circuit 710 operates in a "2C" mode to receive two clock signals through the multi-channel interface 314.

The channel select signal cks0 may include, but is not limited to, three bits and may indicate a channel identifier of a selected clock channel (i.e., one of the plurality of channels LA [0] -LA [5 ]). The channel select signal cks0 may have a bit pattern or signal value that maps to the channel identifier of the selected clock channel. For example, a lane select signal cks0 having a bit pattern of "000" (corresponding to a signal value of "0") may indicate that lane LA [0] is selected as the clock lane. As another example, a lane select signal cks0 having a bit pattern of "011" (corresponding to a signal value of "3") may indicate that lane LA [3] is selected as the clock lane.

The channel select signal cks1 may include, but is not limited to, three bits and may indicate a selected clock channel (i.e., the plurality of channels LA [0 ])]-LA[5]One of them) of a channel identifier. The lane select signal cks1 may have a bit pattern or signal value that maps to the lane identifier of the clock lane selected. When the integrated circuit 710 operates in the "2C" mode to receive two clock signals through the selected two clock lanes, the lane select signal cks0 may indicate a lane identifier of the selected one of the two clock lanes, and the lane select signal cks1 may indicate a lane identifier of the selected other one of the plurality of clock lanes. For example, when the plurality of channel selection signals cks0 and cks1 have bit patterns "000" and "011" IN "2C" mode, respectively, the control input IN_CT7Can indicate the channel LA [0]]And a channel LA [3]Are selected as clock channels to receive respective clock signals, respectively.

IN operation, the control circuit 750 may be responsive to the control input IN when the integrated circuit 710 is operating IN a mode (such as "1C" mode) to receive a single clock signal CKA via the multi-channel interface 314_CT7Generating a clock select signal SEL₇₂. Clock select signal SEL₇₂Can have a first signal value to make the output terminal T₇₀The signal above may be distributed to each sampling circuit. For example, the control circuit 750 may generate the clock selection signal SEL according to the mode selection signal mss₇₂. For another example, the control circuit 750 may use the mode selection signal mss as the clock selection signal SEL₇₂. It is noted that IN some embodiments, the control input IN_CT7The mode selection signal mss in (1) can be directly input to the multiplexer 724.0 as the clock selection signal SEL₇₂。

In addition, the control circuit 750 can generate the clock selection signal SEL according to the channel identifier of the channel inputted by the clock signal CKA₇₀. In this embodiment, the control circuit 750 can generate the clock selecting signal SEL according to the channel selecting signal cks0₇₀Wherein the channel selection signal cks0 indicates the channel identifier of the channel inputted by the clock signal CKA. For example, when the channel selection signal cks0 indicates the channel LA [0]]When configured as a clock channel to receive the clock signal CKA, the control circuit 750 generates the clock selection signal SEL having a signal value "0" according to the channel selection signal cks0₇₀Which maps to the numeric symbol "0" for the pin name dp0/dn0 (i.e., channel LA [0]]The channel identifier of). As another example, when the channel select signal cks0 indicates the channel LA [3]]When configured as a clock channel to receive the clock signal CKA, the control circuit 750 generates the clock selection signal SEL having a signal value of "3" according to the channel selection signal cks0₇₀Which maps to the numerical symbol "3" for pin name dp3/dn 3. It is noted that, in some embodiments, since the channel selection signal cks0 may have the channel identifier mapped to the selected clock channel, the control circuit 750 may use the channel selection signal cks0 as the clock selection signal SEL₇₀。

When the integrated circuit 710 is operating IN another mode (such as the "2C" mode) to receive two clock signals CKB and CKC through the multi-channel interface 314, the control circuit 750 may respond to the control input IN_CT7Generating a clock select signal SEL₇₂. Clock select signal SEL₇₂May have a second signal value different from the first signal value. Thus, the output terminal T₇₀The signal on can be distributed to a plurality of sampling circuits RX 0]-RX[2]And an output terminal T₇₁Can be distributed to a plurality of sampling circuits RX 3]-RX[5]. For example, the control circuit 750 may generate the clock selection signal SEL according to the mode selection signal mss₇₂Or using the mode selection signal mss as the clock selection signal SEL₇₂. It is noted that IN some embodiments, the control input IN_CT7The mode select signal mss in (1) can be directly input to the multiplexer 724.0 as a clock selectGet signal SEL₇₂。

In addition, the control circuit 750 can generate the clock selection signal SEL according to the channel identifier of the channel inputted by the clock signal CKB₇₀And generating a clock selection signal SEL according to the channel identifier of the channel inputted by the clock signal CKC₇₁. In this embodiment, the control circuit 750 can generate the clock selection signals SEL according to the channel selection signals cks0 and cks1 in another mode (such as the "2C" mode)₇₀And SEL₇₁. For example, when the plurality of channel selection signals cks0 and cks1 indicate a plurality of channels LA [0]]And LA [3]]When configured as a clock channel for receiving a plurality of clock signals CKA and CKC, respectively, the control circuit 750 generates a clock selection signal SEL having a signal value of "0" according to a channel selection signal cks0₇₀And generating a clock selection signal SEL having a signal value of "3" according to the channel selection signal cks1₇₁. It is noted that, in some embodiments, since each of the plurality of channel selection signals cks0 and cks1 may have a channel identifier mapped to the selected clock channel, the control circuit 750 may use the plurality of channel selection signals cks0 and cks1 as the plurality of clock selection signals SEL, respectively₇₀And SEL₇₁。

In some embodiments, the transmitting side may send a preamble signal to a channel of the receiving side before sending a clock signal to the channel. By detecting whether the preamble signal exists, the receiving side can determine whether the clock signal reaches the channel. When a preamble signal appearing on a predetermined channel of the receiving side is detected, the receiving side is operable in a forking mode to support multi-clock transmission. For example, in the embodiment shown in fig. 7, the control circuit 750 may include a state machine (state machine)755 to automatically select the mode of the integrated circuit 710.

Fig. 9 is a schematic diagram of the operation of the state machine 755 shown in fig. 7 in accordance with some embodiments of the present application. Please refer to fig. 9 in conjunction with fig. 7. When the physical layer of the integrated circuit 710 is enabled, the state machine 755 may stay in state ST0 (e.g., an initial state). In the state ST0Clock select signal SEL₇₂May have the first signal value, so that the signal on the selected clock channel can pass through the output terminal T₇₀To each sampling circuit. After a period of time T _ wait, the state machine 755 may enter a state ST1, so that the control circuit 750 may be configured to detect whether the multi-channel interface 314 receives a preamble signal. When the leading signal is detected on a predetermined channel (i.e., another selected clock channel) of the multi-channel interface 314, the state machine 755 may enter the state ST2, and the clock select signal SEL₇₂May have the second signal value such that the integrated circuit 710 may operate in a fork mode. After the predetermined channel is deactivated, state machine 755 may return to state ST 0. Clock select signal SEL₇₂May be set to the first signal value.

In some embodiments, the predetermined lane may be the lane indicated by the clock select signal cks 1. The control circuit 750 determines the clock selection signal SEL by detecting whether a preamble signal is inputted to the channel indicated by the channel selection signal cks1₇₂The signal value of (a). In some embodiments, the control circuit 750 may be configured to detect whether any channel receives a preamble signal in addition to the channels indicated by the channel selection signal cks 1. Each channel detected by the control circuit 750 may correspond to the predetermined channel detected in the state ST 1.

The above-described automatic channel detection operation is for illustrative purposes only and is not intended to limit the scope of the present application. Referring again to FIG. 7, in some embodiments, the control circuit 750 of FIG. 7 may be configured to detect whether more than one preamble signal arrives at the multi-channel interface 314. The control circuit 750 may operate in the fork mode to support multi-clock transmission when more than one preamble is detected to arrive at the multi-channel interface 314. For example, the control circuit 750 may be coupled to the multi-channel interface 314 and may generate the clock selection signal SEL having the first signal value when detecting a single preamble on a channel₇₂. When detecting a plurality of leading signals on two channels, the control circuit 750 can generate the clock selecting signal SEL with the second signal value₇₂To makeIntegrated circuit 710 operates in a fork mode.

In addition, the above-described embodiment of implementing channel selection by using the mapping relationship between the channel identifier and the control input is only for illustrative purposes, and is not intended to limit the scope of the present application. In some embodiments, the control circuit 750 may include a decoder (not shown in FIG. 7). The decoder may decode a channel select signal having signal values/signal patterns mapped to channel identifiers of clock channels to generate a clock select signal for a clock channel to be selected. Thus, the control circuit 750 may be configured to control the input IN based on the channel identifier and the control input IN of the clock channel_CT7The channel selection signal of (2) to correctly select the clock channel.

It should be noted that the signal value of a channel selection signal (or the signal value of a clock selection signal) may directly or indirectly correspond/map to (map) the channel identifier of a clock channel to be selected. For example, when the clock signal CKA/CKB is inputted to the channel LA [0]]The channel select signal cks0 may have a bit pattern of "000001" corresponding to a signal value of "2" mapped to the digital symbol "0" of the pin name dp0/dn0⁰". In addition, or alternatively, the control circuit 750 may generate the clock select signal SEL having a bit pattern of "000001₇₀Wherein the bit pattern "000001" corresponds to the signal value "2" of the numeric symbol "0" mapped to the pin name dp0/dn0⁰". Also for example, when clock signal CKC is input to channel LA [3]]The channel select signal cks1 may have a bit pattern of "001000" corresponding to a signal value of "2" mapped to the numeric symbol "3" of the pin name dp3/dn3³". In addition, or alternatively, the control circuit 750 may generate the clock select signal SEL having the bit pattern "001000₇₁Wherein the bit pattern "001000" corresponds to a signal value of 2 mapped to the numeric symbol "3" of the pin name dp3/dn3³”。

In some embodiments, other types of channel identifiers (such as channel names, pin numbers, or identification information carried by the channel) may be mapped to signal values of the channel selection signal. In some embodiments, the control circuit 750 may determine the signal value of the clock selection signal according to other types of channel identifiers (such as channel name, pin number, or identification information carried by the channel). In some embodiments, the numeric symbols of the channel identifier may be in the form of arabic numerals, roman numerals, letters, or other types of numeric symbols. In some embodiments, the set of consecutive numbers indicated by the number symbol of each of the plurality of channel identifiers may be a plurality of consecutive odd numbers, a plurality of consecutive even numbers, or a plurality of numbers having a predetermined consecutive order. For example, some embodiments of the channel identifiers for the multiple channels LA [0] -LA [5] shown in FIG. 7 are shown in FIG. 10, according to some embodiments of the present application. Such design modifications and variations are intended to fall within the scope of the present application following the spirit of the present application.

The channel selection operation described above may be applied to the integrated circuit 110 shown in FIG. 1, the integrated circuit 310 shown in FIG. 3, the plurality of integrated circuits 510A-510C shown in FIGS. 5A-5C, the integrated circuit 610 shown in FIG. 6, and the integrated circuit 810 shown in FIG. 8. For example, please refer to fig. 3 again. The integrated circuit 310 further includes a control circuit 350 responsive to a control input IN_CT3Generating a plurality of clock selection signals SEL₀₀、SEL₀₁And SEL₁₀-SEL₁₅Thereby controlling the channel selection circuit 320.

Control input IN_CT3Information indicating a channel identifier of the selected clock channel. For example. Control input IN_CT3A plurality of channel selection signals may be included, wherein each channel selection signal may indicate information of a channel identifier of a selected clock channel. The control circuit 350 may generate the clock selection signal SEL according to a channel selection signal₀₀And generating a clock selection signal SEL according to the other channel selection signal₀₁. Also for example, the control input IN_CT3A mode select signal may also be included that indicates the mode of the integrated circuit 310. The control circuit 350 may generate a plurality of clock selection signals SEL according to the mode selection signal₁₀-SEL₁₅。

In the "5D 1C" channel configuration, multiple clock selection signals SEL₁₀-SEL₁₅May have the same signal value, so that one of the output sides S02 and S12 may be coupled to each sampling circuit. When the clock signal 5D _ CLK is input to multiple channels LA [0]]-LA[2]In one channel, multiple clock selection signals SEL₁₀-SEL₁₅May have a first signal value such that the output side S02 may be coupled to each sampling circuit. The control circuit 350 can be responsive to a control input IN_CT3One channel selection signal in the clock selection signal SEL₀₀Wherein the channel selection signal has a signal value mapped to a channel identifier of the channel. In addition, or alternatively, the clock select signal SEL₀₀May have a signal value mapped to a channel identifier of the channel. When the clock signal 5D _ CLK is input to multiple channels LA [3]]-LA[5]In one channel, multiple clock selection signals SEL₁₀-SEL₁₅May have a second signal value such that the output side S12 may be coupled to each sampling circuit. The control circuit 350 can be responsive to a control input IN_CT3Generates a clock selection signal SEL by the other channel selection signal₀₁Wherein the other channel selection signal has a signal value mapped to the channel identifier of the channel. In addition, or alternatively, the clock select signal SEL₀₁May have a signal value mapped to a channel identifier of the channel.

In the "2D 1C" branch channel configuration, multiple clock select signals SEL₁₀-SEL₁₂Each clock select signal in (1) may have a signal value different from the plurality of clock select signals SEL₁₃-SEL₁₅Each clock selects a signal value of the signal. Thus, the output side S02 may be coupled to a plurality of sampling circuits RX [0]]-RX[2]The output side S12 may be coupled to a plurality of sampling circuits RX [3]]-RX[5]. Since the clock signal 2D _ CLK0 is input to multiple channels LA [0]]-LA[2]So that the control circuit 350 can control the input IN according to the control signal_CT3One channel selection signal in the clock selection signal SEL₀₀Wherein the channel selection signal has a signal value mapped to a channel identifier of the channel. In addition, or instead ofGround, clock select signal SEL₀₀May have a signal value mapped to a channel identifier of the channel. Similarly, since the clock signal 2D _ CLK0 is input to multiple channels LA [3]]-LA[5]So that the control circuit 350 can control the input IN according to the control signal_CT3Generates a clock selection signal SEL by the other channel selection signal₀₁Wherein the other channel selection signal has a signal value mapped to the channel identifier of the channel. In addition, or alternatively, the clock select signal SEL₀₁May have a signal value mapped to a channel identifier of the channel.

In some embodiments, the clock select signal SEL₀₀And a clock select signal SEL₀₁May be implemented as a single clock select signal. The multiple channel selection units 322.0 and 322.1 may each perform a channel selection operation based on the single clock selection signal. The control circuit 350 may determine the signal value/signal pattern of the single clock selection signal according to one or more channel identifiers of one or more channels to be selected. For example, in a "5D 1C" lane configuration, the single clock signal has a signal value that maps to the lane identifier of the lane for which the clock signal 5D _ CLK is input. As another example, in a "2D 1C" split channel configuration, the first three Least Significant Bits (LSBs) of the single clock signal have a signal value that maps to multiple channels LA [0]]-LA[2]A channel identifier of one of the channels. The first three Most Significant Bits (MSBs) of the single clock signal have a signal value that maps to a plurality of channels LA [3]]-LA[5]A channel identifier of one of the channels.

Similarly, referring again to FIG. 1, the integrated circuit 110 further includes a control circuit 150, which can be responsive to a control input IN_CT1Generating a clock selection signal, or generating the clock selection signal according to a channel identifier of one of the selected plurality of clock channels. Control input IN_CT1The channel identifier may be indicated. Additionally, or alternatively, the clock select signal may have a signal value that maps to the channel identifier. Therefore, the channel selection circuit 120 can select the channel according to the timeThe clock select signal selects the channel. Additionally, or alternatively, in the embodiments shown in fig. 5A, 5B, 5C, and 6, the clock select signal SEL_A/SEL_B1/SEL_B2/SEL_C1/SEL_C2/SEL_C3May be determined based on the channel identifier of the channel to which the clock signal is input. As a person skilled in the art will understand after reading the above paragraphs directed to fig. 7, fig. 8 and fig. 3, it should be appreciated that the clock select signal SEL shown in fig. 5A, fig. 5B, fig. 5C and fig. 6 is generated_A/SEL_B1/SEL_B2/SEL_C1/SEL_C2/SEL_C3Therefore, further description is not repeated herein.

At least one of the channel interchange scheme and the channel selection operation described above may be applied to other sub-layers of the physical layer, such as the physical coding sub-layer. FIG. 11 is a functional block diagram of an exemplary receiver according to some embodiments of the present application. Receiver 1104 may be implemented as receiver 104 in the embodiment shown in fig. 1. Physical layer 1108 of receiver 1104 includes a physical medium attachment layer (PMA)1105 and a Physical Coding Sublayer (PCS) 1107. The physical media connection layer 1105 may employ the circuit structure and operation described with reference to fig. 1-10.

Physical medium connection layer 1105 includes, but is not limited to, a multi-channel interface 1114, a channel selection circuit 1120, and a plurality of S2P converters 1130₀-1130_N-1Wherein N is an integer greater than 1. Multi-channel interface 1114 and channel selection circuitry 1120 may be implemented as embodiments of multi-channel interface 114 and channel selection circuitry 120, respectively, as shown in fig. 1. The multi-channel interface 114 may include the N channels LA [0] shown in FIG. 1]-LA[N-1]. The channel selection circuit 1120 is used for selecting signals { SEL) according to a set of clocks_PMASelect one or more channels in the multi-channel interface 1114 as one or more clock channels. In addition, a plurality of S2P converters 1130₀-1130_N-1N sampling circuits RX 0 shown in FIG. 1 may be utilized]-RX[N-1]And output circuit 140.

The physical coding sublayer 1107 includes, but is not limited to, a multi-channel interface 1116, a channel selection circuit 1122, and a plurality of processing circuits 1132₀-1132_N-1. The multi-channel interface 1116 may be implemented as an embodiment of the multi-channel interface 114 shown in FIG. 1. Multi-channel interface 1116 includes N channels LS [0] coupled to physical media connection layer 1105]-LS[N-1]. The channel selection circuit 1122 can be implemented as the channel selection circuit 120 shown in FIG. 1. The channel selection circuit 1122 is used to select a signal { SEL according to a set of clocks_PCSWill N channels LS [0]]-LS[N-1]Is selected as one or more clock channels. N channels LS [0]]-LS[N-1]Each channel in (1) can be commonly used for a clock channel and a data channel. In addition, multiple processing circuits 1132₀-1132_N-1May be implemented to include N sampling circuits RX [0] respectively as shown in FIG. 1]-RX[N-1]To sample data according to one or more clock signals from the physical media connection layer 1105.

In operation, the physical medium connection layer 1105 can be used to output M clock signals CKD respectively associated with M different clock domains (clock domains)₁-CKD_MAnd M is a positive integer less than N. Physical coding sublayer 1107 may convert N channels LS [0]]-LS[N-1]M channels in the clock signal are selected as M clock channels to receive M clock signals CKD₁-CKD_M. That is, in response to the channel selection operation of the physical media connection layer 1105, the physical coding sublayer 1107 may perform the corresponding channel selection operation. For example, the multi-channel interface 1114 of the physical media connection layer 1105 can receive M clock signals transmitted by M transmitters (not shown in FIG. 11) to generate M clock signals CKD₁-CKD_MWherein the M transmitters operate in the M different clock domains, respectively. The channel selection circuit 1120 can select signals { SEL) according to a set of clocks_PMAWill select the M channels in the multi-channel interface 1114 as M clock channels. Multiple S2P converters 1130₀-1130_N-1M S2P converters (coupled to the selected M channels) can generate M clock signals CKD respectively₁-CKD_M. In response to the channel selection operation of the physical media connection layer 1105, the channel selection circuit 1122 in the physical coding sublayer 1107 may select the channel according to a set of clock selection signals { SEL_PCSWill separate N channels LS [0]]-LS[N-1]The M channels in (a) are selected as M clock channels. N channels LS [0]]-LS[N-1]One or more of the remaining (N-M) lanes may comprise one or more lanes as one or more data lanes. Multiple processing circuits 1132₀-1132_N-1According to M clock signals CKD₁-CKD_MAnd processing the data on the one or more data channels.

A set of clock selection Signals (SEL)_PMAAnd a set of clock select signals { SEL }_PCSMay be generated by a control input shared by the physical media connection layer 1105 and the physical coding sublayer 1107. In this embodiment, the physical coding sublayer 1107 may further comprise a control circuit 1150, which may be implemented as the control circuit 150 shown in fig. 1. The control circuit 1150 may be based on a control input IN_CTRLGenerating a set of clock select signals { SEL_PMAAnd a set of clock select Signals (SEL)_PCS}. Control input IN_CTRLA channel identifier may indicate a selected clock channel in the physical media connectivity layer 1105 and a channel identifier may indicate a selected clock channel in the physical coding sublayer 1107. For example, when the control input IN_CTRLChannel LA [0] with mapping to physical media connection layer 1105]IN accordance with the signal pattern/signal value of the channel identifier, the control circuit 1150 may input IN according to the control_CTRLGenerating a set of clock select signals { SEL_PMAMake the passage LA [0]]May be configured as a clock channel to receive a clock signal transmitted by a transmitter (not shown in fig. 11). IN addition, the control circuit 1150 may control the input IN according to the control input_CTRLGenerating a set of clock select signals { SEL_PCSMake the channel LS [0]](with mapping to control input IN_CTRLThe channel identifier of the signal mode/signal value) may be set as a clock channel to receive the clock signal output by the physical media connection layer 1105, where the clock signal output by the physical media connection layer 1105 is generated in response to the clock signal transmitted by the transmitter.

For example, but not limiting to the present application, control input IN_CTRLA plurality of channel selection signals may be included, wherein each channel selection signal may indicate a channel identifier of a selected clock channel. Also for example, the control input IN_CTRLCan select signals in a modeAnd a plurality of channel selection signals, wherein the mode selection signals may indicate a mode of the receiver 1104, such as "1C" mode or a forking mode. Since it should be understood that the control circuit 1150 can control the channel selection circuit 1120 and the channel selection circuit 1122 by using the mapping relationship between the channel identifier and the control input after reading the paragraphs related to fig. 1 to fig. 10, the repeated descriptions related to the channel selection will not be repeated herein.

In some embodiments, the shared control circuitry 1150 may be disposed in the physical media connection layer 1105 rather than in the physical coding sublayer 1107. In some embodiments, the physical media connection layer 1105 may have a first control circuit disposed therein, and the physical coding sublayer 1107 may have a second control circuit disposed therein. The first control circuit and the second control circuit may be based on the same control input (such as control input IN)_CTRL) To control the channel selection operation. Such design modifications and variations are intended to fall within the scope of the present application following the spirit of the present application.

Some embodiments are provided below to further illustrate the physical coding sublayer 1107 that employs a channel interchange scheme. It should be understood by those skilled in the art that other physical coding sublayers employing the channel interchange scheme described with reference to fig. 1 to 10 all fall within the scope of protection of the present application following the spirit of the present application.

Figure 12 is a schematic diagram of an embodiment of an integrated circuit in the physical coding sublayer 1107 shown in figure 11 according to some embodiments of the present application. Integrated circuit 1210 in physical coding sublayer 1207 may be implemented as integrated circuit 110 (which includes six channels, N6, which may be commonly used for a clock channel and a data channel) in fig. 1. In this embodiment, the physical coding sublayer 1207 is configured to receive clock and data information transmitted by a physical medium attachment layer (PMA)1205, where the physical medium attachment layer 1205 may be implemented as the physical medium attachment layer 1105 shown in fig. 11. The integrated circuit 1210 may include a multi-channel interface 1214, a channel selection circuit 1220, and a plurality of sampling circuits RM 0-RM 5. Multi-channel interface 1214 and channel selection circuitry 1220 may be used as embodiments of multi-channel interface 114 and channel selection circuitry 120, respectively, as shown in FIG. 1. A plurality of sampling circuits RM [0] -RM [5] may be used as an embodiment of the plurality of sampling circuits RX [0] -RX [5] shown in FIG. 1.

Multi-channel interface 1214 is coupled to physical media link layer 1205 and includes a plurality of channels LS [0] -LS [5] shown in FIG. 11. Multiple channels LS [0] -LS [5] may be used as an example of N channels LA [0] -LA [ N-1] shown in fig. 1 (i.e., N ═ 6). In this embodiment, each of the plurality of channels LS [0] -LS [5] may carry a multi-bit output signal, such as a one-byte data signal or a one-byte clock signal.

The channel selection circuit 1220 is used to select a plurality of channels LS [0]]-LS[5]Is selected as one or more clock channels. One or more of the remaining lanes may be used as one or more data lanes. The channel selection circuit 1220 includes, but is not limited to, a plurality of selection stages 1222 and 1224, which may be implemented as embodiments of the plurality of selection stages 122 and 124 shown in fig. 1, respectively. In this embodiment, the select stage 1222 may couple one or two channels to the select stage 1224 in response to a mode of the integrated circuit 1210. The selection stage 1222 includes a plurality of channel selection cells 1222.0 and 1222.1. The channel selection unit 1222.0 selects a signal SEL according to a clock₁₀₀Multiple channels LS [0]]-LS[5]Is coupled to an output terminal T₁₀₀. The channel selection unit 1222.1 is used for selecting a signal SEL according to a clock₁₀₁Multiple channels LS [0]]-LS[5]Is coupled to an output terminal T₁₀₁. The selection stage 1224 may be implemented to include a channel selection unit 1224.0 that selects a channel according to a clock selection signal SEL₁₀₂Will output terminal T₁₀₀And an output terminal T₁₀₁One of which is coupled to an output terminal T₁₀₂。

Multiple sampling circuits RM [0]]-RM[5]The channel selection circuit 1220 is coupled to the multi-channel interface 1214 and the channel selection circuit for sampling data according to the clock information and the data information transmitted by the physical medium link layer 1205. In this embodiment, a plurality of sampling circuits RM [0]]-RM[5]Each sampling circuit in (1) may comprise a clock input PC_INAnd a data input terminal PD_IN. Each sampling circuit being operable to utilize an input to a respective clock inputPC_INFor signals input to the corresponding data input terminal PD_INThe signal of (a) is sampled.

In a mode where the integrated circuit 1210 supports a "4D 1C" channel configuration, the channel selection unit 1224.0 is used to select the output terminal T₁₀₀Is coupled to the output end T₁₀₂. When the channel selection unit 1222.0 selects a plurality of channels LS [0]]-LS[5]When one of the channels is selected as a clock channel, the signal on the clock channel can be coupled to the output end T₁₀₀And is distributed to a plurality of sampling circuits RM [0]]-RM[5]Respective clock input terminal PC_IN. For example, when a clock signal is input to the channel LS [0]]Then, the channel selection unit 1222.0 selects the LS [0] channel]Selected as a clock channel, and a plurality of sampling circuits RM [0]]-RM[5]May be based on the same clock signal (i.e., channel LS [0]]The above) to perform data sampling.

In a mode where the integrated circuit 1210 supports a "2D 1C" branch channel configuration, the channel selection unit 1224.0 is used to select the output terminal T₁₀₁Is coupled to the output end T₁₀₂. When the channel selection unit 1222.0 selects a plurality of channels LS [0]]-LS[5]When one of the channels is selected as a clock channel, the channel selection unit 1222.1 can have multiple channels LS [0]]-LS[5]The other channel is selected as a clock channel. Thus, the signals on the remaining plurality of channels may be sampled according to the signals on the selected plurality of clock channels. For example, when two clock signals are input to the channel LS [1] respectively]And channel LS [4]]Then, the channel selection unit 1222.0 selects the channel LS [1]]Is selected as a clock channel and the channel selection unit 1222.1 selects the channel LS [4]]Is selected as the other clock channel. Multiple sampling circuits RM [0]]-RM[5]May sample data according to the two clock signals involving different clock domains.

It is noted that the physical coding sublayer 1207 may employ the channel selection operation described above. IN this embodiment, the integrated circuit 1210 further includes a control circuit 1250 that can be responsive to a control input IN_CT12Generating a plurality of clock selection signals SEL₁₀₀-SEL₁₀₂And thus controls the channel selection circuit 1220. For example, when the physical medium is transmitted by the connection layer 1205A clock signal is input to the plurality of channels LS [0] in a "4D 1C" channel configuration]-LS[5]IN one channel, the control circuit 1250 can be configured to control the input IN according to the control input_CT12Generating a clock select signal SEL₁₀₀Which may indicate a channel identifier for the channel. As another example, when two clock signals are input to the multiple channels LS [0] in a "2D 1C" split channel configuration]-LS[5]IN two channels, the control circuit 1250 can control the input IN according to the control input_CT12Generating a clock select signal SEL₁₀₀Which may indicate a channel identifier for one of the two channels. IN addition, the control circuit 1250 may be responsive to the control input IN_CT12Generating a clock select signal SEL₁₀₁Which may indicate a channel identifier of the other of the two channels.

The above-described channel selection operation may be applied to a data channel selection operation. For example, the channel selection circuit 1220 further includes a plurality of channel selection units 1232.0-1232.3, which can be used to select a plurality of data selection signals SEL generated by the control circuit 1250₁₁₀-SEL₁₁₃And (4) controlling. In this embodiment, the channel selection units 1232.0-1232.3 may provide data transmitted by the physical medium link layer 1205 to the sampling circuits RM [0] respectively]、RM[2]、RM[3]And RM [5]]。

In the mode of the "4D 1C" channel configuration (multiple channels LS [0]]-LS[5]One of which is selected as a clock channel), the control circuit 1250 may be responsive to the control input IN_CT12Generating a plurality of data selection signals SEL₁₁₀-SEL₁₁₃Wherein the control input IN_CT12The channel identifiers of the respective four channels carrying the data signal transmitted by the physical medium connection layer 1205 can be indicated. For example, a plurality of data selection signals SEL₁₁₀-SEL₁₁₃Respective signal values may be mapped to respective channel identifiers of the four channels, respectively.

In the mode of the "2D 1C" channel configuration (multiple channels LS [0]]-LS[5]Two of which are selected as clock channels), the control circuit 1250 may be responsive to the control input IN_CT12Generating a plurality of data selection signals SEL₁₁₀And SEL₁₁₁Wherein the control input IN_CT12The channel identifiers of the two channels may be indicated. The two lanes may carry data signals related to the clock signal output by the lane select unit 1222.0. For example, a plurality of data selection signals SEL₁₁₀And SEL₁₁₁Respective signal values may be mapped to respective channel identifiers of the two channels, respectively. In addition, the control circuit 1250 can generate a plurality of data selection signals SEL according to the channel identifiers of the other two channels₁₁₂And SEL₁₁₃Wherein the two other lanes may carry data signals related to the clock signal output by lane select unit 1222.1. For example, a plurality of data selection signals SEL₁₁₂And SEL₁₁₃Respective signal values may be mapped to respective channel identifiers of the two further channels, respectively.

Since those skilled in the art should understand that the data channel selecting operation employed in the clock forwarding scheme may be similar to/identical to the clock channel selecting operation described with reference to fig. 1 to 11, repeated descriptions are omitted here.

In some embodiments, control circuitry 1250 may be shared by physical media connectivity layer 1205 and physical coding sublayer 1207. For example, the control circuitry 1250 may generate one or more clock select signals to control the clock select operation of the physical media connection layer 1205. Also for example, the control circuit 1250 may use one or more clock selection signals of the channel selection circuit 1220 to control a channel selection circuit (not shown in fig. 12) of the physical media connection layer 1205 to cause the respective channel selection operations of the physical media connection layer 1205 and the physical coding sublayer 1207 to coincide with each other.

It is noted that the circuit structure and operation of the channel selection circuit 1220 shown in fig. 12 are for illustrative purposes only. In some embodiments, the channel selection circuit 1220 may be implemented using the channel selection circuit 120 shown in FIG. 1, the channel selection circuit 320 shown in FIG. 3, the plurality of channel selection circuits 520A-520C shown in FIGS. 5A-5C, the channel selection circuit 620 shown in FIG. 6, the channel selection circuit 720 shown in FIG. 7, the channel selection circuit 820 shown in FIG. 8, and related design changes described above without departing from the scope of the present application.

For example, please refer to FIG. 13, which is a diagram illustrating another embodiment of an integrated circuit in the physical coding sublayer 1107 of FIG. 11 according to some embodiments of the present application. The structure of the integrated circuit 1310 of the physical coding sublayer 1307 may be similar/identical to the structure of the integrated circuit 1210 shown in fig. 12, except for the channel selection circuit 1320. In this embodiment, the selection stage 1322 of the channel selection circuit 1320 includes a channel selection unit 1322.a, a channel selection unit 1322.b, and the channel selection unit 1222.1 shown in FIG. 12. The channel selection unit 1322.a can select the SEL according to the clock selection signal₁₀₀Multiple channels LS [0]]-LS[5]Is coupled to an output terminal T_13AWherein the output terminal T_13ACoupled to a plurality of sampling circuits RM [0]]-RM[2]Respective clock input terminal PC_IN. The channel selection unit 1322.b can select the signal SEL according to the clock₁₀₀Multiple channels LS [0]]-LS[5]Is coupled to an output terminal T_13BWherein the output terminal T_13BCoupled to the channel selection unit 1224.0. Since the details of the operation of the channel selection circuit 1320 will be understood by those skilled in the art after reading the paragraphs associated with fig. 1-12, further description is omitted here for brevity.

In addition, the above described channel selection scheme may also be applied to the transmit side. FIG. 14 is a functional block diagram of an exemplary multi-channel communication system according to some embodiments of the present application. The multi-channel communication system 1400 may include a transmitter 1402 and a receiver 1404. The transmitter 1402 may be implemented as one of the K transmitters TX [0] -TX [ K-1] shown in FIG. 1. The receiver 1404 may employ the circuit structures and operations described with reference to fig. 1-13. In this embodiment, the transmitter 1402 may cause signals transmitted on the clock channel and on the data channel to be interchanged with one another. Transmitter 1402 includes, but is not limited to, a plurality of signal generating circuits 1410.0-1410.2, a channel selection circuit 1420, a plurality of parallel-to-serial converters (hereinafter "P2S converters") 1430.0-1430.2, a multi-channel interface 1440, and a control circuit 1450.

Each of the plurality of signal generating circuits 1410.0-1410.2 may generate a multi-bit output signal, such as a parallel clock signal or a parallel data signal, on the data bus (data bus). In this embodiment, the signal generation circuit 1410.0 and the signal generation circuit 1410.1 can be implemented by a data signal generator, and the signal generation circuit 1410.2 can be implemented by a clock signal generator. Accordingly, the plurality of signal generating circuits 1410.0 and 1410.1 may generate a plurality of parallel data signals PD0 and PD1 on the plurality of data buses DB0 and DB1, respectively. The signal generation circuit 1410.2 may generate a parallel clock signal PC0 on the data bus DB 2.

The channel selection circuit 1420 is coupled to the plurality of signal generating circuits 1410.0-1410.2 for distributing the plurality of multi-bit output signals generated by the plurality of signal generating circuits 1410.0-1410.2 to the plurality of P2S converters 1430.0-1430.2. In this embodiment, the channel selection circuit 1420 includes a plurality of channel selection units 1422.0-1422.2, wherein each channel selection unit is capable of selecting a channel according to a corresponding selection signal (i.e., a plurality of selection signals SEL)_T0-SEL_T2One of which) to output one of a plurality of output signals on a plurality of data buses DB0-DB 2.

Each P2S converter of the P2S converters 1430.0-1430.2 may convert a parallel output signal to a serial output signal (serial output signal). Multichannel interface 1440 may be implemented as one of the K multichannel interfaces TF [0] -TF [ K-1] shown in FIG. 1. The multi-channel interface 1440 may include a plurality of channels LT [0] -LT [2 ]. At least one of the plurality of lanes LT 0-LT 2 may be common to both the clock lane and the data lane. In this embodiment, each lane of the plurality of lanes LT [0] -LT [2] may be implemented using a two-wire lane, which is a differential lane comprising a pair of signal pins. The included pair of signal pins for channel LT [0] may be designated as "dpt 0" and "dnt 0", the included pair of signal pins for channel LT [1] may be designated as "dpt 1" and "dnt 1", and so on. In some embodiments, each of the lanes LT [0] -LT [2] may be implemented using other types of lanes, such as a single lane or a lane having more than two lines, without departing from the scope of the present application.

The control circuit 1450 is used for controlling the input IN according to a control input_CT14Generating a plurality of selection signals SEL_T0-SEL_T2Thereby controlling the channel selection circuit 1420. Multiple selection signals SEL_T0-SEL_T2Wherein the signal value of each selection signal can be input IN according to the control_CT14Is determined, wherein control inputs IN_CT14A channel identifier corresponding to a channel may be indicated. For example, the receiver 1404 may use the channel 1406.0 as a clock channel to receive clock information transmitted by the transmitter 1402. Both channel 1406.1 and channel 1406.2 may serve as data channels for receiver 1404. By coupling the signal generation circuit 1410.2 to the P2S transformer 1430.0, the channel selection unit 1422.0 can select a signal SEL according to the selection signal SEL_T0Channel LT [0]](which is coupled to channel 1406.0) is selected as a clock channel. Control circuit 1450 may be responsive to lane LT [0]]Such as a pin name "dpt 0/dnt 0" or a channel name "LT [0]]") to determine the selection signal SEL_T0The signal value of (a). In addition, the channel selection unit 1422.1 can select the signal SEL according to the selection signal SEL_T1Will channel LT [1]]Is selected as a data channel, and the channel selection unit 1422.2 selects the data channel according to the selection signal SEL_T2Will channel LT 2]Is selected as a data channel. Since the details of the clock/data channel selection operation of the channel selection circuit 1420 will be understood by those skilled in the art after reading the above paragraphs directed to the clock/data channel selection operation of the receiving side, further description is omitted here for brevity.

The circuit configuration described above is for illustrative purposes only and is not intended to limit the scope of the present application. In some embodiments, the number of channels of the multi-channel interface may be changed according to different design requirements and applications. For example, a multi-channel interface may include four channels, eight channels, or other numbers of channels according to various embodiments. In some embodiments, the one or more channel selection units may be implemented using one or more multiplexers, or using other circuitry with signal path selection capabilities. In some embodiments, the one OR more multiplexers may be implemented based on inverters, OR-logic gates (OR-logic gates), other circuits with signal path selection capability, OR a combination thereof.

The physical layer of the receiving side may support different channel configurations of the transmitting side by at least one channel that may be used interchangeably between the clock channel and the data channel. For example, the physical layer may be divided into multiple physical interfaces to support multiple transmitters. In addition, a clock/data lane may be selected based on its lane identifier to facilitate clock/data lane selection.

The previous description briefly presents features of certain embodiments of the application so that those skilled in the art may more fully understand the various aspects of the application. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should understand that they can still make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (20)

1. An integrated circuit in a physical layer of a receiver, comprising:

a multi-channel interface having N channels, N being an integer greater than 1;

a channel selection circuit, coupled to the multi-channel interface, for selecting M of the N channels as M clock channels and outputting M signals on the M clock channels, respectively, where M is a positive integer less than N, and the remaining (N-M) channels are used as (N-M) data channels; and

n sampling circuits coupled to the multi-channel interface and the channel selection circuit, wherein (N-M) sampling circuits of the N sampling circuits are respectively coupled to the (N-M) data channels; each of the (N-M) sampling circuits is configured to sample a signal on a data channel of the (N-M) data channels according to one of the M signals on the M clock channels;

wherein the channel selection circuit comprises:

a first multiplexer having an input side coupled to each of the N channels;

a second multiplexer, an input side of the second multiplexer being coupled to a portion of the N channels and not being coupled to another portion of the N channels; and

n third multiplexers, respective output sides of the N third multiplexers being coupled to the N sampling circuits, respectively, wherein the first multiplexer selects one clock channel by coupling one of the N channels to an input side of each of the N third multiplexers; the second multiplexer selects a clock channel by coupling one of the partial channels of the N channels to an input side of each of a portion of the N third multiplexers.

2. The integrated circuit of claim 1, wherein the channel selection circuit is configured to couple the signal on the clock channel to each of the N sampling circuits when M equals 1; when M is greater than 1, the channel selection circuit is configured to couple one of the M signals on the M clock channels to one of the N sampling circuits and to couple another one of the M signals on the M clock channels to another one of the N sampling circuits.

3. The integrated circuit of claim 1, wherein the channel selection circuit selects one of the N channels as a clock channel by coupling the one of the N channels to a clock input of one of the N sampling circuits.

4. The integrated circuit of claim 1, wherein each of the M signals on the M clock channels is not coupled to a data input of each of the N sampling circuits.

5. The integrated circuit of claim 1, wherein the first multiplexer and the second multiplexer are at least a portion of a first selection stage of the channel selection circuit, and the N third multiplexers are at least a portion of a second selection stage of the channel selection circuit, wherein:

the first selection stage has an input side and an output side, the input side of the first selection stage is coupled to the multi-channel interface, and the first selection stage is configured to couple the M signals on the M clock channels from the input side of the first selection stage to the output side of the first selection stage; and

the second selection stage is disposed between an output side of the first selection stage and the N sampling circuits, and the second selection stage is configured to couple each of the M signals on the M clock channels to one or more of the N sampling circuits.

6. The integrated circuit of claim 1, further comprising:

the control circuit is coupled to the channel selection circuit and used for detecting whether a channel in the M channels receives a leading signal or not so as to generate a clock selection signal, wherein when the control circuit detects that the channel in the M channels receives the leading signal, the channel selection circuit is used for selecting the channel in the M channels according to the clock selection signal.

7. The integrated circuit of claim 1, wherein the integrated circuit is located at a physical media connection layer of the physical layer, M being greater than 1, the integrated circuit further comprising: and an output circuit, coupled to the N sampling circuits, for outputting M clock signals from the physical medium connection layer according to sampling results of the N sampling circuits, wherein the M clock signals are respectively associated with M different clock domains.

8. The integrated circuit of claim 1, wherein the channel selection circuit is configured to select one of the M channels according to a clock selection signal; the integrated circuit further comprises:

a control circuit, coupled to the channel selection circuit, for generating the clock selection signal according to a channel identifier of the channel of the M channels, the clock selection signal having a signal value mapped to the channel identifier.

9. The integrated circuit of claim 8, wherein the channel identifiers of each of the N channels each include a numeric symbol, and wherein the plurality of numeric symbols included in the channel identifiers of each of the N channels indicates a set of consecutive numbers.

10. The integrated circuit of claim 1, wherein the channel selection circuit is configured to couple one of the (N-M) channels to one of the N sampling circuits according to a data selection signal; the integrated circuit further comprises:

a control circuit, coupled to the channel selection circuit, for generating the data selection signal having a signal value mapped to the channel identifier of the one of the (N-M) channels according to the channel identifier of the one of the (N-M) channels.

11. The integrated circuit of claim 10, wherein the channel identifiers of each of the N channels each include a numeric symbol, and wherein the plurality of numeric symbols included in the channel identifiers of each of the N channels indicates a set of consecutive numbers.

12. An integrated circuit in a physical layer of a receiver, comprising:

a multi-channel interface having N channels, N being an integer greater than 1;

n sampling circuits coupled to the multi-channel interface, wherein each of the N sampling circuits has a clock input and a data input; and

a channel selection circuit for selecting M of the N channels as M clock channels by coupling the M channels to N clock inputs of the N sampling circuits, wherein M is a positive integer less than N, and the remaining (N-M) channels are used as (N-M) data channels; in one mode, one of the N channels is selected as a clock channel coupled to one or more of the N clock inputs; in another mode, the selected one of the N channels serves as a data channel coupled to one of N data inputs of the N sampling circuits but not to the N clock inputs;

wherein the channel selection circuit comprises:

a first multiplexer having an input side coupled to each of the N channels;

a second multiplexer, an input side of the second multiplexer being coupled to a portion of the N channels and not being coupled to another portion of the N channels; and

n third multiplexers, respective output sides of the N third multiplexers being coupled to the N sampling circuits, respectively, wherein the first multiplexer selects one clock channel by coupling one of the N channels to an input side of each of the N third multiplexers; the second multiplexer is configured to select a clock channel by coupling one of the partial channels of the N channels to an input side of each of the N third multiplexers.

13. The integrated circuit of claim 12, wherein the N sampling circuits are divided into M groups of sampling circuits, and wherein the M groups of sampling circuits are configured to receive M signals on the M clock channels, respectively.

14. The integrated circuit of claim 12, wherein each of the (N-M) sampling circuits respectively coupled to the (N-M) data channels is configured to sample a signal on the corresponding data channel according to a selected signal on the clock channel when M equals 1; when M is greater than 1, one of the (N-M) sampling circuits respectively coupled to the (N-M) data channels is configured to sample a signal on the corresponding data channel according to one of the M signals on the M clock channels, and another of the (N-M) sampling circuits is configured to sample a signal on the corresponding data channel according to another of the M signals on the M clock channels.

15. The integrated circuit of claim 12, wherein the first multiplexer and the second multiplexer are at least a portion of a first selection stage of the channel selection circuit, and the N third multiplexers are at least a portion of a second selection stage of the channel selection circuit, wherein:

the first selection stage has an input side and an output side, the input side of the first selection stage is coupled to the multi-channel interface, and the first selection stage is configured to couple the M signals on the M clock channels from the input side of the first selection stage to the output side of the first selection stage; and

the second selection stage is disposed between the output side of the first selection stage and the N sampling circuits, and the second selection stage is configured to distribute the M signals on the M clock channels to the N clock input terminals.

16. The integrated circuit of claim 12, wherein the integrated circuit is located at a physical media connection layer of the physical layer, M being greater than 1, the integrated circuit further comprising:

and an output circuit, coupled to the N sampling circuits, for outputting M clock signals from the physical medium connection layer according to sampling results of the N sampling circuits, wherein the M clock signals are respectively associated with M different clock domains.

17. The integrated circuit of claim 12, further comprising:

the control circuit is coupled to the channel selection circuit and used for detecting whether a channel in the M channels receives a leading signal or not so as to generate a clock selection signal, wherein when the control circuit detects that the channel in the M channels receives the leading signal, the channel selection circuit is used for selecting the channel in the M channels according to the clock selection signal.

18. The integrated circuit of claim 12, wherein the channel selection circuit is configured to select one of the M channels according to a clock selection signal; the integrated circuit further comprises:

a control circuit, coupled to the channel selection circuit, for generating the clock selection signal according to a channel identifier of the channel of the M channels, the clock selection signal having a signal value mapped to the channel identifier.

19. The integrated circuit of claim 12, wherein the channel selection circuit is configured to couple one of the (N-M) channels to one of the N sampling circuits according to a data selection signal; the integrated circuit further comprises:

a control circuit, coupled to the channel selection circuit, for generating the data selection signal having a signal value mapped to the channel identifier of the one of the (N-M) channels according to the channel identifier of the one of the (N-M) channels.

20. A physical layer of a receiver, comprising:

a physical medium connection layer having N first channels for selecting M of the N first channels as M first clock channels according to a first group of clock selection signals, and outputting M second clock signals respectively associated with M different clock domains according to M first clock signals on the M first clock channels, wherein M is an integer greater than 1;

a physical coding sublayer coupled to the physical medium connection layer and having N second channels, the physical coding sublayer being configured to select M of the N second channels as M second clock channels according to a second set of clock selection signals and receive the M second clock signals through the M second clock channels; and

and the control circuit is arranged on one of the physical medium connection layer and the physical coding sublayer and used for generating the first group of clock selection signals and the second group of clock selection signals according to control input.

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