CN112311405B - The integrated circuit in the physical layer of the receiver and the physical layer of the receiver - Google Patents

Abstract

The present application discloses an integrated circuit in the physical layer of a receiver and the physical layer of the receiver. The integrated circuit includes a multi-channel interface, a channel selection circuit and N sampling circuits. The multi-channel interface has N channels. The channel selection circuit is coupled to the multi-channel interface, and is used for selecting M channels among the N channels as M clock channels, and outputting M signals respectively on the M clock channels. M is a positive integer less than N. The remaining (N‑M) channels are used as (N‑M) data channels. The N sampling circuits are coupled to the multi-channel interface and the channel selection circuit. (N-M) sampling circuits in the N sampling circuits are respectively coupled to the (N-M) data channels. Each of the (N-M) sampling circuits samples a signal on a data channel of the (N-M) data channels according to one of the M signals. The integrated circuit is capable of supporting different channel configurations on the transmit side.

Description

The integrated circuit in the physical layer of the receiver and the physical layer of the receiver

technical field

The present application relates to clock forwarding interfaces, and more particularly to an integrated circuit in a clock forwarding interface receiver having channels that can be used interchangeably between clock and data channels, and The physical layer of the clock forwarding interface receiver.

Background technique

Certain communication systems utilize clock forwarding schemes to provide high-speed data transfer between transmitters and receivers. In this clock forwarding scheme, a clock signal is transmitted from a transmitter to a receiver along with one or more data signals. For example, the receiver may include a clock forwarding interface having a clock lane and a plurality of data lanes. A clock signal on the clock channel is forwarded from the transmitter to the receiver along with data signals on the plurality of data channels. Accordingly, the receiver may capture the plurality of data signals using the clock signal forwarded by the transmitter. Depending on the physical layer (PHY) specification used, each channel (ie, clock channel or data channel) in the clock forwarding interface may be point-to-point (point-to-point) for clock or data transmission. -point), two-wire or three-wire interface.

SUMMARY OF THE INVENTION

Embodiments of the present application disclose an integrated circuit in a clock forwarding interface receiver having a channel that can be used interchangeably between clock and data channels, and its associated physical layer.

Certain embodiments of the present application disclose a physical layer integrated circuit of a receiver. The integrated circuit includes a multi-channel interface, a channel selection circuit and N sampling circuits. N is an integer greater than 1. The multi-channel interface has N channels. The channel selection circuit is coupled to the multi-channel interface, and is used for selecting M channels among the N channels as M clock channels, and outputting M signals respectively on the M clock channels. M is a positive integer less than N. The remaining (N-M) channels are used as (N-M) data channels. The N sampling circuits are coupled to the multi-channel interface and the channel selection circuit. (N-M) sampling circuits in the N sampling circuits are respectively coupled to the (N-M) data channels. Each sampling circuit in the (N-M) sampling circuits is used for, according to one of the M signals on the M clock channels, a signal on a data channel of the (N-M) data channels. to sample.

Certain embodiments of the present application disclose a physical layer integrated circuit of a receiver. The integrated circuit includes a multi-channel interface, N sampling circuits and a channel selection circuit. N is an integer greater than 1. The multi-channel interface has N channels. The N sampling circuits are coupled to the multi-channel interface. Each of the N sampling circuits has a clock input terminal and a data input terminal. The channel selection circuit is used for selecting the M channels as M clock channels by coupling M channels of the N channels to the N clock input terminals of the N sampling circuits. M is a positive integer less than N. The remaining (N-M) channels are used as (N-M) data channels. In one mode, one of the N channels is selected as a clock channel coupled to one or more of the N clock inputs. In another mode, the selected channel among the N channels is used as one of the N data input terminals coupled to the N sampling circuits and not coupled to one of the N clock input terminals. data channel.

Certain embodiments of the present application disclose a physical layer of a receiver. The physical layer includes a physical medium attachment layer (PMA) and a physical coding sublayer (PCS). The physical medium connection layer is used for outputting M clock signals respectively related to M different clock domains. M is an integer greater than 1. The physical coding sublayer has N channels and is coupled to the physical medium connection layer. N is an integer greater than M. The physical coding sublayer is used to select M channels among the N channels as M clock channels, and receive the M clock signals through the M clock channels. One or more of the remaining (N-M) channels in the N channels are used as one or more data channels.

The physical layer on the receiving side can support different lane configurations on the transmitting side through at least one lane that can be used interchangeably between the clock lane and the data lane. For example, the physical layer may be divided into multiple physical interfaces to support multiple transmitters. In addition, a clock/data channel can be selected according to the channel identifier of the clock/data channel, so as to facilitate the selection of the clock/data channel.

Description of drawings

1 is a functional block diagram of an exemplary multi-channel communication system in accordance with certain embodiments of the present application.

2A-2C are schematic diagrams of different modes of the receiver shown in FIG. 1 according to some embodiments of the present application.

FIG. 3 is a schematic diagram of a specific implementation of the integrated circuit shown in FIG. 1 according to some embodiments of the present application.

4A-4C are schematic diagrams of operations of the integrated circuit shown in FIG. 3 according to some embodiments of the present application.

5A-5C are schematic diagrams of other specific implementations of the integrated circuit shown in FIG. 1 according to some embodiments of the present application.

FIG. 6 is a schematic diagram of another specific implementation of the integrated circuit shown in FIG. 1 according to some embodiments of the present application.

FIG. 7 is a schematic diagram of another specific implementation of the integrated circuit shown in FIG. 1 according to some embodiments of the present application.

FIG. 8 is a schematic diagram of another specific implementation of the integrated circuit shown in FIG. 1 according to some embodiments of the present application.

FIG. 9 is a schematic diagram of the operation of the state machine shown in FIG. 7 according to some embodiments of the present application.

FIG. 10 is a schematic diagram of a specific implementation of channel identifiers for the multiple channels shown in FIG. 7 according to some embodiments of the present application.

11 is a functional block diagram of an exemplary receiver in accordance with certain embodiments of the present application.

12 is a schematic diagram of an embodiment of an integrated circuit in the physical coding sublayer shown in FIG. 11 according to some embodiments of the present application.

13 is a schematic diagram of another embodiment of an integrated circuit in the physical coding sublayer shown in FIG. 11 according to some embodiments of the present application.

14 is a functional block diagram of an exemplary multi-channel communication system in accordance with certain embodiments of the present application.

Detailed ways

The following disclosure discloses various embodiments or illustrations that can be used to implement various features of the present disclosure. Specific examples of parameter values, components, and configurations are described below to simplify the content of this application. As can be appreciated, these descriptions are exemplary only, and are not intended to limit the content of this application. In addition, the present disclosure may reuse reference numerals and/or reference numerals in various embodiments. Such reuse is for brevity and clarity, and does not in itself represent a relationship between the different embodiments and/or configurations discussed.

Furthermore, it will be understood that if an element is described as being "connected to" or "coupled to" with another element, the two may be directly connected or coupled, or there may be Other intervening components.

The physical layer of the receiver using the clock forwarding interface can use a dedicated clock lane to receive the clock signal transmitted through the clock lane on the transmit side. However, in applications where the transmitter's clock channel and multiple data channels are used interchangeably with each other to meet certain communication requirements, this receiver will no longer be suitable. For example, the number of transport devices on the transport side may vary. For another example, the transmission device on the transmission side may use the clock channel and the data channel interchangeably in some operational situations.

The present application discloses an exemplary integrated circuit having channels interchangeable between clock and data channels in a clock forwarding interface receiver. In certain embodiments, the exemplary integrated circuit may be implemented in a sublayer of a physical layer of the clock forwarding interface receiver, such as a physical medium attachment layer (PMA) or a physical Coding sublayer (physical codingsublayer, PCS). With the exemplary integrated circuit, the clock forwarding interface receiver can accommodate the interchangeable use of clock lanes and data lanes to support different lane arrangements on the transmit side.

FIG. 1 is a functional block diagram of an exemplary multi-lane communication system according to some embodiments of the present application. The multi-channel communication system 100 includes K transmitters TX[0]-TX[K-1] on a transmit side TS and a receiver 104 on a receiver side RS, where K is a positive integer. Each of the K transmitters TX[0]-TX[K-1] may include a multi-channel interface (ie, one of the K multi-channel interfaces TF[0]-TF[K-1]) to Transmit clock information and data information. Each of the K multi-channel interfaces TF[0]-TF[K-1] may include at least one clock channel and at least one data channel (not shown in FIG. 1 ).

The receiver 104 is configured to communicate with each of the K transmitters TX[0]-TX[K-1] via a communication link 106. A physical layer 108 of receiver 104 may employ a clock forwarding scheme to receive clock information and data information transmitted over communication link 106 . Therefore, at least one clock signal can be forwarded from the transmitting side TS to the receiving side RS together with the at least one data signal. The physical layer 108 includes an integrated circuit 110 , which may be disposed in the physical medium connection layer or the physical coding sublayer of the physical layer 108 . The integrated circuit 110 can be adapted to various lane ranges/configurations of the transmission side TS. For example, the integrated circuit 110 may operate in a mode to communicate with the transmit-side TS, wherein the transmit-side TS uses a single channel as a clock channel to transmit a clock signal. The integrated circuit 110 may operate in another mode to communicate with the transmission side TS, wherein the transmission side TS uses multiple channels as multiple clock channels to transmit multiple clock signals.

In this embodiment, the integrated circuit 110 includes (but is not limited to) a multi-lane interface 114, a lane selection circuit 120 and N sampling circuits RX[0]-RX[N- 1], where N is an integer greater than 1. The multi-channel interface 114 is connected to each of the K multi-channel interfaces TF[0]-TF[K-1] through the communication link 106 . The multi-lane interface 114 includes N lanes LA[0]-LA[N-1]. At least one channel among the N channels LA[0]-LA[N-1] is interchangeable between the clock channel and the data channel, that is, the at least one channel can be between the clock channel and the data channel Used interchangeably.

The channel selection circuit 120 is coupled to the multi-channel interface 114 for selecting M channels among the N channels LA[0]-LA[N-1] as M clock channels, where M is a positive integer smaller than N. In addition, the channel selection circuit 120 may be configured to output M signals CK ₀ -CK _(M-1) (ie, M clock signals) on the M clock channels, respectively. The remaining (NM) channels can be used as (NM) data channels respectively. At least one of the (NM) data channels can carry data signals transmitted from the transmission side TS. In this embodiment, the M clock signals may be forwarded along with (NM) data signals (ie, (NM) signals DA0-DA _{( NM-1)} on the (NM) lanes) , so that each data channel can carry a data signal. It is worth noting that the channel selection circuit 120 can select any one of the N channels LA[0]-LA[N-1] as the clock channel. Each of the N channels LA[0]-LA[N-1] can be commonly used for the clock channel and the data channel.

In this embodiment, the channel selection circuit 120 includes (but is not limited to) a plurality of selection stages 122 and 124 . The selection stage 122 has an input side S1 and an output side S2. The input side S1 is coupled to the multi-channel interface 114 . The selection stage 122 is used for coupling the M signals CK ₀ -CK _(M-1) on the M clock channels from the input side S1 to the output side S2. The selection stage 124 is disposed between the output side S2 and the N sampling circuits RX[ ₀ ]-RX[N-1], for coupling each of the M signals CK0-CK _(M-1) to N One or more of the sampling circuits RX[0]-RX[N-1]. For example, the selection stage 122 may be implemented as an N-to-M multiplexer, which may couple M of the N channels LA[0]-LA[N-1] to Output side S2. The selection stage 124 may be implemented as M clock trees CT, where each clock tree may assign a clock signal (ie, one of the M signals CK0-CK _{( M-1)} ) to more than one sample circuit.

The N sampling circuits RX[0]-RX[N-1] are coupled to the multi-channel interface 114 and the channel selection circuit 120 to perform data sampling according to the clock information and data information transmitted from the transmission side TS. In this embodiment, each of the N sampling circuits RX[0]-RX[N-1] is used to receive M signals CK ₀ -CK _(M-1) on the M clock channels, wherein one of. In addition, (NM) sampling circuits among the N sampling circuits RX[0]-RX[N-1] are respectively coupled to the (NM) data channels for receiving the (NM) data channels (NM) signals DA ₀ -DA _(NM-1) . Each of the (NM) sampling circuits is configured to, according to one of the M signals CK ₀ -CK _(M-1) , pair one of the (NM) signals DA ₀ -DA _(NM-1) to sample.

For example (but the present application is not limited thereto), each of the N sampling circuits RX[0]-RX[N-1] may include a clock input terminal C _IN and a data input terminal D _IN . Each sampling circuit uses the signal input to the corresponding clock input terminal C _IN to sample the signal input to the corresponding data input terminal D _IN . By coupling M channels among the N channels LA[0]-LA[N-1] to the N clock input terminals C _IN of the N sampling circuits RX[0]-RX[N-1], the channel selection The circuit 120 may select the M channels among the N channels LA[0]-LA[N-1] as the M clock channels. Each of the remaining (NM) channels can be coupled to a data input terminal D _IN but not coupled to the N clock input terminals C _IN , thereby serving as a data channel. Therefore, when each sampling circuit is coupled to a data channel through its data input terminal D _IN and is coupled to a clock channel through its included clock input terminal C _IN , the sampling circuit can utilize the clock channel to sample the signal on the data channel. In some embodiments, a clock channel can be coupled to one or more clock input terminals of the N clock input terminals C _IN , so that multiple sampling circuits can perform data sampling according to the same clock signal.

The sampling results SR output by the N sampling circuits RX[0]-RX[N-1] include clock information and data information, which can be transmitted to the output circuits of the integrated circuit 110 including other functional blocks (not shown in FIG. 1 ) 140 for further processing. For example, a sampling circuit simultaneously coupled to one of the M signals CK ₀ -CK _(M-1) and one of the (NM) signals DA ₀ -DA _(NM-1) can output a The data signal, which can be part of the sampling result SR. A sampling circuit coupled to one of the M signals CK ₀ -CK _(M-1) but not coupled to the (NM) signals DA ₀ -DA _(NM-1) can output a clock signal, the The clock signal can be used as another part of the sampling result SR. The output circuit 140 can output M clock signals and (NM) data signals according to the sampling result SR. In some embodiments, the output circuit 140 may include a deserializer block. Each of the M clock signals and the (NM) data signals output from the output circuit 140 may be a multi-bit parallel output signal.

In some embodiments, the transmitter may provide information to indicate which channel should be used as a clock channel. Based on the information provided by the transmitter, the receiver 104 may configure/configure the channel selection circuit 120 to select the appropriate channel as the clock channel. The receiver 104 can properly use the signal on the clock channel to process the signal on one or more data channels.

In some embodiments, the transmitter may generate a clock signal by repeating a specific bit pattern, thereby indicating which channel on the RS on the transmission side should be used as a clock channel. For example, the transmitter may repeatedly transmit a one-bit pattern "01", such as "01010101", as a clock signal. The receiver 104 can identify which channel can be used as the clock channel by checking whether a bit stream received by a channel has a repeated bit pattern. That is, the receiver 104 can configure/set the channel selection circuit 120 according to the detection result of a predetermined repeated bit pattern.

In some embodiments, a system application (not shown in FIG. 1 ) associated with receiver 104 may determine which channel of multi-channel interface 104 should act as a clock channel. According to the instructions sent by the system application, the receiver 104 can configure/set the channel selection circuit 120 to select an appropriate channel as the clock channel.

Please note that the above description is for illustrative purposes only and is not intended to limit the scope of this application. In some embodiments, the channel selection circuit 120 shown in FIG. 1 may be implemented by a single selection stage or more than two selection stages without departing from the scope of this application. In some embodiments, at least one of the N sampling circuits RX[0]-RX[N-1] shown in FIG. 1 may be implemented with a sampling circuit having more than one data output.

The physical layer 108 of the RS on the receiving side can support different channel configurations of the TS on the transmitting side through at least one channel that can be used interchangeably between the clock channel and the data channel. In order to further illustrate the lane interchange scheme of the RS on the receiving side, some embodiments of the lane configuration of the TS on the transmitting side are provided below. Those skilled in the art should understand that the channel interchange scheme of the RS on the receiving side can support other channel configurations of the TS on the transmitting side, without departing from the scope of the present application.

2A-2C are schematic diagrams of different modes of the receiver 104 shown in FIG. 1 according to some embodiments of the present application. The receiver 104 may operate in different modes OP1-OP3 respectively according to different channel configurations of the TS on the transmission side. In the mode OP1 shown in FIG. 2A, the receiver 104 can be used to receive clock information and data information provided by a single transmitter. For convenience of description, the single transmitter can be represented by the transmitter TX[0] shown in FIG. 1 . The multi-channel interface TF[0] of the transmitter TX[0] includes a plurality of channels L0[0]-L0[P], where P is a positive integer. The transmitter TX[0] is used to combine the clock signal C0 on the channel L0[P] together with the P data signals D0 ₀ -D0 _(P-1) on the P channels L0[0]-L0[P-1]. and output.

The receiver 104 is used to select one of the N channels LA[0]-LA[N-1] as a clock channel (ie, M=1) to receive the clock signal C0 through the communication link 106 . P channels among the remaining (N-1) channels can be used as P data channels to receive P data signals D0 ₀ -D0 _(P-1) . In this embodiment, the sum of the number of data signals and the number of clock signals transmitted from the transmitter TX[0] may be equal to the number of channels of the multi-channel interface 114 (ie, P+1=N) . Therefore, each of the N channels LA[0]-LA[N-1] can be used to receive the signal information provided by the transmission side TX[0]. Receiver 104 may select channel LA[N-1] (ie, the channel on which the clock signal C0 on channel L0[P] is input) as the clock channel. The remaining (N-1) channels LA[0]-LA[N-2] can be used as (N-1) data channels to receive P data signals D0 ₀ -D0 _(P-1) .

In the mode OP2 shown in FIG. 2B , the receiver 104 can be used to receive clock information and data information provided by multiple transmitters, wherein multiple channels of the transmission side TS can be used as multiple clock channels to carry multiple clock signals. For example, when operating in a bifurcation mode, the physical layer 108 may be divided into a plurality of physical layers different from each other to support the K transmitters TX[0]-TX[K-1] shown in FIG. multiple transmitters. For the convenience of description, in this embodiment, the plurality of transmitters can be represented by two transmitters TX[1] and TX[2]. The multi-channel interface TF[1] of the transmitter TX[1] includes a plurality of channels L1[0]-L0[Q], where Q is a positive integer. The transmitter TX[1] is used to convert the clock signal C1 on the channel L1[Q] together with the Q data signals D1 ₀ -D1 _(Q-1) on the Q channels L1[0]-L1[Q-1]. and output. The multi-channel interface TF[2] of the transmitter TX[2] includes a plurality of channels L2[0]-L2[R], where R is a positive integer. The transmitter TX[2] is used to combine the clock signal C2 on the channel L2[R] together with the R data signals D2 ₀ -D2 _(R-1) on the R channels L2[0]-L2[R-1]. and output. Since both channels of the transmission side TS are used as clock channels in the mode OP2, the channel configuration of the transmission side TS in the mode OP2 is different from the channel configuration of the transmission side TS in the mode OP1 (it uses a single channel as the clock channel) .

In response to the mode OP2, the receiver 104 can select two channels among the N channels LA[0]-LA[N-1] as two clock channels (ie, M=2) to receive the data transmitted by the transmission side TS A plurality of clock signals C1 and C2. (Q+R) of the remaining (N-2) channels can be used as (Q+R) data channels to receive multiple data signals D1 ₀ -D1 _(Q-1) and D2 ₀ -D2 _{( R-1)} . In this embodiment, the sum of the number of data signals and the number of clock signals transmitted from the plurality of transmitters TX[1] and TX[2] may be equal to the number of channels of the multi-channel interface 114 ( That is, Q+R+2=N). Therefore, each of the N channels LA[0]-LA[N-1] can be used to receive signal information provided by a plurality of transmitters TX[1] and TX[2]. The receiver 104 may select the two channels LA[J] and LA[N-1] (ie, the channels to which the plurality of clock signals C1 and C2 are input) as the two clock channels. J is an integer between 0 and N-2. The remaining (N-2) channels can be used as (N-2) data channels to receive a plurality of data signals D1 ₀ -D1 _(Q-1) and D2 ₀ -D2 _(R-1) . Since channel LA[J] can function as a data channel in mode OP1 and a clock channel in mode OP2, integrated circuit 110 can support not only a single transmitter, but also multiple transmitters.

In some embodiments, one or more transmitters have channels that can be used interchangeably between data channels and clock channels to provide different channel configurations on the transmit side TS. For example, in the mode OP3 shown in FIG. 2C, the receiver 104 can be used to receive clock information and data information provided by the transmitter TX[0], which can transmit from the channel L0[0] The clock signal C0, and the P data signals D0 ₀ -D0 _(P-1) are transmitted from the P channels L0[1]-L0[P]. Compared to the mode OP1, the transmitter TX[0] can cause the signals transmitted on the clock channel and on the data channel to be interchanged with each other. Therefore, channel L0[0], which is a data channel in mode OP1, can be a clock channel in mode OP3, and channel L0[P], which is a clock channel in mode OP1, can be a data channel in mode OP3. The receiver 140 may select channel LA[0] as the clock channel to receive the clock signal C0. P channels among the remaining (N-1) channels LA[1]-LA[N-1] can be used as P data channels to receive P data signals D0 ₀ -D0 _(P-1) . By using lanes LA[0] and lanes LA[N-1] interchangeably between data lanes and clock lanes, respectively, integrated circuit 110 may support a transmitter TX[0] capable of interchangeably using clock lanes and data lanes .

In order to facilitate the understanding of the content of the present application, some embodiments are provided below to further describe the clock forwarding interface receiver adopting the channel interchange scheme. Those skilled in the art should understand that other embodiments of the channel interchange scheme described based on the integrated circuit 110 or the receiver 104 shown in FIG. 1 all follow the spirit of the present application and fall within the protection scope of the present application.

FIG. 3 is a schematic diagram of a specific implementation of the integrated circuit 110 shown in FIG. 1 according to some embodiments of the present application. The integrated circuit 310 is disposed in the physical layer of the receiver 300, such as the physical medium connection layer, to receive clock information and data information transmitted by one or more transmitters on the transmission side. The integrated circuit 310 can be used as an embodiment of the integrated circuit 110 shown in FIG. 1 (which includes six channels that can be commonly used for clock channels and data channels, N=6). In this embodiment, the integrated circuit 310 may include a plurality of sampling circuits RX[0]-RX[5] shown in FIG. 1 , a multi-channel interface 314 and a channel selection circuit 320 . The multi-channel interface 314 and the channel selection circuit 320 can be respectively used as embodiments of the multi-channel interface 114 and the channel selection circuit 120 shown in FIG. 1 .

In this embodiment, each of the multiple lanes LA[0]-LA[5] of the multi-lane interface 314 can be implemented using a two-wire lane. A two-lane channel is a differential lane including a pair of signal pins and an amplifier. In certain embodiments, each of the plurality of channels LA[0]-LA[5] may be implemented with other types of channels, such as single-wire channels or channels with more than two wires, without departing from the teachings of the present application scope.

The channel selection circuit 320 is used for selecting one or more channels among the plurality of channels LA[0]-LA[5] as one or more clock channels. The channel selection circuit 320 may include a plurality of selection stages 322 and 324, which may be embodiments of the plurality of selection stages 122 and 124 shown in FIG. 1, respectively. In this embodiment, selection stage 322 may couple one or both channels to selection stage 324 in response to the mode of integrated circuit 310 . The selection stage 322 includes, but is not limited to, a plurality of channel selection units 322.0 and 322.1. The channel selection unit 322.0 is used for coupling a plurality of channels LA[0]-LA[2] from the input side S01 to the output side S02 according to a clock selection signal _SEL00 . The channel selection unit 322.1 is used for coupling a plurality of channels LA[3]-LA[5] from the input side S11 to the output side S12 according to a clock selection signal _SEL01 .

Selection stage 324 may distribute the signal on each channel selected by selection stage 322 to more than one sampling circuit. The selection stage 324 includes, but is not limited to, a plurality of channel selection units 324.0-324.5. Each of the plurality of channel selection units 324.0-324.5 can be coupled to the corresponding sampling circuits according to the corresponding clock selection signal (ie, one of the plurality of clock selection signals _SEL10 - _SEL15 ). The description of the plurality of clock select signals SEL ₀₀ , SEL ₀₁ and SEL ₁₀ -SEL ₁₅ will be described later.

The respective clock input terminals C _IN of the multiple sampling circuits RX[0]-RX[5] are respectively coupled to the respective output terminals of the multiple channel selection units 324.0-324.5. The respective data input terminals D _IN of the plurality of sampling circuits RX[0]-RX[5] are respectively coupled to the plurality of channels LA[0]-LA[5]. In this embodiment, each sampling circuit in the plurality of sampling circuits RX[0]-RX[5] can utilize a flip-flop (such as a D-type flip-flop) to Implemented for data sampling. Those skilled in the art should understand that each sampling circuit of the plurality of sampling circuits RX[0]-RX[5] can be implemented using other types of sampling circuits without departing from the scope of the present application.

4A-4C are schematic diagrams of operations of the integrated circuit 310 shown in FIG. 3 according to some embodiments of the present application. In the embodiment shown in FIGS. 4A and 4B , the integrated circuit 310 operates in a mode similar to the mode OP1/OP3 shown in FIGS. 2A/2C to receive a single clock signal from the multi-channel interface 314 . The channel selection circuit 320 may select one of the multiple channels LA[0]-LA[5] as a clock channel to receive the clock signal. The channel selection circuit 320 is used for coupling the signal on the clock channel (ie, the clock signal) to each sampling circuit in the plurality of sampling circuits RX[0]-RX[5]. In the embodiment shown in FIG. 4C , the integrated circuit 310 operates in a mode similar to the mode OP2 shown in FIG. 2B to receive multiple clock signals from the multi-channel interface 314 . The channel selection circuit 320 may select two channels among the plurality of channels LA[0]-LA[5] as two clock channels to receive the plurality of clock signals. The channel selection circuit 320 is used for coupling the signal on each clock channel to one or more sampling circuits among the plurality of sampling circuits RX[0]-RX[5].

Referring first to FIG. 4A , the integrated circuit 310 may support a “5D1C” channel configuration, in which a clock signal 5D_CLK is input to one of the multiple channels LA[0]-LA[2] (in this embodiment, a clock signal 5D_CLK is input to Take channel LA[0] as an example to illustrate). Five data signals 5D ₀ - 5D ₄ are input to the remaining five channels. The channel selection unit 322.0 couples the channel LA[0] to the output side S02 according to the clock selection signal SEL ₀₀ to select the channel LA[0] as the clock channel. The multiple channels LA[1] and LA[2] are not coupled to the output side S02. In addition, each of the plurality of channel selection units 324.0-324.5 can couple the output side S02 of the channel selection unit 322.0 to the corresponding sampling circuit according to the corresponding clock selection signal. Therefore, the clock signal 5D_CLK can be transmitted to the respective clock input terminals C _IN of the plurality of sampling circuits RX[0]-RX[5]. The plurality of sampling circuits RX[1]-RX[5] respectively coupled to the plurality of channels LA[1]-LA[5] can sample the plurality of data signals _5D0-5D4 according to the clock signal _{5D_CLK} .

Referring to FIG. 4B , the integrated circuit 310 may support a “5D1C” channel configuration, in which the clock signal 5D_CLK is input to one of the multiple channels LA[3]-LA[5] (in this embodiment, the clock signal 5D_CLK is input to the channel LA [3] as an example to illustrate). A plurality of data signals 5D ₀ - 5D ₄ are input to the remaining five channels. The channel selection unit 322.1 couples the channel LA[3] to the output side S12 according to the clock selection signal SEL ₀₁ , so as to select the channel LA[3] as the clock channel. Each of the plurality of channel selection units 324.0-324.5 can couple the output side S12 of the channel selection unit 322.1 to the corresponding sampling circuit. Therefore, a plurality of sampling circuits RX[0]-RX[2], RX[4] and RX[ are respectively coupled to the plurality of channels LA[0]-LA[2], LA[4] and LA[5] 5] The plurality of data signals 5D ₀ - 5D ₄ may be sampled according to the clock signal 5D_CLK.

Referring to FIG. 4C, the integrated circuit 310 can be used as two circuit interfaces, both of which can support a "2D1C" channel configuration (two channels as data channels and one channel as clock channel). In this embodiment, a clock signal 2D_CLK0 is input to one of the plurality of channels LA[0]-LA[2], such as channel LA[0]. The associated data signals 2D ₀₀ and 2D ₀₁ can be input to the remaining two channels. In addition, a clock signal 2D_CLK1 is input to one of a plurality of channels LA[3]-LA[5], such as channel LA[3]. The associated data signals 2D ₁₀ and 2D ₁₁ can be input to the remaining two channels.

The channel selection unit 322.0 is used for coupling the channel LA[0] to the output side S02 according to the clock selection signal _SEL00 . Each of the plurality of channel selection units 324.0-324.2 is used for coupling the output side S02 to the corresponding sampling circuit according to the corresponding clock selection signal. Therefore, the plurality of sampling circuits RX[1] and RX[2] respectively coupled to the plurality of channels LA[1] and LA[2] can sample the plurality of data signals 2D ₀₀ and 2D ₀₁ according to the clock signal 2D_CLK0. Similarly, the channel selection unit 322.1 is used to couple the channel LA[3] to the output side S12 according to the clock selection signal _SEL01 . Each of the plurality of channel selection units 324.3-324.5 is used for coupling the output side S12 to the corresponding sampling circuit according to the corresponding clock selection signal. Therefore, the plurality of sampling circuits RX[4] and RX[5] respectively coupled to the plurality of channels LA[4] and LA[5] can sample the plurality of data signals 2D ₁₀ and 2D ₁₁ according to the clock signal 2D_CLK1. Since the signal level/signal value of each clock selection signal in the plurality of clock selection signals _SEL10 - _SEL12 may be different from the signal level/signal value of each clock selection signal in the plurality of clock selection signals _SEL13 - _SEL15 Therefore, the multiple channel selection units 324.0-324.5 can distribute different clock signals 2D_CLK0 and 2D_CLK1 to the multiple sampling circuits RX[0]-RX[5].

4A and 4B, the selection stage 322 and the selection stage 324 shown in FIG. 3 can be used as a 6-to-1 multiplexer (6-to-1 multiplexer) and a clock tree, respectively, to support " 5D1C” channel configuration. Furthermore, by the selection operation described with reference to FIG. 4C, the selection stage 322 shown in FIG. 3 may function as two 3-to-1 multiplexers, and the selection stage 324 shown in FIG. 3 may function as two a clock tree to support "2D1C" channel configuration in bifurcated mode. Thus, the channel selection circuit 320 shown in FIG. 3 can support one or more transmitters by operating as a 6-to-M multiplexer and M clock trees, where M can be equal to 1 or 2 (depending on the mode of integrated circuit 310).

Please note that the circuit structures of the plurality of selection stages 322 and 324 shown in FIG. 3 are only for the purpose of convenience of description, and are not intended to limit the scope of the present application. In some embodiments, the selection stage 322 may be implemented by other circuit structures to provide operation of a multiplexer. In some embodiments, the selection stage 324 may be implemented by other circuit structures to construct one or more clock trees. In some embodiments, the signal (such as a clock signal) on each selected clock channel may not be coupled to the data input terminal D _IN of each sampling circuit. For example, when the channel LA[0] shown in FIG. 3 is selected as the clock channel, the channel LA[0] may not be coupled to the data input terminal D _IN of each sampling circuit.

In some embodiments, multiple clock select signals SEL ₁₀ -SEL ₁₂ may be implemented with the same clock select signal, or may have the same signal value. In some embodiments, multiple clock select signals SEL ₁₃ -SEL ₁₅ may be implemented with the same clock select signal, or may have the same signal value. These design modifications and changes all follow the spirit of the present application and fall into the protection scope of the present application.

5A to 5C are schematic diagrams of other specific implementations of the integrated circuit 110 shown in FIG. 1 according to some embodiments of the present application. Each of the plurality of integrated circuits 510A-510C shown in FIGS. 5A to 5C can be used as the integrated circuit 110 shown in FIG. 1 (which includes six channels that can be commonly used for clock channels and data channels, N=6) example. In these embodiments, the channel selection circuit 120 shown in FIG. 1 may be implemented using different clock tree groups to support different channel configurations on the transmission side. Each clock tree group includes at least one clock tree circuit, and a clock tree circuit includes a multiplexer and a clock tree.

See first Figure 5A. Except for the channel selection circuit 520A, the structure of the integrated circuit 510A is similar/same as the structure of the integrated circuit 310 shown in FIG. 3 . The circuit operation provided by the channel selection circuit 520A may be similar/same as the circuit operation of the channel selection circuit 320 described with reference to FIGS. 4A/4B. In this embodiment, the channel selection circuit 520A may be implemented using a clock tree group G1. The clock tree group G1 has a clock tree circuit including a multiplexer 522A (ie, a 6-to-1 multiplexer) and a clock tree 524A. The multiplexer 522A can select one of the plurality of channels LA[0]-LA[5] as a clock channel according to a clock selection signal SEL _A , so as to output the signal on the selected channel from an output terminal _T5D . Clock tree 524A may distribute the signal on output T _5D to each of the plurality of sampling circuits RX[0]-RX[5]. Please note that the circuit structure of the selection stage 322 shown in FIGS. 4A/4B can be used as an implementation of the multiplexer 522A. Additionally, or alternatively, the circuit structure of the selection stage 324 shown in FIGS. 4A/4B may be used as an implementation of the clock tree 524A. Since those skilled in the art should be able to understand the details of the operation of the channel selection circuit 520A shown in Further description is omitted here.

See Figure 5B. Except for the channel selection circuit 520B, the structure of the integrated circuit 510B is similar/same as the structure of the integrated circuit 310 shown in FIG. 3 . The circuit operation provided by the channel selection circuit 520B may be similar/same as the circuit operation of the channel selection circuit 320 described with reference to FIG. 4C. In this embodiment, the channel selection circuit 520B can be implemented using a clock tree group G2. The clock tree group G2 has two clock tree circuits, one clock tree circuit includes a multiplexer 522B.0 and a clock tree 524B.0, and the other clock tree circuit includes a multiplexer 522B.1 and a clock tree 524B.1. The multiplexer 522B.0 (ie, a 3-to-1 multiplexer) can select one of the multiple channels LA[0]-LA[2] as a clock channel according to a clock selection signal SEL _B0 . Clock tree 524B.0 may distribute the signal on output T _2D0 to each of the plurality of sampling circuits RX[0]-RX[2]. The multiplexer 522B.1 (ie, a 3-to-1 multiplexer) can select one of the multiple channels LA[3]-LA[5] as a clock channel according to a clock selection signal SEL _B1 . Clock tree 524B.1 may distribute the signal on output T _2D1 to each of the plurality of sampling circuits RX[3]-RX[5]. Please note that the circuit structure of the selection stage 322 shown in FIG. 4C can be used as an implementation of multiple multiplexers 522B.0 and 522B.1. Additionally, or alternatively, the circuit structure of the selection stage 324 shown in FIG. 4C may be implemented as a plurality of clock trees 524B.0 and 524B.1. Since those skilled in the art should be able to understand the details of the operation of the channel selection circuit 520B shown in FIG. 5B in the “2D1C” channel configuration after reading the paragraph descriptions related to FIG. 3 and FIG. 4C , further descriptions about channel selection are in This will not be repeated here.

See Figure 5C. Except for the channel selection circuit 520C, the structure of the integrated circuit 510C is similar/same as the structure of the integrated circuit 310 shown in FIG. 3 . The channel selection circuit 520C may be implemented using a clock tree group G3. The clock tree group G3 has three clock tree circuits, thereby supporting the transmission side where three clock channels and their associated three data channels are provided. In this embodiment, the channel selection circuit 520C includes multiple multiplexers 522C.0-522C.2 (ie, multiple 2-to-1 multiplexers) and multiple clock trees 524C.0-524C.2. The multiplexer 522C.0 may select one of the multiple channels LA[0] and LA[1] as a clock channel according to a clock selection signal SEL _C0 . The multiplexer 522C.1 can select one of the multiple channels LA[2] and LA[3] as a clock channel according to a clock selection signal SEL _C1 . The multiplexer 522C.2 can select one of the multiple channels LA[4] and LA[5] as a clock channel according to a clock selection signal SEL _C2 . Clock tree 524C.0 may distribute the signal on output T _1D0 to each of the plurality of sampling circuits RX[0] and RX[1]. Clock tree 524C.1 may distribute the signal on output _T1D1 to each of the plurality of sampling circuits RX[2] and RX[3]. Clock tree 524C.2 may distribute the signal on output _T1D2 to each of the plurality of sampling circuits RX[4] and RX[5].

For example, multiplexers 522C.0-522C.2 may select multiple lanes LA[0], LA[2], and LA[4] as multiple clock lanes. Therefore, the sampling circuit RX[1] can sample the signal on the channel LA[1] according to the signal on the channel LA[0]. The sampling circuit RX[3] can sample the signal on the channel LA[3] according to the signal on the channel LA[2]. The sampling circuit RX[5] can sample the signal on the channel LA[5] according to the signal on the channel LA[4]. The integrated circuit 510C can be divided into three interfaces, and each interface can support the "1D1C" channel configuration (one channel can be used as a clock channel, and the other channel can be used as a data channel).

FIG. 6 is a schematic diagram of another specific implementation manner of the integrated circuit 110 shown in FIG. 1 according to some embodiments of the present application. The integrated circuit 610 can be used as an embodiment of the integrated circuit 110 shown in FIG. 1 (which includes six channels that can be commonly used for clock channels and data channels, N=6). In this embodiment, the integrated circuit 610 may employ multiple clock tree groups G1-G3 shown in FIGS. 5A-5C to support different channel configurations. The integrated circuit 610 includes a channel selection circuit 620 and the multi-channel interface 314 shown in FIG. 3 and a plurality of sampling circuits RX[0]-RX[5]. The channel selection circuit 620 may be an embodiment of the channel selection circuit 120 shown in FIG. 1 and may include a plurality of selection stages 622 and 624 .

The selection stage 622 may include the multiplexer 522A of the clock tree group G1 shown in FIG. 5A , the multiplexers 522B.0 and 522B.1 of the clock tree group G2 shown in FIG. 5B , and the multiplexers 522B.0 and 522B.1 of the clock tree group G2 shown in FIG. 5C . A plurality of multiplexers 522C.0-522C.2 of the clock tree group G3. The selection stage 624 may include a plurality of multiplexers 624.0-624.5. The multiplexer 624.0 is used for coupling one of the output terminals T _5D , T _2D0 and T _1D0 to the clock input terminal C _IN of the sampling circuit RX[0]. The multiplexer 624.1 is used for coupling one of the output terminals T _5D , T _2D0 and T _1D0 to the clock input terminal C _IN of the sampling circuit RX[1]. The multiplexer 624.2 is used for coupling one of the output terminals T _5D , T _2D0 and T _1D1 to the clock input terminal C _IN of the sampling circuit RX[2]. The multiplexer 624.3 is used for coupling one of the output terminals T _5D , T _2D1 and T _1D1 to the clock input terminal C _IN of the sampling circuit RX[3]. The multiplexer 624.4 is used for coupling one of the output terminals T _5D , T _2D1 and T _1D2 to the clock input terminal C _IN of the sampling circuit RX[4]. The multiplexer 624.5 is used for coupling one of the output terminals T _5D , T _2D1 and T _1D2 to the clock input terminal C _IN of the sampling circuit RX[5].

In the mode in which the integrated circuit 610 is used to support the "5D1C" channel configuration, each of the multiplexers 624.0-624.5 is used to couple the output terminal T _5D to the corresponding sampling circuit so that the output terminal T _5D is on the output terminal T 5D. The clock signal 5D_CLK can be distributed to each sampling circuit. For example, the multiplexer 522A can couple the channel LA[0] to the output terminal T _5D according to the clock selection signal SEL _A. The remaining multiple channels LA[1]-LA[5] can be used as data channels. The plurality of sampling circuits RX[1]-RX[5] respectively coupled to the plurality of channels LA[1]-LA[5] can perform data sampling operations according to the clock signal 5D_CLK. Note that multiple multiplexers 624.0-624.5, which can act as a clock tree to distribute the clock signal 5D_CLK, can be used to implement the clock tree 524A in the clock tree group G1 shown in FIG. 5A.

In another mode in which the integrated circuit 610 is used to support "2D1C" lane configurations with bifurcation, each of the multiplexers 624.0-624.2 is used to couple the output T _2D0 to the corresponding The sampling circuit enables the clock signal 2D_CLK0 on the output terminal T _2D0 to be distributed to each sampling circuit in the plurality of sampling circuits RX[0]-RX[2]. Each of the multiplexers 624.3-624.5 is used to couple the output terminal _T2D1 to the corresponding sampling circuit, so that the clock signal _{2D_CLK1} on the output terminal T2D1 can be distributed to the multiple sampling circuits RX[3]- Each sampling circuit in RX[5]. Multiple multiplexers 624.0-624.5 may be used to implement multiple clock trees 524B.0 and 524B.1 in clock tree group G2 shown in FIG. 5B. Therefore, the plurality of sampling circuits RX[0]-RX[5] can be divided into two groups of sampling circuits. The physical layer where the integrated circuit 610 is located is operable as two separate physical layers, wherein one physical layer includes a plurality of channels LA[0]-LA[2] and a plurality of sampling circuits RX[0]-RX[2] , another physical layer includes multiple channels LA[3]-LA[5] and multiple sampling circuits RX[3]-RX[5].

In another mode in which the integrated circuit 610 is used to support the "1D1C" bifurcated channel configuration, each of the multiplexers 624.0 and 624.1 is used to couple the output _T1D0 to the corresponding sampling circuit so that the output The clock signal _{1D_CLK0} on the terminal T1D0 may be distributed to each of the plurality of sampling circuits RX[0] and RX[1]. Similarly, each of the multiplexers 624.2 and 624.3 is used to couple the output terminal _T1D1 to the corresponding sampling circuit, so that the clock signal _{1D_CLK1} on the output terminal T1D1 can be distributed to the multiple sampling circuits RX[ 2] and each sampling circuit in RX[3]. Each of the multiplexers 624.4 and 624.5 is used for coupling the output terminal _T1D2 to the corresponding sampling circuit, so that the clock signal _{1D_CLK2} on the output terminal T1D2 can be distributed to the multiple sampling circuits RX[4] and RX[4] and Each sampling circuit in RX[5]. Multiple multiplexers 624.0-624.5 may be used to implement multiple clock trees 524C.0-524C.2 in clock tree group G3 shown in Figure 5C. Therefore, the plurality of sampling circuits RX[0]-RX[5] can be divided into three groups of sampling circuits. The physical layer in which integrated circuit 610 resides is operable as three separate physical layers to support three transmitters.

With multiple multiplexers 522A, 522B.0, 522B.1, and 522C.0-522C.2, selection stage 622 is operable as 6 pairs of M multiplexers, where and M may be equal to 1, 2, or 3 (depending on mode of integrated circuit 610). Furthermore, through multiple multiplexers 624.0-624.5, the selection stage 624 can operate into M clock trees, where and M can be equal to 1, 2, or 3 (depending on the mode of the integrated circuit 610). Therefore, the integrated circuit 610 may divide the plurality of lanes LA[0]-LA[5] into one or more groups of lanes, wherein each lane group includes a clock lane and a data lane to support one or more lanes Transmitter.

The circuit structure and operations described above with reference to FIG. 6 are only for the purpose of convenience of description, and are not intended to limit the scope of the present application. In certain embodiments, integrated circuit 610 is operable in a bifurcated mode that supports both a "3D1C" channel configuration and a "1D1C" channel configuration. For example, the multiplexers 624.0-624.3 can couple the output terminal _T5D to the corresponding sampling circuit, so that the clock signal _{5D_CLK} on the output terminal T5D can be distributed to the multiple sampling circuits RX[0]-RX[ 3] in each sampling circuit. Each of the multiplexers 624.4 and 624.5 is used for coupling the output terminal _T1D2 to the corresponding sampling circuit, so that the clock signal _{1D_CLK2} on the output terminal T1D2 can be distributed to the multiple sampling circuits RX[4] and RX[4] and Each sampling circuit in RX[5]. Therefore, the physical layer in which the integrated circuit 610 is located is operable as two separate physical layers to support two transmitters with different numbers of data channels.

In some embodiments, it is also feasible not to use a channel as a data channel when performing data transmission. For example, when used to support the "5D1C" channel configuration, the integrated circuit 610 can use five or less data channels to receive data information transmitted by the transmission side. The number of data channels used may depend on the number of data signals communicated to the multi-channel interface 314 .

In some embodiments, selection stage 622 may be implemented using other multiplexer circuits to select one or more channels in response to the mode of integrated circuit 610 . In some embodiments, selection stage 624 may be implemented using other clock tree structures to distribute one or more clock signals in response to the mode of integrated circuit 610 . These design modifications and changes all follow the spirit of the present application and fall into the protection scope of the present application.

FIG. 7 is a schematic diagram of another specific implementation manner of the integrated circuit 110 shown in FIG. 1 according to some embodiments of the present application. The integrated circuit 710 can be used as an embodiment of the integrated circuit 110 shown in FIG. 1 (which includes six channels that can be commonly used for clock channels and data channels, N=6). In this embodiment, the integrated circuit 710 may be disposed at the physical medium connection layer in the physical layer to perform serial-to-parallel conversion.

The integrated circuit 710 includes a channel selection circuit 720, a plurality of serial-to-parallel converters (hereinafter referred to as "S2P converters") 730.0-730.5, and the multi-channel interface 314 shown in FIG. 3 . The channel selection circuit 720 may be an embodiment of the channel selection circuit 120 shown in FIG. 1 and may include a plurality of selection stages 722 and 724 . The selection stage 722 may include a plurality of multiplexers 722.0 and 722.1. The multiplexer 722.0 is used for coupling a plurality of channels LA[0]-LA[5] to an output terminal _T70 according to a clock selection signal _SEL70 . The multiplexer 722.0 is used for coupling a plurality of channels LA[0]-LA[5] to an output terminal _T71 according to a clock selection signal _SEL71 . Selection stage 724 may be implemented to include a multiplexer 724.0, which may couple multiple outputs _T70 and _T71 to an output _T72 according to a clock selection signal _SEL72 .

Each of the plurality of S2P converters 730.0-730.5 is used to output a multi-bit parallel output signal. The multi-bit parallel output signal may be a parallel data signal, a byte data signal, a parallel clock signal or a byteclock signal. In this embodiment, each S2P converter includes a sampling circuit and a deserializer (ie, one or more of the sampling circuits RX[0]-RX[5] shown in FIG. One of the deserializers DS[0]-DS[5]). The plurality of deserializers DS[0]-DS[5] can be used as an output circuit 740, which can output one or more clock signals according to the sampling results SR of the plurality of sampling circuits RX[0]-RX[5].

In the mode in which the integrated circuit 710 is used to support the " _5D1C " channel configuration, the multiplexer 724.0 is used to couple the output terminal T70 to the output terminal _T72 . When the multiplexer 722.0 selects one of the multiple channels LA[0]-LA[5] as a clock channel, the signal on the clock channel can be coupled to the output terminal T ₇₀ and distributed to the multiple channels The respective clock input terminals C _IN of the sampling circuits RX[0]-RX[5]. For example, multiplexer 722.0 may select channel LA[0] as the clock channel. Each of the plurality of sampling circuits RX[1]-RX[5] can perform data sampling according to the same clock signal (ie, the signal on the channel LA[0]). The deserializer DS[0] can output a clock signal (ie, a parallel clock signal) according to the sampling result SR. Note that in this mode, multiple multiplexers 722.0 and 724.0 may be used as an embodiment of the clock tree group G1 shown in FIG. 5A.

In the mode in which the integrated circuit 710 is used to support the " _2D1C " bifurcated channel configuration, the multiplexer 724.0 is used to couple the output terminal T71 to the output terminal _T72 . When the multiplexer 722.0 selects one of the multiple channels LA[0]-LA[5] as a clock channel, the multiplexer 722.1 may select the other one of the multiple channels LA[0]-LA[5] One channel is selected as a clock channel. Therefore, the signals on the remaining channels can be sampled according to the signals on the selected clock channel. Two of the multiple deserializers DS[0]-DS[5] can output two clock signals according to the sampling result SR. For example, the multiplexer 722.0 can select channel LA[0] as the clock channel, and each sampling circuit in the plurality of sampling circuits RX[1] and RX[2] can be performed according to the signal on the channel LA[0] Data sampling. The multiplexer 722.1 can select the channel LA[3] as the clock channel, and each sampling circuit in the multiple sampling circuits RX[4] and RX[5] can perform data sampling according to the signal on the channel LA[3]. The deserializer DS[0] can output a parallel clock signal related to the signal on the channel LA[0], and a plurality of deserializers DS[1] and DS[2] can respectively output a plurality of channels LA Multiple parallel data signals associated with respective signals on [1] and LA[2]. In addition, the deserializer DS[3] can output a parallel clock signal related to the signal on the channel LA[3], and the multiple deserializers DS[4] and DS[5] can respectively output multiple A plurality of parallel data signals associated with respective signals on channels LA[4] and LA[5]. In this mode, multiple multiplexers 722.0, 722.1 and 724.0 may serve as an embodiment of the clock tree group G2 shown in Figure 5B.

The circuit structure and operation described above with reference to FIG. 7 are not intended to limit the scope of the present application. For example, the channel selection circuit 720 may be implemented by the channel selection circuit 320 shown in FIG. 3 or the channel selection circuit 620 shown in FIG. 6 without departing from the scope of this application. For another example, the multiplexers 722.0, 722.1 and 724.0 in the channel selection circuit 720 can be arranged in the arrangement shown in FIG. 8 . Referring to FIG. 8 , except for the channel selection circuit 820 , the structure of the integrated circuit 810 is similar/same as the structure of the integrated circuit 710 shown in FIG. 7 . In this embodiment, the multiplexer 724.0 can couple one of the plurality of clock selection signals SEL ₇₀ and SEL ₇₁ to the output terminal T ₇₁ according to the clock selection signal SEL ₇₂ . The multiplexer 722.1 can couple the multiple channels LA[0]-LA[5] to the output terminal T71 according to the signal output by the multiplexer _724.0 . Since those skilled in the art should be able to understand the details of the operation of the channel selection circuit 820 after reading the relevant paragraphs in FIG. 1 to FIG. 7 , further descriptions about the channel selection will not be repeated here.

Please note that for the convenience of channel selection, a clock selection signal used in the clock forwarding scheme disclosed in this application may have a signal value/signal mode ( signal pattern). The channel selection circuit can select the clock channel according to the clock selection signal. In some embodiments, the lane identifier may be the lane name of the selected clock lane, the pin name of the signal pin located in the selected clock lane , or the pin number of a signal pin. For example, the channel identifier may be marked on a circuit board on which an integrated circuit with the selected clock channel is located, or on a package that encapsulates the integrated circuit. As another example, the channel identifier may be marked or described in a datasheet, data book, or device specification of the integrated circuit. In some embodiments, the channel identifier may be identification information carried by the selected clock channel. The integrated circuit can determine which channel should be selected as the clock channel by detecting the identification information.

See Figure 7 again. The integrated circuit 710 also includes a control circuit 750 that can be used to generate a plurality of clock select signals SEL ₇₀ -SEL ₇₂ to control the channel select circuit 720 . When the clock select signal SEL ₇₀ /SEL ₇₁ has a signal value mapped to the channel identifier of one of the plurality of channels LA[0]-LA[5], the channel select circuit 720 may select the channel according to the clock select signal SEL ₇₀ /SEL ₇₁ The channel of the plurality of channels LA[0]-LA[5] is selected. In this embodiment, the respective channel identifiers of the multiple channels LA[0]-LA[5] may include a numerical symbol, and the respective channels of the multiple channels LA[0]-LA[5] The number symbols included in the identifier indicate a group of consecutive numbers. For example (but the present application is not limited to this), a pin name corresponding to a channel can be used as a channel identifier of the channel. A pair of signal pins for channel LA[0] can be named "dp0" and "dn0", a pair of signal pins for channel LA[1] can be named "dp1" and "dn1", and so on. The respective numerical symbols (ie, "0"-"5") of the plurality of pin names dp0-dp5 may indicate a group of consecutive numbers (0-5).

In this embodiment, the control circuit 750 may generate a plurality of clock select signals SEL ₇₀ -SEL ₇₂ in response to a control input IN _CT7 , wherein the control input IN _CT7 may indicate information of a channel identifier of the selected clock channel. The control input IN _CT7 may include (but is not limited to) a mode select signal mss, a channel select signal cks0 and a channel select signal cks1. The mode selection signal mss may indicate the mode of the integrated circuit 710 . For example, the mode selection signal mss may include a bit to indicate whether the integrated circuit 710 operates in the "1C" mode or the "2C" mode. Integrated circuit 710 operates in “1C” mode to receive a single clock signal through multi-channel interface 314 . Integrated circuit 710 operates in “2C” mode to receive two clock signals through multi-channel interface 314 .

The channel selection signal cks0 may include (but is not limited to) three bits, and may indicate a channel identifier of a selected clock channel (ie, one of the plurality of channels LA[0]-LA[5]). The channel select signal cks0 may have a bit pattern or signal value that maps to the channel identifier of the clock channel selected. For example, a channel select signal cks0 having a bit pattern of "000" (corresponding to a signal value of "0") may indicate that channel LA[0] is selected as the clock channel. As another example, a channel select signal cks0 having a bit pattern of "011" (corresponding to a signal value of "3") may indicate that channel LA[3] is selected as the clock channel.

The channel selection signal cks1 may include (but is not limited to) three bits, and may indicate a channel identifier of a selected clock channel (ie, one of the plurality of channels LA[0]-LA[5]). The channel select signal cks1 may have a bit pattern or signal value that maps to the channel identifier of the selected clock channel. When the integrated circuit 710 operates in the "2C" mode to receive two clock signals through the selected two clock channels, the channel select signal cks0 may indicate a channel identifier of one of the selected two clock channels, The channel selection signal cks1 may indicate a channel identifier of the other one of the selected clock channels. For example, when multiple channel select signals cks0 and cks1 have bit patterns "000" and "011", respectively, in "2C" mode, control input IN _CT7 may indicate that both channel LA[0] and channel LA[3] are Select as the clock channel to receive the corresponding clock signal respectively.

In operation, when integrated circuit 710 operates in a mode (such as "1C" mode) to receive a single clock signal CKA through multi-channel interface 314, control circuit 750 may generate clock select signal _SEL72 in response to control input IN _CT7 . The clock select signal SEL ₇₂ may have a first signal value such that the signal on the output terminal T ₇₀ may be distributed to each sampling circuit. For example, the control circuit 750 may generate the clock selection signal SEL ₇₂ according to the mode selection signal mss. For another example, the control circuit 750 may use the mode selection signal mss as the clock selection signal SEL ₇₂ . Notably, in some embodiments, the mode select signal mss in the control input IN _CT7 may be directly input to the multiplexer 724.0 as the clock select signal SEL ₇₂ .

In addition, the control circuit 750 may generate the clock selection signal SEL ₇₀ according to the channel identifier of the channel input by the clock signal CKA. In this embodiment, the control circuit 750 may generate the clock selection signal SEL ₇₀ according to the channel selection signal cks0 , wherein the channel selection signal cks0 may indicate the channel identifier of the channel to which the clock signal CKA is input. For example, when the channel selection signal cks0 indicates that the channel LA[0] is set as a clock channel to receive the clock signal CKA, the control circuit 750 can generate a clock selection with a signal value of "0" according to the channel selection signal cks0 Signal _SEL70 , which maps to the digital symbol "0" of the pin name dp0/dn0 (ie, the channel identifier of channel LA[0]). For another example, when the channel selection signal cks0 indicates that the channel LA[3] is set as a clock channel to receive the clock signal CKA, the control circuit 750 can generate a clock selection signal with a signal value of "3" according to the channel selection signal cks0 SEL ₇₀ , which maps to the digital symbol "3" of the pin name dp3/dn3. It should be noted that, in some embodiments, since the channel selection signal cks0 may have a channel identifier mapped to the selected clock channel, the control circuit 750 may use the channel selection signal cks0 as the clock selection signal SEL ₇₀ .

Control circuit 750 may generate clock select signal _SEL72 in response to control input IN _CT7 when integrated circuit 710 operates in another mode, such as a "2C" mode, to receive two clock signals CKB and CKC through multi-channel interface 314. The clock select signal SEL ₇₂ may have a second signal value different from the first signal value. Thus, the signal on output T ₇₀ can be distributed to a plurality of sampling circuits RX[0]-RX[2], and the signal on output T ₇₁ can be distributed to a plurality of sampling circuits RX[3]-RX[5] . For example, the control circuit 750 may generate the clock selection signal SEL ₇₂ according to the mode selection signal mss, or use the mode selection signal mss as the clock selection signal SEL ₇₂ . It should be noted that, in some embodiments, the mode select signal mss in the control input IN _CT7 can be directly input to the multiplexer 724.0 as the clock select signal SEL ₇₂ .

In addition, the control circuit 750 may generate the clock selection signal _SEL70 according to the channel identifier of the channel input by the clock signal CKB, and generate the clock selection signal _SEL71 according to the channel identifier of the channel input by the clock signal CKC. In this embodiment, the control circuit 750 may generate a plurality of clock selection signals SEL ₇₀ and SEL ₇₁ according to the plurality of channel selection signals cks0 and cks1 in the above-mentioned another mode (such as the "2C" mode), respectively. For example, when the plurality of channel selection signals cks0 and cks1 may indicate that the plurality of channels LA[0] and LA[3] are set as clock channels to receive the plurality of clock signals CKA and CKC, respectively, the control circuit 750 may according to the channel The select signal cks0 generates a clock select signal SEL ₇₀ having a signal value of "0", and a clock select signal SEL ₇₁ having a signal value of "3" is generated according to the channel select signal cks1. It should be noted that, in some embodiments, since the plurality of channel selection signals cks0 and cks1 may have channel identifiers mapped to the selected clock channel, the control circuit 750 may separate the plurality of channel selection signals cks0 and cks1 The signals SEL ₇₀ and SEL ₇₁ are selected as a plurality of clocks.

In some embodiments, the transmitting side may send a preamble signal to a channel on the receiving side before sending a clock signal to the channel. By detecting whether the preamble signal exists, the receiving side can determine whether the clock signal will reach the channel. When a preamble signal present on a predetermined channel on the receiving side is detected, the receiving side can operate in a forked mode to support multi-clock transmission. For example, in the embodiment shown in FIG. 7 , the control circuit 750 may include a state machine 755 to automatically select the mode of the integrated circuit 710 .

FIG. 9 is a schematic diagram of the operation of the state machine 755 shown in FIG. 7 in accordance with certain embodiments of the present application. Please refer to Figure 9 together with Figure 7 . When the physical layer of integrated circuit 710 is enabled, state machine 755 may stay in state ST0 (eg, initial state). In state ST0, the clock selection signal SEL ₇₂ can have the first signal value, so that the signal on a selected clock channel can be distributed to each sampling circuit through the output terminal T ₇₀ . After a period of time T_wait, the state machine 755 can enter the state ST1, so that the control circuit 750 can be used to detect whether the multi-channel interface 314 receives a preamble signal. When the preamble signal is detected on a predetermined channel (ie, another clock channel selected) of the multi-channel interface 314, the state machine 755 may enter state ST2, and the clock select signal SEL ₇₂ may have the The second signal value enables the integrated circuit 710 to operate in the bifurcated mode. After the predetermined channel is deactivated, state machine 755 may return to state ST0. The signal value of the clock select signal SEL ₇₂ may be set to the first signal value.

In some embodiments, the predetermined channel may be a channel indicated by the clock selection signal cks1. By detecting whether a preamble signal is input to the channel indicated by the channel selection signal cks1, the control circuit 750 can determine the signal value of the clock selection signal SEL ₇₂ . In some embodiments, in addition to the channel indicated by the channel selection signal cks1, the control circuit 750 can also be used to detect whether any channel receives a preamble signal. Each channel detected by the control circuit 750 may correspond to the predetermined channel detected in the state ST1.

The above-mentioned automatic channel detection operation is for illustrative purposes only, and is not intended to limit the scope of the present application. Referring again to FIG. 7 , in some embodiments, the control circuit 750 shown in FIG. 7 may be used to detect whether more than one preamble signal arrives at the multi-channel interface 314 . When more than one preamble signal is detected to arrive at the multi-channel interface 314, the control circuit 750 can operate in the fork mode to support multi-clock transmission. For example, the control circuit 750 can be coupled to the multi-channel interface 314 and can generate the clock select signal SEL ₇₂ having the first signal value when a single preamble signal on a channel is detected. When multiple preamble signals on the two channels are detected, the control circuit 750 can generate the clock select signal SEL ₇₂ with the second signal value, so that the integrated circuit 710 operates in the branch mode.

In addition, the above-mentioned implementation manner in which the mapping relationship between the channel identifier and the control input is used to realize the channel selection is only for the purpose of illustration, and is not intended to limit the scope of the present application. In some embodiments, the control circuit 750 may include a decoder (not shown in FIG. 7 ). The decoder can decode a channel select signal to generate a clock select signal for a clock channel to be selected, wherein the channel select signal has a signal value mapped to a channel identifier of the clock channel /signal mode. Therefore, the control circuit 750 can correctly select the clock channel according to the mapping relationship between the channel identifier of the clock channel and the channel selection signal of the control input IN _CT7 .

Please note that the signal value of a channel select signal (or the signal value of a clock select signal) may directly or indirectly correspond/map to the channel identifier of a clock channel to be selected. For example, when the clock signal CKA/CKB is input to the channel LA[0], the channel select signal cks0 may have a bit pattern "000001", which corresponds to the signal mapped to the digital symbol "0" of the pin name dp0/dn0 The value "2 ⁰ ". Additionally, or alternatively, the control circuit 750 may generate the clock select signal SEL ₇₀ having a bit pattern "000001", where the bit pattern "000001" corresponds to the signal value "0" mapped to the digital symbol "0" of the pin name dp0/dn0 ²⁰ ". For another example, when the clock signal CKC is input to the channel LA[3], the channel selection signal cks1 may have a bit pattern "001000", which corresponds to the signal value "2" mapped to the digital symbol "3" of the pin name dp3/dn3 ³ ". Additionally, or alternatively, the control circuit 750 may generate the clock select signal _SEL71 having a bit pattern "001000", where the bit pattern "001000" corresponds to the signal value 2 mapped to the digital symbol "3" of the pin name dp3/dn3 ³ ".

In some embodiments, other types of channel identifiers (such as channel names, pin numbers, or identifying information carried by the channel) may be mapped to the signal value of the channel select signal. In some embodiments, the control circuit 750 may determine the signal value of the clock select signal based on other types of channel identifiers, such as channel names, pin numbers, or identification information carried by the channels. In some embodiments, the numerical symbols of the channel identifiers may be in the form of Arabic numerals, Roman numerals, letters, or other types of numerical symbols. In some embodiments, the set of consecutive numbers indicated by the respective numerical symbols of the plurality of channel identifiers may be a plurality of consecutive odd numbers, a plurality of consecutive even numbers, or a plurality of numbers having a predetermined consecutive order. For example, some embodiments of channel identifiers for the plurality of channels LA[0]-LA[5] shown in FIG. 7 are shown in FIG. 10 according to some embodiments of the present application. These design modifications and changes all follow the spirit of the present application and fall into the protection scope of the present application.

The channel selection operation described above can be applied to the integrated circuit 110 shown in FIG. 1 , the integrated circuit 310 shown in FIG. 3 , the multiple integrated circuits 510A- 510C shown in FIGS. Circuit 610 and integrated circuit 810 shown in FIG. 8 . See again Figure 3 for an example. The integrated circuit 310 further includes a control circuit 350 , which can generate a plurality of clock select signals SEL ₀₀ , SEL ₀₁ and SEL ₁₀ -SEL ₁₅ in response to a control input IN _CT3 to control the channel select circuit 320 .

The control input IN _CT3 may indicate information of the channel identifier of the selected clock channel. for example. The control input IN _CT3 may include a plurality of channel selection signals, wherein each channel selection signal may indicate information of a channel identifier of a selected clock channel. The control circuit 350 can generate a clock selection signal SEL ₀₀ according to a channel selection signal, and generate a clock selection signal SEL ₀₁ according to another channel selection signal. For another example, the control input IN _CT3 may also include a mode selection signal, which may indicate the mode of the integrated circuit 310 . The control circuit 350 can generate a plurality of clock selection signals SEL ₁₀ -SEL ₁₅ according to the mode selection signal.

In the "5D1C" channel configuration, the multiple clock selection signals SEL ₁₀ -SEL ₁₅ may have the same signal value, so that one of the multiple output sides S02 and S12 may be coupled to each sampling circuit. When the clock signal 5D_CLK is input to one of the plurality of channels LA[0]-LA[2], the plurality of clock select signals _SEL10 - _SEL15 can have a first signal value, so that the output side S02 can be coupled to each sampling circuit. The control circuit 350 may generate the clock select signal SEL ₀₀ from a channel select signal in the control input IN _CT3 , wherein the channel select signal has a signal value mapped to the channel identifier of the channel. Additionally, or alternatively, clock select signal SEL ₀₀ may have a signal value that maps to the channel identifier of the channel. When the clock signal 5D_CLK is input to one of the plurality of channels LA[3]-LA[5], the plurality of clock selection signals _SEL10 - _SEL15 can have a second signal value, so that the output side S12 can be coupled to each sampling circuit. The control circuit 350 may generate the clock select signal SEL ₀₁ according to another channel select signal in the control input IN _CT3 , wherein the other channel select signal has a signal value mapped to the channel identifier of the channel. Additionally, or alternatively, the clock select signal SEL ₀₁ may have a signal value that maps to the channel identifier of the channel.

In the "2D1C" bifurcated channel configuration, each of the plurality of clock select signals _SEL10 - _SEL12 may have a signal value, wherein the signal value is different from the plurality of clock select signals _SEL13 - _SEL15 The signal value of the selected signal for each clock in . Therefore, the output side S02 can be coupled to a plurality of sampling circuits RX[0]-RX[2], and the output side S12 can be coupled to a plurality of sampling circuits RX[3]-RX[5]. Since the clock signal 2D_CLK0 is input to one of the plurality of channels LA[0]-LA[2], the control circuit 350 can generate the clock selection signal SEL ₀₀ according to a channel selection signal in the control input IN _CT3 , wherein the channel The pick signal has a signal value that maps to the channel identifier of the channel. Additionally, or alternatively, clock select signal SEL ₀₀ may have a signal value that maps to the channel identifier of the channel. Similarly, since the clock signal 2D_CLK0 is input to one of the plurality of channels LA[3]-LA[5], the control circuit 350 can generate the clock selection signal SEL ₀₁ according to another channel selection signal in the control input IN _CT3 , wherein the other channel select signal has a signal value mapped to a channel identifier of the channel. Additionally, or alternatively, the clock select signal SEL ₀₁ may have a signal value that maps to the channel identifier of the channel.

In some embodiments, clock select signal SEL ₀₀ and clock select signal SEL ₀₁ may be implemented as a single clock select signal. Each of the multiple channel selection units 322.0 and 322.1 can perform a channel selection operation according to the single clock selection signal. The control circuit 350 can determine the signal value/signal mode of the single clock selection signal according to one or more channel identifiers of the one or more channels to be selected. For example, in a "5D1C" channel configuration, the single clock signal has a signal value that maps to the channel identifier of the channel to which the clock signal 5D_CLK is input. For another example, in a "2D1C" bifurcated channel configuration, the first three least significant bits (LSBs) of the single clock signal have a signal value that maps to multiple channels LA[0]-LA[ 2] The channel identifier of one of the channels. The first three most significant bits (MSBs) of the single clock signal have a signal value that maps to a channel identifier of one of the plurality of channels LA[3]-LA[5].

Similarly, referring to FIG. 1 again, the integrated circuit 110 further includes a control circuit 150, which can generate a clock selection signal according to a control input IN _CT1 , or according to a channel identifier of a channel among the selected clock channels symbol to generate the clock select signal. Control input IN _CT1 may indicate the channel identifier. Additionally, or alternatively, the clock select signal may have a signal value mapped to the channel identifier. Therefore, the channel selection circuit 120 can select the channel according to the clock selection signal. Additionally, or alternatively, in the embodiments shown in FIGS. 5A , 5B, 5C and 6 , the signal values of the clock select signals SEL _A /SEL _B1 /SEL _B2 /SEL _C1 /SEL _C2 /SEL _C3 may be based on The channel identifier of the channel to which the clock signal is input is determined. Since those skilled in the art should understand the generation of the clock selection signals SEL _A /SEL _B1 / shown in FIGS. 5A , 5B, 5C and 6 after reading the above paragraphs about FIGS. 7 , 8 and 3 , The details of SEL _B2 /SEL _C1 /SEL _C2 /SEL _C3 , therefore, further description will not be repeated here.

At least one of the channel swapping scheme and the channel selection operation described above can be applied to other sublayers of the physical layer, such as the physical coding sublayer. 11 is a functional block diagram of an exemplary receiver according to some embodiments of the present application. The receiver 1104 may be an embodiment of the receiver 104 shown in FIG. 1 . The physical layer 1108 of the receiver 1104 includes a physical medium attachment layer (PMA) 1105 and a physical coding sublayer (PCS) 1107 . The physical medium connection layer 1105 may employ the circuit structures and operations described with reference to FIGS. 1 to 10 .

The physical medium connection layer 1105 includes (but is not limited to) a multi-channel interface 1114, a channel selection circuit 1120, and a plurality of S2P converters 1130 ₀ -1130 _N-1 , where N is an integer greater than 1. The multi-channel interface 1114 and the channel selection circuit 1120 can be used as embodiments of the multi-channel interface 114 and the channel selection circuit 120 shown in FIG. 1 , respectively. The multi-lane interface 114 may include N lanes LA[0]-LA[N-1] shown in FIG. 1 . The channel selection circuit 1120 is used to select one or more channels in the multi-channel interface 1114 as one or more clock channels according to a set of clock selection signals {SEL _PMA }. Furthermore, multiple S2P converters 1130 ₀ - 1130 _N-1 may be implemented using the N sampling circuits RX[0]-RX[N-1] and the output circuit 140 shown in FIG. 1 .

The physical coding sublayer 1107 includes (but is not limited to) a multi-channel interface 1116, a channel selection circuit 1122, and a plurality of processing circuits 1132 ₀ - 1132 _N-1 . The multi-channel interface 1116 may be an embodiment of the multi-channel interface 114 shown in FIG. 1 . The multi-lane interface 1116 includes N lanes LS[0]-LS[N-1] coupled to the physical medium connection layer 1105 . The channel selection circuit 1122 can be used as an embodiment of the channel selection circuit 120 shown in FIG. 1 . The channel selection circuit 1122 is used for selecting one or more channels among the N channels LS[0]-LS[N-1] as one or more clock channels according to a set of clock selection signals {SEL _PCS }. Each of the N channels LS[0]-LS[N-1] can be commonly used for the clock channel and the data channel. In addition, the plurality of processing circuits 1132 ₀ - 1132 _N-1 may be implemented to include the N sampling circuits RX[0]-RX[N-1] shown in FIG. Multiple clock signals for data sampling.

In operation, the physical medium connection layer 1105 may be configured to output M clock signals CKD ₁ -CKD _M respectively associated with M different clock domains, where M is a positive integer less than N. The physical coding sublayer 1107 may select M channels among the N channels LS[0]-LS[N-1] as M clock channels to receive M clock signals CKD ₁ -CKD _M . That is to say, in response to the channel selection operation of the physical medium connection layer 1105, the physical coding sublayer 1107 can perform the corresponding channel selection operation. For example, the multi-channel interface 1114 of the physical medium attachment layer 1105 may receive M clock signals transmitted by M transmitters (not shown in FIG. 11 ) to generate M clock signals CKD ₁ -CKD _M , where the M The transmitters operate in the M different clock domains respectively. The channel selection circuit 1120 may select the M channels in the multi-channel interface 1114 as the M clock channels according to a set of clock selection signals {SEL _PMA }. M S2P converters (coupled to the selected M channels) among the plurality of S2P converters 1130 ₀ - 1130 _N-1 can respectively generate M clock signals CKD ₁ -CKD _M . In response to the channel selection operation of the physical medium connection layer 1105, the channel selection circuit 1122 in the physical coding sublayer 1107 can select the N channels LS[0]-LS[N-1] according to a set of clock selection signals {SEL _PCS } The M channels are selected as M clock channels. One or more channels included in the remaining (NM) channels in the N channels LS[0]-LS[N-1] can be used as one or more data channels. The plurality of processing circuits 1132 ₀ - 1132 _N-1 may process data on the one or more data lanes according to the M clock signals CKD ₁ -CKD _M.

A set of clock select signals {SEL _PMA } and a set of clock select signals {SEL _PCS } may be generated by a control input shared by the physical medium connection layer 1105 and the physical coding sublayer 1107 . In this embodiment, the physical coding sublayer 1107 may further include a control circuit 1150, which may be used as an embodiment of the control circuit 150 shown in FIG. 1 . The control circuit 1150 can generate a set of clock select signals {SEL _PMA } and a set of clock select signals {SEL _PCS } according to a control input IN _CTRL . The control input IN _CTRL may indicate the channel identifier of the clock channel selected in the physical medium connection layer 1105 and the channel identifier of the clock channel selected in the physical coding sublayer 1107 . For example, when the control input IN _CTRL has a signal mode/signal value that maps to the channel identifier of channel LA[0] of the physical medium attach layer 1105, the control circuit 1150 may generate a set of clock select signals according to the control input IN _CTRL {SEL _PMA }, so that channel LA[0] can be set as a clock channel to receive the clock signal transmitted by the transmitter (not shown in Figure 11). In addition, the control circuit 1150 can generate a set of clock select signals {SEL _PCS } according to the control input IN _CTRL , so that the channel LS[0] (the channel identifier with the signal mode/signal value mapped to the control input IN _CTRL ) can be set The clock channel is designated to receive the clock signal output by the physical medium connection layer 1105, wherein the clock signal output by the physical medium connection layer 1105 is generated in response to the clock signal transmitted by the transmitter.

For example (but the present application is not limited thereto), the control input IN _CTRL may include a plurality of channel selection signals, wherein each channel selection signal may indicate a channel identifier of a selected clock channel. As another example, the control input IN _CTRL may be a mode select signal and multiple channel select signals, wherein the mode select signal may indicate the mode of the receiver 1104, such as "1C" mode or bifurcated mode. As those skilled in the art should understand after reading the relevant paragraphs in FIGS. 1 to 10 , the control circuit 1150 can use the mapping relationship between the channel identifier and the control input to control the channel selection circuit 1120 and the channel selection circuit 1122, Therefore, the repeated description about channel selection will not be repeated here.

In some embodiments, the shared control circuit 1150 may be located in the physical medium connection layer 1105 instead of the physical coding sublayer 1107 . In some embodiments, the physical medium connection layer 1105 may have a first control circuit disposed therein, and the physical coding sublayer 1107 may have a second control circuit disposed therein. The first control circuit and the second control circuit may control the channel selection operation according to the same control input, such as the control input _INCTRL . These design modifications and changes all follow the spirit of the present application and fall into the protection scope of the present application.

Some embodiments are provided below to further illustrate the physical coding sublayer 1107 using the channel swap scheme. Those skilled in the art should understand that other physical coding sublayers adopting the channel interchange scheme described with reference to FIG. 1 to FIG. 10 all follow the spirit of the present application and fall within the protection scope of the present application.

FIG. 12 is a schematic diagram of an embodiment of an integrated circuit in the physical coding sublayer 1107 shown in FIG. 11 according to some embodiments of the present application. The integrated circuit 1210 in the physical coding sublayer 1207 can be used as an embodiment of the integrated circuit 110 shown in FIG. 1 (which includes six channels that can be commonly used for clock channels and data channels, N=6). In this embodiment, the physical coding sublayer 1207 is used to receive the clock and data information transmitted by the physical medium connection layer (PMA) 1205, wherein the physical medium connection layer 1205 can be used as the implementation of the physical medium connection layer 1105 shown in FIG. 11 . example. The integrated circuit 1210 may include a multi-channel interface 1214, a channel selection circuit 1220, and a plurality of sampling circuits RM[0]-RM[5]. The multi-channel interface 1214 and the channel selection circuit 1220 can be used as embodiments of the multi-channel interface 114 and the channel selection circuit 120 shown in FIG. 1 , respectively. The multiple sampling circuits RM[0]-RM[5] can be used as an embodiment of the multiple sampling circuits RX[0]-RX[5] shown in FIG. 1 .

The multi-channel interface 1214 is coupled to the physical medium connection layer 1205 and includes a plurality of channels LS[0]-LS[5] shown in FIG. 11 . Multiple lanes LS[0]-LS[5] can be used as an embodiment of the N lanes LA[0]-LA[N-1] shown in FIG. 1 (ie, N=6). In this embodiment, each of the plurality of channels LS[0]-LS[5] can carry a multi-bit output signal, such as a one-byte data signal or a one-byte clock signal.

The channel selection circuit 1220 is used for selecting one or more channels among the plurality of channels LS[0]-LS[5] as one or more clock channels. One or more of the remaining channels can be used as one or more data channels. The channel selection circuit 1220 includes, but is not limited to, a plurality of selection stages 1222 and 1224, which may be embodiments of the plurality of selection stages 122 and 124 shown in FIG. 1, respectively. In this embodiment, selection stage 1222 may couple one or two channels to selection stage 1224 in response to the mode of integrated circuit 1210 . The selection stage 1222 includes a plurality of channel selection units 1222.0 and 1222.1. The channel selection unit 1222.0 is used for coupling a plurality of channels LS[0] _-LS [5] to an output terminal T100 according to a clock selection signal _SEL100 . The channel selection unit 1222.1 is used for coupling a plurality of channels LS[0] _-LS [5] to an output terminal T101 according to a clock selection signal _SEL101 . The selection stage 1224 may be implemented to include a channel selection unit _1224.0 , which may couple _one of the output terminal T100 and the output terminal T101 to an output terminal _T102 according to a clock selection signal _SEL102 .

A plurality of sampling circuits RM[0]-RM[5] are coupled to the multi-channel interface 1214 and the channel selection circuit 1220 for sampling data according to the clock information and data information transmitted by the physical medium connection layer 1205 . In this embodiment, each of the plurality of sampling circuits RM[0]-RM[5] may include a clock input terminal PC _IN and a data input terminal PD _IN . Each sampling circuit can use the signal input to the corresponding clock input terminal PC _IN to sample the signal input to the corresponding data input terminal PD _IN .

In the mode in which the integrated circuit 1210 is used to support the "4D1C" channel configuration, the channel selection unit 1224.0 is used to couple the output terminal T ₁₀₀ to the output terminal T ₁₀₂ . When the channel selection unit 1222.0 selects one of the multiple channels LS[0]-LS[5] as a clock channel, the signal on the clock channel can be coupled to the output terminal T ₁₀₀ and distributed to multiple channels The respective clock input terminals PC _IN of the sampling circuits RM[0]-RM[5]. For example, when a clock signal is input to channel LS[0], the channel selection unit 1222.0 can select channel LS[0] as the clock channel, and four of the sampling circuits RM[0]-RM[5] The two sampling circuits may sample data according to the same clock signal (ie, the signal on channel LS[0]).

In the mode in which the integrated circuit 1210 is used to support the "2D1C" bifurcated channel configuration, the channel selection unit 1224.0 is used to couple the output terminal T ₁₀₁ to the output terminal T ₁₀₂ . When the channel selection unit 1222.0 selects one of the multiple channels LS[0]-LS[5] as a clock channel, the channel selection unit 1222.1 can select another one of the multiple channels LS[0]-LS[5] The channel is selected as a clock channel. Therefore, the signals on the remaining plurality of channels may be sampled according to the signals on the selected plurality of clock channels. For example, when two clock signals are input to channel LS[1] and channel LS[4] respectively, the channel selection unit 1222.0 may select channel LS[1] as a clock channel, and the channel selection unit 1222.1 may select channel LS[1] 4] Select another clock channel. Four sampling circuits in the plurality of sampling circuits RM[0]-RM[5] may perform data sampling according to the two clock signals involving different clock domains.

It should be noted that the physical coding sublayer 1207 can adopt the channel selection operation described above. In this embodiment, the integrated circuit 1210 further includes a control circuit 1250 , which can generate a plurality of clock selection signals SEL ₁₀₀ -SEL ₁₀₂ according to a control input IN _CT12 to control the channel selection circuit 1220 . For example, when a clock signal transmitted by the physical medium connection layer 1205 is input to one of the multiple channels LS[0]-LS[5] in the "4D1C" channel configuration, the control circuit 1250 can input IN according to the control _CT12 generates clock select signal _SEL100 , which may indicate the channel identifier of the channel. For another example, when two clock signals are input to two of the multiple channels LS[0]-LS[5] in the "2D1C" bifurcated channel configuration, the control circuit 1250 can generate the clock selection signal according to the control input IN _CT12 SEL ₁₀₀ , which may indicate the channel identifier of one of the two channels. In addition, the control circuit 1250 can generate the clock select signal SEL ₁₀₁ according to the control input IN _CT12 , which can indicate the channel identifier of the other channel among the two channels.

The channel selection operation described above can be applied to the data channel selection operation. For example, the channel selection circuit 1220 further includes a plurality of channel selection units 1232.0-1232.3, which can be controlled by a plurality of data selection signals SEL ₁₁₀ -SEL ₁₁₃ generated by the control circuit 1250. In this embodiment, the plurality of channel selection units 1232.0-1232.3 can respectively provide the data transmitted by the physical medium connection layer 1205 to the plurality of sampling circuits RM[0], RM[2], RM[3] and RM[5] ].

In the "4D1C" channel configuration mode (one of the multiple channels LS[0] _-LS [5] is selected as the clock channel), the control circuit 1250 can generate a plurality of data select signals SEL ₁₁₀ − SEL ₁₁₃ , where control input IN _CT12 may indicate the respective channel identifiers of the four channels that carry the data signals carried by the physical medium connection layer 1205 . For example, respective signal values of the plurality of data select signals SEL ₁₁₀ -SEL ₁₁₃ may be mapped to respective channel identifiers of the four channels, respectively.

In the "2D1C" channel configuration mode (two of the multiple channels LS[0]-LS[5] are selected as clock channels), the control circuit 1250 can generate a plurality of data selection signals SEL ₁₁₀ according to the control input IN _CT12 and SEL ₁₁₁ , where the control input IN _CT12 may indicate the respective channel identifiers of the two channels. The two channels may carry data signals related to the clock signal output by the channel selection unit 1222.0. For example, respective signal values of the plurality of data select signals SEL ₁₁₀ and SEL ₁₁₁ may be mapped to respective channel identifiers of the two channels, respectively. In addition, the control circuit 1250 can generate a plurality of data selection signals SEL ₁₁₂ and SEL ₁₁₃ according to the respective channel identifiers of the other two channels, wherein the other two channels can carry data related to the clock signal output by the channel selection unit 1222.1 Signal. For example, respective signal values of the plurality of data select signals SEL ₁₁₂ and SEL ₁₁₃ may be mapped to respective channel identifiers of the other two channels, respectively.

As those skilled in the art should understand that the data channel selection operation used in the clock forwarding scheme may be similar/same as the clock channel selection operation described with reference to FIGS. No longer.

In some embodiments, the control circuit 1250 may be shared by the physical medium connection layer 1205 and the physical coding sublayer 1207 . For example, the control circuit 1250 may generate one or more clock selection signals to control the clock selection operation of the physical medium attachment layer 1205 . For another example, the control circuit 1250 can use one or more clock selection signals of the channel selection circuit 1220 to control the channel selection circuit of the physical medium connection layer 1205 (not shown in FIG. 12 ), so that the physical medium connection layer 1205 and the physical encoder The respective channel selection operations of the layers 1207 are consistent with each other.

It should be noted that the circuit structure and operation of the channel selection circuit 1220 shown in FIG. 12 are only for illustrative purposes. In some embodiments, the channel selection circuit 1220 may utilize the channel selection circuit 120 shown in FIG. 1 , the channel selection circuit 320 shown in FIG. 3 , the plurality of channel selection circuits 520A-520C shown in FIGS. 5A to 5C , The channel selection circuit 620 shown in FIG. 6 , the channel selection circuit 720 shown in FIG. 7 , the channel selection circuit 820 shown in FIG. 8 , and the related design changes described above are implemented without departing from the scope of this application.

For example, please refer to FIG. 13, which is a schematic diagram of another embodiment of an integrated circuit in the physical coding sublayer 1107 shown in FIG. 11 according to some embodiments of the present application. Except for the channel selection circuit 1320, the structure of the integrated circuit 1310 of the physical coding sublayer 1307 may be similar/same as the structure of the integrated circuit 1210 shown in FIG. 12 . In this embodiment, the selection stage 1322 in the channel selection circuit 1320 includes a channel selection unit 1322.a, a channel selection unit 1322.b, and the channel selection unit 1222.1 shown in FIG. 12 . The channel selection unit 1322.a can couple a plurality of channels LS[0]-LS[5] to an output terminal _T13A according to the clock selection signal _SEL100 , wherein the output terminal _T13A is coupled to a plurality of sampling circuits RM[0 ]-RM[2] respective clock inputs PC _IN . The channel selection unit 1322.b can couple the plurality of channels LS[0]-LS[5] to an output terminal _T13B according to the clock selection signal _SEL100 , wherein the output terminal _T13B is coupled to the channel selection unit 1224.0. Since those skilled in the art should be able to understand the details of the operation of the channel selection circuit 1320 after reading the relevant paragraphs in FIG. 1 to FIG. 12 , further descriptions will not be repeated here.

In addition, the channel selection scheme described above can also be applied to the transmission side. 14 is a functional block diagram of an exemplary multi-channel communication system according to some embodiments of the present application. The multi-channel communication system 1400 may include a transmitter 1402 and a receiver 1404 . The transmitter 1402 may be an embodiment of one of the K transmitters TX[0]-TX[K-1] shown in FIG. 1 . The receiver 1404 may employ the circuit structure and operation described with reference to FIGS. 1 to 13 . In this embodiment, the transmitter 1402 can cause the signals transmitted on the clock channel and on the data channel to be interchanged with each other. The transmitter 1402 includes (but is not limited to) a plurality of signal generating circuits 1410.0-1410.2, a channel selection circuit 1420, a plurality of parallel-to-serial converters (hereinafter referred to as "P2S converters") 1430.0 -1430.2, a multi-channel interface 1440, and a control circuit 1450.

Each of the plurality of signal generation circuits 1410.0-1410.2 may generate a multi-bit output signal, such as a parallel clock signal or a parallel data signal, on a data bus. In this embodiment, both the signal generating circuit 1410.0 and the signal generating circuit 1410.1 can be implemented by a data signal generator, and the signal generating circuit 1410.2 can be implemented by a clock signal generator. Therefore, the plurality of signal generating circuits 1410.0 and 1410.1 can respectively generate the plurality of parallel data signals PD0 and PD1 on the plurality of data buses DB0 and DB1. The signal generating circuit 1410.2 can generate a parallel clock signal PC0 on the data bus DB2.

The channel selection circuit 1420 is coupled to the plurality of signal generating circuits 1410.0-1410.2 for distributing the plurality of multi-bit output signals generated by the plurality of signal generating circuits 1410.0-1410.2 to the plurality of P2S converters 1430.0-1430.2. In this embodiment, the channel selection circuit 1420 includes a plurality of channel selection units _{1422.0-1422.2} , wherein each channel selection unit can output a plurality of channels according to a corresponding selection signal (ie, one of the plurality of selection signals SEL _T0 -SEL T2). One of multiple output signals on the data buses DB0-DB2.

Each of the plurality of P2S converters 1430.0-1430.2 can convert a parallel output signal into a serial output signal. The multi-channel interface 1440 may be an embodiment of one of the K multi-channel interfaces TF[0]-TF[K-1] shown in FIG. 1 . The multi-lane interface 1440 may include multiple lanes LT[0]-LT[2]. At least one of the plurality of channels LT[0]-LT[2] can be commonly used for the clock channel and the data channel. In this embodiment, each of the plurality of channels LT[0]-LT[2] may be implemented using a two-wire channel, which is a differential channel including a pair of signal pins. The included pair of signal pins of channel LT[0] may be named "dpt0" and "dnt0", and the included pair of signal pins of channel LT[1] may be named "dpt1" and "dnt1", so that analogy. In certain embodiments, each of the plurality of channels LT[0]-LT[2] may be implemented with other types of channels, such as single-wire channels or channels with more than two wires, without departing from the scope of the present application scope.

The control circuit 1450 is used for generating a plurality of selection signals SEL _T0 -SEL _T2 according to a control input IN _CT14 to control the channel selection circuit 1420 . The signal value of each of the plurality of selection signals SEL _T0 -SEL _T2 can be determined according to the control input IN _CT14 , wherein the control input IN _CT14 can indicate a channel identifier corresponding to a channel. For example, the receiver 1404 can use the channel 1406.0 as a clock channel to receive the clock information transmitted by the transmitter 1402. Both channel 1406.1 and channel 1406.2 can act as data channels for receiver 1404. By coupling the signal generating circuit 1410.2 to the P2S converter 1430.0, the channel selection unit 1422.0 can select the channel LT[0] (which is coupled to the channel 1406.0) as a clock channel according to the selection signal SEL _T0 . The control circuit 1450 may decide the signal value of the select signal SEL _T0 according to the channel identifier of the channel LT[0], such as the pin name "dpt0/dnt0" or the channel name "LT[0]". In addition, the channel selection unit 1422.1 may select the channel LT[1] as a data channel according to the selection signal SEL _T1 , and the channel selection unit 1422.2 may select the channel LT[2] as a data channel according to the selection signal SEL _T2 . Since those skilled in the art should be able to understand the details of the clock/data channel selection operation of the channel selection circuit 1420 after reading the above paragraphs about the clock/data channel selection operation on the receiving side, further descriptions will not be given here. Repeat.

The circuit structures described above are for illustrative purposes only, and are not intended to limit the scope of the present application. In some embodiments, the number of channels of the above-mentioned multi-channel interface can be changed according to different design requirements and applications. For example, a multi-lane interface may include four lanes, eight lanes, or other numbers of lanes according to different embodiments. In some embodiments, the one or more channel selection units described above may be implemented using one or more multiplexers, or may be implemented using other circuits with signal path selection capability. In certain embodiments, one or more of the multiplexers described above may be implemented based on inverters, OR-logic gates, other circuits with signal routing capabilities, or a combination thereof.

The physical layer on the receiving side can support different channel configurations on the transmitting side through at least one channel that can be used interchangeably between the clock channel and the data channel. For example, the physical layer can be divided into multiple physical interfaces to support multiple transmitters. In addition, a clock/data channel can be selected according to the channel identifier of the clock/data channel, so as to facilitate the selection of the clock/data channel.

The foregoing description briefly sets forth the features of certain embodiments of the application, so that those skilled in the art can more fully understand the various aspects of the application. Those skilled in the art will appreciate that they can readily use the content of this application as a basis to design or modify other processes and structures to achieve the same purposes and/or achieve the same advantages as the embodiments described herein . Those skilled in the art should understand that these equivalent embodiments still belong to the spirit and scope of the present application, and various changes, substitutions and alterations can be made without departing from the spirit and scope of the present application.

Claims (20)

1. An integrated circuit in a physical layer of a receiver, comprising: A multi-channel interface with N channels, where N is an integer greater than 1; A channel selection circuit, coupled to the multi-channel interface, is used to select M channels among the N channels as M clock channels, and output M signals respectively on the M clock channels, wherein M is a positive integer less than N, with the remaining (N-M) channels as (N-M) data channels; and N sampling circuits are coupled to the multi-channel interface and the channel selection circuit, wherein (N-M) sampling circuits in the N sampling circuits are respectively coupled to the (N-M) data channels; the Each sampling circuit in the (N-M) sampling circuits is used to sample the signals on the data channels in the (N-M) data channels according to one of the M signals on the M clock channels; Wherein the channel selection circuit includes: a first multiplexer, the input side of the first multiplexer is coupled to each of the N channels; a second multiplexer, the input side of the second multiplexer is coupled to a part of the N channels, but not coupled to another part of the N channels; and N third multiplexers, the respective output sides of the N third multiplexers are respectively coupled to the N sampling circuits, wherein the first multiplexer is configured by coupling one of the N channels On the input side of each third multiplexer in the N third multiplexers, a clock channel is selected; the second multiplexer passes one of the partial channels of the N channels A clock channel is selected by being coupled to the input side of each third multiplexer in a part of the N third multiplexers. 2 . The integrated circuit of claim 1 , wherein when M is equal to 1, the channel selection circuit is configured to couple the signal on the clock channel to the signal in the N sampling circuits. 3 . each sampling circuit; when M is greater than 1, the channel selection circuit is used to couple one of the M signals on the M clock channels to a part of the N sampling circuits, and to Another one of the M signals on the M clock channels is coupled to another part of the N sampling circuits. 3 . The integrated circuit of claim 1 , wherein the channel selection circuit selects one of the N channels by coupling one of the N channels to a clock input of one of the N sampling circuits. 4 . The channel among the N channels is selected as a clock channel. 4 . The integrated circuit of claim 1 , wherein none of the M signals on the M clock channels are coupled to the sampling circuits of the N sampling circuits. 5 . data input. 5. The integrated circuit of claim 1, wherein the first multiplexer and the second multiplexer serve as at least a part of a first selection stage of the channel selection circuit, and the N multiplexers A third multiplexer acts as at least a part of the second selection stage of the channel selection circuit, wherein: The first selection stage has an input side and an output side, the input side of the first selection stage is coupled to the multi-channel interface, and the first selection stage is used to convert the M signals are coupled from the input side of the first selection stage to the output side of the first selection stage; and The second selection stage is arranged between the output side of the first selection stage and the N sampling circuits, and the second selection stage is used to convert the M signals on the M clock channels into the M signals. Each signal of is coupled to one or more sampling circuits in the N sampling circuits. 6. The integrated circuit of claim 1, further comprising: a control circuit, coupled to the channel selection circuit, for detecting whether one of the M channels receives a preamble signal to generate a clock selection signal, wherein when the control circuit detects the M channels When the channel in the M channels receives the preamble signal, the channel selection circuit is configured to select the channel of the M channels according to the clock selection signal. 7. The integrated circuit of claim 1, wherein the integrated circuit is located at the physical medium connection layer of the physical layer, M is greater than 1, and the integrated circuit further comprises: an output circuit, coupled to the N sampling circuits for outputting M clock signals from the physical medium connection layer according to the sampling results of the N sampling circuits, wherein the M clock signals are respectively related to M different clock domains. 8. The integrated circuit of claim 1, wherein the channel selection circuit is used to select a channel among the M channels according to a clock selection signal; the integrated circuit further comprises: a control circuit, coupled to the channel selection circuit, for generating the clock selection signal according to the channel identifier of the channel in the M channels, the clock selection signal having a channel identifier mapped to the channel the signal value. 9 . The integrated circuit according to claim 8 , wherein the respective channel identifiers of the N channels include digital symbols, and the plurality of digital symbols included in the respective channel identifiers of the N channels indicate the Get a set of consecutive numbers. 10 . The integrated circuit of claim 1 , wherein the channel selection circuit is configured to couple one of the (N-M) channels to the N sampling circuits according to a data selection signal. 11 . one; the integrated circuit further includes: A control circuit, coupled to the channel selection circuit, is used for generating the data selection signal according to the channel identifier of the channel in the (N-M) channels, the data selection signal having a mapping to the ( The signal value of the channel identifier of the channel of the N-M) channels. 11. The integrated circuit of claim 10, wherein the respective channel identifiers of the N channels comprise digital symbols, and the plurality of digital symbols included in the respective channel identifiers of the N channels indicate that Get a set of consecutive numbers. 12. An integrated circuit in a physical layer of a receiver, comprising: A multi-channel interface with N channels, where N is an integer greater than 1; N sampling circuits coupled to the multi-channel interface, wherein each sampling circuit in the N sampling circuits has a clock input terminal and a data input terminal; and A channel selection circuit for selecting the M channels as M clock channels by coupling M channels in the N channels to the N clock input terminals of the N sampling circuits, wherein M is a positive integer less than N, and the remaining (N-M) channels are used as (N-M) data channels; in a mode, one of the N channels is selected to be coupled to the N clock inputs In another mode, the selected channel among the N channels is used as one of the N data inputs coupled to the N sampling circuits without a data channel coupled to the N clock input terminals; Wherein the channel selection circuit includes: a first multiplexer, the input side of the first multiplexer is coupled to each of the N channels; a second multiplexer, the input side of the second multiplexer is coupled to a part of the N channels, but not coupled to another part of the N channels; and N third multiplexers, the respective output sides of the N third multiplexers are respectively coupled to the N sampling circuits, wherein the first multiplexer is configured by coupling one of the N channels At the input side of each third multiplexer in the N third multiplexers, a clock channel is selected; the second multiplexer is used to pass One is coupled to the input side of each of the N third multiplexers, and selects one clock channel. 13 . The integrated circuit of claim 12 , wherein the N sampling circuits are divided into M groups of sampling circuits, and the M groups of sampling circuits are used to receive M signals on the M clock channels respectively. 14 . a signal. 14. The integrated circuit according to claim 12, wherein when M is equal to 1, each sampling circuit in the (N-M) sampling circuits respectively coupled to the (N-M) data channels is used according to the The selected signal on the clock channel is sampled on the signal on the corresponding data channel; when M is greater than 1, a sample in the (N-M) sampling circuits respectively coupled to the (N-M) data channels The circuit is used for sampling the signal on the corresponding data channel according to one of the M signals on the M clock channels, and another sampling circuit in the (N-M) sampling circuits is used for sampling according to the The other one of the M signals on the M clock channels samples the signal on the corresponding data channel. 15. The integrated circuit of claim 12, wherein the first multiplexer and the second multiplexer serve as at least a part of a first selection stage of the channel selection circuit, and the N multiplexers A third multiplexer acts as at least a part of the second selection stage of the channel selection circuit, wherein: The first selection stage has an input side and an output side, the input side of the first selection stage is coupled to the multi-channel interface, and the first selection stage is used to convert the M clock channels on the M clock channels. a signal is coupled from the input side of the first selection stage to the output side of the first selection stage; and The second selection stage is arranged between the output side of the first selection stage and the N sampling circuits, and the second selection stage is used to convert the M clock channels on the M clock channels. Signals are distributed to the N clock inputs. 16. The integrated circuit of claim 12, wherein the integrated circuit is located at a physical medium connection layer of the physical layer, M is greater than 1, and the integrated circuit further comprises: an output circuit, coupled to the N sampling circuits, for outputting M clock signals from the physical medium connection layer according to the sampling results of the N sampling circuits, wherein the M clock signals are respectively associated with the M clock signals Different clock domains are related. 17. The integrated circuit of claim 12, further comprising: a control circuit, coupled to the channel selection circuit, for detecting whether one of the M channels receives a preamble signal to generate a clock selection signal, wherein when the control circuit detects the M channels When the channel in the M channels receives the preamble signal, the channel selection circuit is configured to select the channel of the M channels according to the clock selection signal. 18. The integrated circuit of claim 12, wherein the channel selection circuit is configured to select a channel among the M channels according to a clock selection signal; the integrated circuit further comprises: a control circuit, coupled to the channel selection circuit, for generating the clock selection signal according to the channel identifier of the channel in the M channels, the clock selection signal having a channel identifier mapped to the channel the signal value. 19. The integrated circuit of claim 12, wherein the channel selection circuit is configured to couple one of the (N-M) channels to the N sampling circuits according to a data selection signal one; the integrated circuit further includes: A control circuit, coupled to the channel selection circuit, is used for generating the data selection signal according to the channel identifier of the channel in the (N-M) channels, the data selection signal having a mapping to the ( The signal value of the channel identifier of the channel of the N-M) channels. 20. A physical layer of a receiver, comprising: The physical medium connection layer has N first channels, and is used to select M channels among the N first channels as M first clock channels according to the first group of clock selection signals, and according to the M first clock channels M first clock signals on the clock channel, output M second clock signals respectively related to M different clock domains, where M is an integer greater than 1; The physical coding sublayer is coupled to the physical medium connection layer and has N second channels, and the physical coding sublayer is used to select M channels among the N second channels according to the second set of clock selection signals. selecting M second clock channels, and receiving the M second clock signals through the M second clock channels; and The control circuit is arranged in one of the physical medium connection layer and the physical coding sub-layer, and is used for generating the first group of clock selection signals and the second group of clock selection signals according to the control input.

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