JPH0653938A - Serial data transmission system - Google Patents

Abstract

PURPOSE:To reduce the scale of an error inspecting circuit in in a receiving part, and to prevent a data area to be transmitted from being decreased by sharing an inspection bit generating circuit in transmitting part at every serial data. CONSTITUTION:A transmitting part 2 is equipped with plural parallel/serial data conversion circuits 31-3n which alternately insert two kinds of constants (a) and (-a) into the specific bit area of transmitted serial data by each frame and each serial data transmission line, and an inspection bit generating circuit 4 which prepares inspection bit information corresponding to the entire serial data transmission lines by each bit unit for an inspection information line. A receiving part 1 is equipped with a bit/constant inspecting circuit 3 which operates an error inspection per-bit corresponding to the plural serial data transmission lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data transmission system, and more particularly to a serial data transmission system having a plurality of serial data transmission lines and the transfer timings of the serial data transmission lines being synchronized.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 5, this type of serial data transmission system uses n serial data transmission lines 1.
, 10n through 01, 102, ..., 10n
, N connected in parallel to each other, which receives P (parallel) input to the transmission unit 6 and converts it into serial data, and n-parallel conversion circuits 81, 82, ... -N check bit generation circuits 71, 72, ..., 7n that are transformed into the output of the serial conversion circuit are provided.

On the other hand, the receiving unit 5 converts n received serial data into parallel data and restores them to obtain P (parallel) outputs. N serial-parallel data conversion circuits 51 to 5n.
, And n error checking circuits 61, 62, ..., 6n for detecting an error in the received serial data.

[0004]

In this conventional serial data transmission system, since error detection is performed in units of each serial data transmission line of a plurality of serial data transmission lines, it is proportional to the increase in the number of serial data transmission lines. Therefore, in order to increase the circuit scale of each error detection circuit of the transmitter and the receiver and to increase the error detection rate, it is necessary to provide an error check code area in the transmission information area in addition to the parity bit. However, there is a problem that the data area to be transmitted is reduced accordingly.

The object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a serial data transmission system in which an increase in circuit scale for error detection and a reduction in transmission data area are significantly suppressed.

[0006]

According to the method of the present invention, parallel data is converted into serial data from an opposite transmission side via an n-line serial data transmission line, and the serial data is transmitted. In a serial data transmission method for converting and restoring parallel data, an inspection information line provided in parallel with the n-line serial data transmission line,
N parallel-serial conversion circuits and the inspection information, in which a constant a and two constants of (-) a having logically opposite polarities are alternately assigned for each frame in a specific bit area before and after the transmission information converted into serial data. The serial data input via the n-line serial data transmission line, and the transmission side having a test bit generation circuit for generating and transmitting the inspection bit information for the n-line serial data transmission line for each line. And a receiver having a bit / constant check circuit for checking the two types of constants in the specific bit area including the bit and error check on a bit-by-bit basis.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a serial data transmission system according to an embodiment of the present invention.

The configuration of the embodiment shown in FIG. 1 is such that n lines of serial data transmission lines 101, 102, ...
It has a receiving unit 1 and a transmitting unit 2 which are connected to each other via a line inspection information line 10P.

The transmitting section 2 includes n parallel-serial data conversion circuits 31, 3 corresponding to n serial data lines.
2, ..., 3n, and a check bit generation circuit 4 for generating a check bit to be superimposed on the output of each of the parallel-serial data conversion circuits.

Further, the receiving unit 1 has a structure provided with n serial-parallel data conversion circuits 11, 12, ..., 1n and a bit / constant check circuit 3 for detecting an error in the received serial data. ..

Next, the operation of this embodiment will be described.

The n parallel-serial data conversion circuits 31 to 3n of the transmission unit 2 include the parallel information contained in the P (parallel data) input as serial data information serial data information (1) to (n) as shown in FIG. , And serial data information (1) to (n) of each serial data string transmitted to the serial data transmission lines 101, 102, ..., 10n.
For a pair of specific bit areas A1 and A2 before and after, a pair of constants (a, (-) having different logical polarities for each frame.
In step a), the logical polarities are alternately converted and assigned line by line.

Here, the symbol (-) indicates the logical reverse polarity of the constant a, and for example, if the constant a is 1, (-) a will be 0.

Further, from the check bit generating circuit 4, FIG.
As shown in the inspection information line 10P, the inspection bit information corresponding to all the serial data transmission lines is generated and output for every bit unit, and predetermined constants P and P ′ are assigned before and after the inspection bit information and transmitted.

FIG. 4 is a diagram showing a specific example of transmission data on the serial data transmission line and the inspection information line, and shows the case where the serial data transmission line is four lines as an example.

In FIG. 4, the inspection information is an odd parity check, and A1 = is assigned to the specific bit areas A1 and A2 of the four serial data transmission lines 101 to 104, respectively.
(0,1,0,1) and A2 = (1,0,1,0) are assigned.

The receiving unit 5 converts the serial data input by the n serial-parallel data conversion circuits 21 to 2n into parallel data and obtains n P (parallel data) outputs. The serial data input to the n serial-parallel conversion circuits 21 to 2n is also input to the bit / constant check circuit 3.

The bit / constant check circuit 3 performs error detection on the n-line serial data transmission lines 101 to 10n by performing a bit-unit error check and a match check of the constants P and P '.

FIG. 2 is a block diagram of the bit / constant checking circuit 3 of FIG.

The bit / constant checking circuit 3 includes a comparing circuit 7
A two constant setting circuit 8 for setting two constants, a parity check circuit 9 for performing a parity check, a timing generation circuit 12, and an OR gate 11 are provided. Error detection is performed based on the constant check result and the bit count result by the parity check circuit 11.

[0022]

As described above, according to the present invention, in the serial data transmission system in which the data converted into the parallel data is transmitted through the n-line serial data transmission line, and the parallel data is again received at the receiving side, the transmitting unit For the circuit for inserting two kinds of constants for error detection alternately into the two specific bit areas assigned to the converted serial data for each serial data transmission line and the inspection information line arranged in parallel with the serial data transmission line. A bit / constant for detecting the inspection information corresponding to each of the n serial data transmission lines in the receiving unit. By providing the inspection circuit, even if the number of serial data transmission lines is increased, the error inspection performance is not deteriorated, and the small-scale circuit structure is provided. Transmitting unit in, effect that the receiving unit can be constructed.

[Brief description of drawings]

FIG. 1 is a block diagram of a serial data transmission system according to an embodiment of the present invention.

FIG. 2 is a block diagram of a bit / constant check circuit 3 of FIG.

FIG. 3 is a time chart showing a basic configuration of transmission data of the present invention.

FIG. 4 is a time chart showing a specific example of transmission data in the embodiment of FIG.

FIG. 5 is a block diagram of a conventional serial data transmission system.

[Explanation of symbols]

 1,5 Receiver 2,6 Transmitter 3 bits / constant check circuit 4 check bit generation circuit 7 comparison circuit 8 2 constant setting circuit 9 parity check circuit 10 timing generation circuit 21-2n series-parallel data conversion circuit 31-3n Parallel-serial data conversion circuit 51-5n Serial-parallel data conversion circuit 61-6n Error checking circuit 71-7n Check bit generating circuit 81-8n Parallel-serial data converting circuit

Claims (1)

[Claims] 1. A serial data transmission system in which parallel data is converted into serial data from a transmission side opposite thereto via an n-line serial data transmission line and transmitted, and the received serial data is converted into parallel data and restored. In the above, in the inspection information line juxtaposed to the n-line serial data transmission line, and two constants, a constant a and a logically opposite polarity (-) a, in a specific bit area before and after the transmission information converted into serial data. Transmissions having n parallel-serial conversion circuits for alternately allocating each of the frames and a test bit generation circuit for generating and transmitting the test bit information for the n lines of serial data transmission lines for each bit to the test information line. On the side and before the specific bit area included in the serial data input through the n-line serial data transmission line. A serial data transmission system, comprising: a receiving unit having a bit / constant checking circuit that checks two kinds of constants and also performs a bit-unit error check.