SU944130A1 - Device for correcting errors in code combination - Google Patents

Description

The invention relates to telecommunications and can be used in an atma. transmission format - receiving discrete information. A device for correcting errors in a code combination is known, comprising a first threshold block connected in series, a first key, a first modulo-two adder, an AND element, a second modulo-yes, a first OR element and an error detection block, as well as a second threshold block and sequentially the second OR element and the accumulator are connected, while the inputs of the first and second threshold units are dineny, and the output of the second unit is connected to the second Bxoty of the spice And, the first and second outputs of the first key are connected respectively to the second th inputs of the second adder modulo two and the first OR l. However, the known device is characterized by low noise immunity. The purpose of the invention is to increase the interference of sustainability. The goal is achieved by the fact that the device for correcting errors in a code sequence comprising a first threshold block connected in series, a first key, a first modulo two adder, an AND element, a second modulo two, a first OR element, and an error detection unit, as well as the second threshold unit and the second OR element connected in series and the accumulator, while the inputs of the first and second threshold units are combined, and the output of the second threshold unit is connected to the second input of the And element, the first and second the outputs of the first key are connected respectively to the second inputs of the second modulo-two adder and the first element OR, a second key is entered and in series, connected to the third modulo-modulator by pressure N, the BANE element, the output of which is connected to the first input of

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element OR, to the second input of which the first output of the error detection unit is connected, the second output of which is connected to the second input of the first key, the second input of the BAN element, the third Bxotv of the second element OR and the control input of the second key to the information coke of which is connected the output of the accumulator, and the outputs of the second key are connected respectively to the third U in the first element OR and the second input of the first modulo two, while the outputs of the first modulo two are connected to the inputs of the first and second modules th threshold blokov.15

The drawing shows a structural electrical circuit of the proposed device.

The device contains the first threshold block I, the second threshold block 2, 20 elements OR 3 and 4, adders 5-7 modulo two, keys 8 and 9, prohibition item 1O, drive 11, element 12, error detection block 13.

The device operates as follows.

The received code combination enters the inputs of the first and second threshold blocks 1 and 2. From the output of the first threshold block 1, the first modification of the code combination through the first key 8, the first element OR 3 enters the error detection unit 13.

In addition, the same sequence is fed to the first input of the third adder 7, the second input of which receives erase signals from the output of the second threshold unit 2, previously converted into single signals. From the output of the third adder 7 modulo-two code combination, whose positions are embedded by erase signals (second Mtvdifikadi) goes through element 1O BAN, the second element OR 4 to the accumulator 11. Error detection unit 13 performs a code check of the first modification combination . If no errors are detected, the first modification is output to the output of the device. In case of detection of errors, the error detection unit 13 50 outputs the first modification on the first output through the second element OR 4 to the accumulator 11. At the same time, the second modification modi is output from the storage device 11, which through the second key 55 9, the first element OR 3 enters the detection unit 13 mistakes. If the error is not detected, then the second mod.

qi is issued to the devices on the device. In the event of an error of € 1, block 13 of error detection gives BTOIDUTO a modification of the code combination the second element OR

4c accumulator 11. Once, from the error detection unit 13, signals are sent to the control inputs of keys 8 and 9, to the second input of the element 10 BAN. From accumulator 11, the first modification of the code pattern of the first repetition goes through the second key 9 to the second input of the first adder 5 modulo two. Modulo two to the first input of the first adder 5 via the first kilo 8 comes from the output of the first threshold blc

1 combination of the first modification. To correct errors in the first adder

5 according to the dea module, a parallel alignment of both combinations occurs. The result of the equalization goes to the input from the inputs of the input 12, the other: whose input signals are erased from the output of the second threshold unit 2. Inverting the elements of the second repeat combination of the second adder 6 modulo occurs in the event that the inputs of the element And 12 at the same time there is a discrepancy of the first adder 5 modulo two and the signal to erase

from the second threshold of block 2. The corrected combination arrives at block 13, the error detection is issued to the recipient.

The use of the proposed device provides an increase in noise immunity and speed of transmission by reducing the number of retransmissions.

Claims (1)

Invention Formula Device for fixing errors in code combination, soda | each first per-threshold threshold block, the first key, the first modulo two, the AND element, the second adder, modulo two first OR element and error detection unit, and the second threshold block of the successively connected second OR element and accumulator, with In this case, the inputs of the first and second threshold units are combined, and the output of the second threshold unit is connected to the second input of the element I, the first and second outputs of the first key are connected respectively to the second inputs of the second modulo two and ttepBoro element nta OR, different from the fact that, in order to increase the noise immunity, the second key and serially connected third modulo two adder and the BAN, the output of which is connected to the first input of the second OR element, the second output of which is connected to the second input error detection, the second output of which is connected to the second input of the first key, the second input, the BAN element, the third input of the second OR element and the control input of the second key, to the information input of which is connected the output of the accumulator, and the outputs of the second key are connected respectively to the third input of the first element OR and the second input of the first modulo-two adder, while the outputs of the first and second modules are connected to the inputs of the third modulo-two adder. Sources of information taken into account in the examination I. USSR Copyright Certificate No. 634469, cl. H 04 L I / IO, 1977 i (prototype).