RU102403U1 - INFORMATION STORAGE DEVICE - Google Patents

Abstract

 An information storage device comprising a memory unit, an input coding unit, generating control bit values r1 and r2 by adding modulo 2 information symbols x1, x2, x3, y1, y2, y3 to the inputs of the input coding unit, in accordance with the rule: r1 = x1⊕x2⊕u1⊕u2; r2 = х2⊕х3⊕у2⊕у3, the output coding unit, which forms the values of the test check bits r1П, r2П by adding modulo 2 information symbols х1C, х2C, х3C, у1C, у2C, у3C, received at the inputs of the output encoding unit and received at reading information from the information outputs of the memory node in accordance with the rule: r1P = x1C⊕x2C⊕u1C⊕u2C; r2P = х2C⊕х3C⊕у2C⊕у3C, error detection block, first block of AND elements, AND element, first block of OR elements, device zeroing input, write input, read input, address inputs, information inputs, synchronization input, information outputs, signal output when an error occurs, characterized in that it further comprises a second block of OR elements, a second block of elements, a third block of AND elements, and the input to the zero state, write input, read input, address inputs are connected respectively to the first , to the second, third and fourth inputs of the memory node, the information inputs are connected to the fifth inputs of the memory node and to the first inputs of the second block of OR elements, the second inputs of which are connected to the outputs of the second block of AND elements, and the outputs are connected to the inputs of the coding block, the outputs of which are connected to sixth inputs of the memory node and to the first inputs of the error detection unit, the synchronization input is connected to the seventh input of the memory node and to the first inputs of

Description

An information storage device with increased reliability of operation relates to computer technology and can be used to increase the reliability of the operation of information storage and transmission devices.

A memory device with a parity check [1] is known, comprising a memory node, an input unit for generating an additional parity check bit, an output unit for generating an additional parity check bit, an ambiguity element, information inputs of the device are connected to the memory node and to the inputs of the input additional generating unit parity check, the outputs of the memory node are the information outputs of the device and are connected to the inputs of the output block of the formation of an additional discharge A parity check, the output of which is connected to the first input of the disambiguation element, the second input of the disambiguation element is connected to the output of the input unit for generating an additional parity check digit, and a signal is removed from its output when an error occurs.

The disadvantage of this device is the low reliability of the device, since only single (odd) errors are detected, i.e. 50% of possible errors are detected.

The closest in technical solution is a device for storing and transmitting information with the detection of double errors [2], containing a memory node, an input coding unit, an output coding unit, an error detection unit, a block of AND elements, an AND element, an OR element, an input to set the device to zero status, write input, read input, address inputs, information inputs, synchronization input, information outputs, signal output in case of an error, zero input, write input, read input, address inputs are connected to the first, second, third and fourth inputs of the memory node, respectively, information inputs are connected to the fifth inputs of the memory node and to the inputs of the input coding block, the outputs of which are connected to the sixth inputs of the memory node, the synchronization input is connected to the seventh input of the memory node and the first inputs of the block of elements And and the element And, the first outputs of the memory node are connected to the inputs of the output coding block and to the second inputs of the block of elements And, the outputs of the output coding block are connected to the first inputs of the detection block Errors, to second inputs of which are connected the second output of the storage unit, and outputs connected to inputs of the OR gate, an output of OR connected to the second input of the AND gate, the outputs of the block elements and data outputs are device yield and the element is the output signal when an error occurs.

The disadvantage of this device is a large hardware redundancy, since two coding units are used: an input coding unit and an output information coding unit.

The purpose of the utility model is to reduce hardware costs by using a single coding unit that encodes input and output information.

This goal is achieved in that the device containing the memory node, the coding unit, the error detection unit, the first block of AND elements, the AND element, the first block of OR elements, the input of setting the device to zero, write input, read input, address inputs, information inputs , the synchronization input, information outputs, the signal output when an error occurs, further comprises a second block of OR elements, a second block of elements, a third block of AND elements, and the input is in the zero state, the write input, the read input I, the address inputs, are connected respectively to the first, second, third and fourth inputs of the memory node, the information inputs are connected to the fifth inputs of the memory node and to the first inputs of the second block of OR elements, the second inputs of which are connected to the outputs of the second block of AND elements, and the outputs are connected to the inputs of the coding block, the outputs of which are connected to the sixth inputs of the memory node and to the first inputs of the error detection block, the synchronization input is connected to the seventh input of the memory node and to the first inputs of the first block of AND elements and to the first input to the And element, the first outputs of the memory node are connected to the second inputs of the first block of And elements and to the first inputs of the second block of And elements, the second input of which is connected to the read input, the second outputs of the memory node are connected to the second inputs of the error detection unit, the outputs of which are connected to the inputs the first block of OR elements, the output of which is connected to the second input of the AND element, the outputs of the first block of AND elements are information outputs of the device, the output of the AND element is the signal output when an error occurs.

Figure 1 shows a block diagram of an information storage device .. The information storage device contains: a memory unit 1, an encoding unit 2, an error detection unit 3, a first block of 4 OR elements, a second block of 5 OR elements, a first block of 6 AND elements, a second block 7 elements AND, element 8 AND, input 9 to zero, input 10 records, input 11 reads, address inputs 12, information inputs 13, synchronization input 14, information outputs 15, signal output 16 when an error occurs.

The input 9 is set to zero, input 10 records, input 11 reads, address inputs 12 are connected respectively to the first, second, third and fourth inputs of the memory node 1, information inputs 13 are connected to the fifth inputs of the memory node 1 and to the first inputs of the second block 5 OR elements, the second inputs of which are connected to the outputs of the second block of 7 AND elements, and the outputs are connected to the inputs of the coding unit 2, the outputs of which are connected to the sixth inputs of the memory unit 1 and to the first inputs of the error detection unit 3, the synchronization input 14 is connected to the seventh the first input of the memory node 1 and to the first inputs of the first block of 6 And elements, and to the first input of the 8 And element, the first outputs of the memory node 1 are connected to the second inputs of the first block of 6 And elements and to the first inputs of the second block of 7 And elements, the second input of which is connected to the read input 11, the second outputs of the memory node 1 are connected to the second inputs of the error detection unit 3, the outputs of which are connected to the inputs of the first block of 4 elements OR, the output of which is connected to the second input of the element 8 AND, the outputs of the first block of 6 elements AND are information outputs and device 15 output 16 and the element 8 is the output signal when an error occurs.

The memory node 1, in this case, is a static semiconductor operational memory device and is designed to store code sets: _K = x ₁ x ₂ x ₃ , y ₁ y ₂ y ₃ r ₁ r ₂ obtained when encoding the original binary sets: = x ₁ , x ₂ , x ₃ , y ₁ , y ₂ , y ₃ .

Block 2 encoding is intended for the formation of the values of the control bits r ₁ , r ₂ by adding mod2 information symbols in accordance with the rule:

r ₁ = x ₁ ⊕x ₂ ⊕y ₁ ⊕y ₂ ;

r ₂ = x ₂ ⊕x ₃ ⊕y ₂ ⊕y ₃ .

and, the formation of the values of the test check bits r _1P , gzp by adding mod2 information symbols (x _iC , y _iC ) obtained by reading information from the memory node 1 in accordance with the rule:

_1H r = x _1C ⊕x _2C ⊕y _1C ⊕r _2C;

r _2P = x _2C ⊕x _3C ⊕y _2C ⊕y _3C .

Block 3 error detection is designed to detect errors in the code set when reading information from the memory node 1 by adding mod2 values of the control bits r _1C and r _2C , read from the second outputs of the memory node 1, respectively, with the values of the control bits r _1P and r _2P , formed at the outputs of the output coding unit 3:

λ ₁ = r _1C ⊕r _1P ;

λ ₂ = r _2C ⊕r _2P .

A zero result of the sum indicates the absence of an error, and its presence otherwise.

The outputs λ ₁ and λ _{2 of} block 3 are combined into one output by the first block of 4 elements OR, the signal value at this output goes to the second input of element 8 I.

Reading the output information from the outputs 15 of the device is carried out upon receipt of a signal from the input 14 of the synchronization to the first inputs of the first block of 6 elements And element 8 I.

The device operates as follows. Before starting the operation of the device, a single signal is applied to the input 9 of the "zero state", which puts the device into zero state.

When recording information in the memory node 1, a single signal is supplied to the recording input 10, address inputs 12 and information inputs 13.

For example, the information combination receives the code combination: x ₁ x ₂ x ₃ y ₁ y ₂ y ₃ corresponding to the value - 000110

In this case, the input coding unit 2 generates a vector:

r ₁ = x ₁ ⊕x ₂ ⊕y ₁ ⊕y ₂ = 0; r ₂ = x ₂ ⊕x ₃ ⊕y ₂ ⊕y ₃ = 1.

Accordingly, information is written to the memory node 1:

00011001.

When reading information at the input 11 of the reading and address inputs 12, signals are given that allow the reading of information from the node 1 memory at the specified address. The information to be read is fed to the second inputs of the first block of 6 AND elements and the inputs of the second block of 7 AND elements, from the outputs of which information is supplied through the second block of 5 OR elements to coding block 2. Coding block 2 with respect to information bits generates values: r _1P = 0 and R _2P = 1 which, in the absence of error, are equal to r _1C and r _2C , respectively, therefore, at the output of comparison block 3 we have the values: λ ₁ = 0, λ ₂ = 0 .

Suppose an error occurred in the first information category: 1 * 00 110 01. In this case, at the outputs of coding unit 2, we obtain the signal values: r _1P = 1 and r _2P = 1. Since the value of r _1P ≠ r _1C (1 ≠ 0), then at the output of block 3 of comparison we get the values of the signals: λ ₁ = 1, λ ₂ = 0, respectively, at the output of the first block 4 OR, a single value of the signal will appear, which when a signal is received from synchronization input 14, it will go to the output of element 8 AND, which indicates an error. Similarly, the device works when other errors occur.

Compared with the prototype, the device uses one coding block instead of two. Since the coding block is built on mod2 combiners, which contain four simple two-input elements each, its hardware will be (kk / 3-1) 2 * 4 i.e., for six information bits the hardware costs of the coding block will be 24 two-input logical elements. The total hardware costs for the additionally introduced the second block of 7 AND elements, the second block of 5 OR elements will be 12 two-input logic elements.

Thus, the proposed device allows to reduce hardware costs, compared with the prototype, by 12 two-input logic elements.

INFORMATION SOURCES

1. B. M. Kogan, I.B. Mkrtumyan Fundamentals of computer operation. M. - Energoatom published, 1988, 430 p., Fig. 4.17.

2. Patent for utility model No. 76479 "Memory device with detection of double errors" / Boroday V.E., Bobkov S.G., Osipenko P.N., Pavlov A.A., Tsarkov A.N., from o4. 2008/04

Appendix to the application for a utility model: “Information storage device”

The effectiveness of automated control systems, information systems, computer and measuring equipment, information storage and transmission devices is largely determined by the reliability of the information that is processed in these systems [1].

In turn, the reliability of the functioning of digital devices substantially depends on the selected method for detecting errors (the detecting ability of the selected method for monitoring information and hardware costs necessary for implementing this method). Currently, for this purpose, the parity check method is most widely used, which requires minimal hardware costs for detecting binary set errors. The disadvantage of this method is its low detecting ability, since only odd errors are detected. At the same time, the experience of operating discrete devices shows that the most probable event is the occurrence of single and double errors (respectively, single errors account for 80-85%, double errors 25–20% and errors of other multiplicity up to 2%) [1] , i.e. The main disadvantage of the parity check method is the inability to detect double errors.

The method of controlling information by mod3 has a much greater detecting ability, however, the implementation of this method requires large hardware costs for constructing convolution schemes and time costs associated with the delay in the passage of the signal.

In this regard, there is a need to develop a method of information control that detects 100% of single errors and the maximum number of double errors, with minimal hardware and time costs for decoding.

Justification of the method of coding information

Let the initial binary set be represented by three information bits:

To detect errors of a given multiplicity, it is necessary to ensure that the condition for the code distance d [1] is satisfied:

where t is the number of error bits in the code set.

To detect a double error, it is necessary to provide a code distance d≥3, respectively, for this purpose, it is necessary to use two control bits.

Since the reliability of the operation and the processing speed of the controlled information substantially depends on the hardware costs associated with the formation of the values of the control bits, it becomes necessary to choose a method of encoding information that provides minimal hardware costs.

Due to the fact that the parity check, in relation to the known error detection methods, requires minimal time and hardware costs, it is advisable to use the information coding method to detect double errors, requiring for its implementation hardware and time costs commensurate with the costs necessary when using parity control method.

Studies conducted for this purpose have shown that for the task at hand it is advisable to use independent orthogonal checks. So, for a three-digit binary set Y = x ₁ , x ₂ , x _{3, the} formation of the values of two control bits can be carried out by two checks: r ₁ = x ₁ ⊕x ₂ and r ₂ = x ₂ ⊕x ₃ .

Accordingly, the code set is represented as:

In Tab. 1 shows the detecting ability of the received code with respect to error-free code set: Y _K = 00000.

Note: The symbol "*" indicates a sign of a detected error in the corresponding control category, the symbol "-" - not detected; Undetectable errors are shown in bold; oblique font represents double errors.

The analysis of Table 1 shows that out of thirty-one erroneous code sets, seven error sets are not detected, while 100% of single errors are detected, and out of ten double errors, one error is not detected.

If we take into account that 80% of errors are accounted for by a single error, and »20% by a double error, then the proposed coding method can significantly increase the probability of detecting errors that occur.

To encode three-bit information by the proposed method, two adders with mod2 are required, i.e. the same number of adders as for parity.

For decoding information (comparing the control digits of the transmitted and received information) for the proposed method, one adder is required one more adder with respect to the parity control, while the information processing speed not only does not decrease, but also decreases, because along the signal path, when encoding and decoding information using the proposed method, there is one adder (two for parity).

When encoding a binary set with an arbitrary number of information bits (let the number of information bits be a multiple of three), we divide the binary set into blocks of information, three bits in each block:

As a result of encoding the binary set in question by the proposed method, we obtain the code set:

or

Example: Let the number of information bits be six, then, for the considered number of information bits we have a code set:

Table 2. erroneous code sets for single and double errors with respect to error-free code set are presented: 00000000.

The analysis of Table 2 shows that single errors are detected 100%, out of twenty-six double errors, six are not detected. The binary method coding by the proposed method will require six mod2 adders (for parity testing, five mod2 adders). Decoding the code set for the proposed method will require eight adders mod2 (for parity six adders mod2).

The total hardware cost for the proposed coding method will be fourteen adders in mod2, and for parity, eleven adders in mod2.

In this case, for the proposed method, when decoding information on the signal path, there are four adders in mod2 (the formation of the values of two control bits is carried out in parallel), and for adherence to parity there are six adders in mod2.

Thus, the proposed error detection method allows to detect all single errors and the maximum number of double errors with a slight increase in hardware costs in relation to the parity control method, without reducing the speed of information processing.

Information storage device Table 1. No. Error Code Set: 000000 No. Error Code Set: 000000 Invalid Code Sets Sign of error: Invalid Code Sets Error sign r ₁ r ₂ r ₁ r ₂ one 00001 - * 17 10001 * * 2 00010 * - eighteen 10010 - - 3 00011 * * 19 10011 - - four 00100 - - * twenty 10100 * * 5 00101 * - 21 10101 * - 6 00110 * * 22 10110 - * 7 00111 * - 23 10111 - - 8 01000 * * 24 11000 - * 9 01001 - - 25 11001 - - 10 01010 - * 26 11010 * * eleven 01011 * * 27 11011 * 12 01100 * - 28 11100 - - 13 01101 - * 29th 11101 - * fourteen 01110 - - thirty 11110 * - fifteen 01111 * * 31 11111 * * 16 10,000 -

Information storage device Table 2. No. Error code set 00000000 Error sign No. Error code set 00000000 Error sign Invalid Code Set r ₁ r ₂ Invalid Code Set r ₁ r ₂ one 00000001 - * 19 00100010 * * 2 00000010 * - twenty 01000010 - * 3 00000100 - * 21 10000010 - - four 00001000 * * 22 00001100 * - 5 00010000 * - 23 00010100 * * 6 00100000 - * 24 00100100 - - 7 01000000 * * 25 01000100 * - 8 10,000,000 * - 26 10000100 * * 9 00000011 * * 27 00011000 - * 10 00000101 - - 28 00101000 * - eleven 00001001 * - 29th 01001000 - - 12 00010001 * * thirty 10001000 - * 13 00100001 - - 31 00110000 * * fourteen 01000001 * - 32 01010000 - * fifteen 10000001 * - 33 10010000 - - 16 00000110 * * 34 01100000 * - 17 00001010 - * 35 10 100 000 * * eighteen 00010010 36 11000000 *

Claims (1)

An information storage device comprising a memory unit, an input coding unit, generating control bit values r1 and r2 by adding modulo 2 information symbols x1, x2, x3, y1, y2, y3 to the inputs of the input coding unit, in accordance with the rule: r1 = x1⊕x2⊕u1⊕u2; r2 = х2⊕х3⊕у2⊕у3, the output coding unit that generates the values of the test check bits r1 _П , r2 _П by modulo addition of 2 information symbols х1 _C , х2 _C , х3 _C , у1 _C , у2 _C , у3 _C , received the inputs of the output coding unit and information obtained by reading information from the memory unit outputs according to the rule: r1 = x1 _P ⊕h2 _{C C C} ⊕u1 ⊕u2 _C; r2 _П = х2 _C ⊕х3 _C ⊕у2 _C ⊕у3 _C , error detection block, first block of AND elements, AND element, first block of OR elements, input to set the device to zero, write input, read input, address inputs, information inputs , a synchronization input, information outputs, a signal output when an error occurs, characterized in that it further comprises a second block of OR elements, a second block of elements, a third block of AND elements, and the zero input, write input, read input, address inputs are connected respectively to p the first, second, third and fourth inputs of the memory node, the information inputs are connected to the fifth inputs of the memory node and to the first inputs of the second block of OR elements, the second inputs of which are connected to the outputs of the second block of AND elements, and the outputs are connected to the inputs of the encoding block, the outputs of which are connected to the sixth inputs of the memory node and to the first inputs of the error detection unit, the synchronization input is connected to the seventh input of the memory node and to the first inputs of the first block of AND elements and to the first input of the AND element, the first outputs of the memory node are connected They are connected to the second inputs of the first block of AND elements and to the first inputs of the second block of AND elements, the second input of which is connected to the read input, the second outputs of the memory node are connected to the second inputs of the error detection unit, the outputs of which are connected to the inputs of the first block of OR elements, the output of which is connected to the second input of the AND element, the outputs of the first block of AND elements are information outputs of the device, the output of the AND element is the signal output when an error occurs.