RU2421786C1 - Device to store information of higher functioning validity - Google Patents

Abstract

FIELD: information technologies. ^ SUBSTANCE: initial binary information is coded on the basis of organisation of independent inspections and due to introduction of a coding unit, an error detection unit, the first unit of elements AND, the second unit of elements AND, an element AND, the first unit of elements OR, element 4 OR. ^ EFFECT: higher validity of storage devices functioning and information transfer with provision of the possibility to detect single and binary errors with minimum time and hardware expenditures. ^ 1 dwg, 2 tbl, 1 app

Description

The invention relates to computer technology and can be used to increase the reliability of the operation of devices for storage and transmission of information.

A memory device with a parity check [1] is known, comprising a memory node, an input unit for generating an additional parity check bit, an output unit for generating an additional parity check bit, an ambiguity element, information inputs of the device are connected to the memory node and to the inputs of the input additional generating unit parity check, the outputs of the memory node are the information outputs of the device and are connected to the inputs of the output block of the formation of an additional discharge A parity check, the output of which is connected to the first input of the disambiguation element, the second input of the disambiguation element is connected to the output of the input unit for generating an additional parity check digit, and a signal is removed from its output when an error occurs.

The disadvantage of this device is the low reliability of the device, since only single (odd) errors are detected, i.e. 50% of possible errors are detected.

The closest in technical solution is a device for storing and transmitting information with the detection of double errors [2], containing a memory node, an input coding unit, an output coding unit, an error detection unit, a block of AND elements, an AND element, an OR element, an input to set the device to zero status, write input, read input, address inputs, information inputs, synchronization input, information outputs, signal output in case of an error, zero input, write input, read input, address inputs These are connected respectively to the first, second, third and fourth inputs of the memory node, the information inputs are connected to the fifth inputs of the memory node and to the inputs of the input coding block, the outputs of which are connected to the sixth inputs of the memory node, the synchronization input is connected to the seventh input of the memory node and to the first the inputs of the block of elements AND and the element AND, the first outputs of the memory node are connected to the inputs of the output coding block and to the second inputs of the block of elements AND, the outputs of the output coding block are connected to the first inputs of the detection unit errors, the second inputs of which are connected to the second outputs of the memory node, and the outputs are connected to the inputs of the OR element, the output of the OR element is connected to the second input of the AND element, the outputs of the AND block are information outputs of the device, the output of the AND element is the signal output when an error occurs.

The disadvantage of this device is a large hardware redundancy, since two coding units are used: an input coding unit and an output information coding unit.

The aim of the invention is to reduce hardware costs through the use of a single coding unit that encodes input and output information.

This goal is achieved in that the device containing the memory node, the coding unit, the error detection unit, the first block of AND elements, the AND element, the first block of OR elements, the input of setting the device to zero, write input, read input, address inputs, information inputs , the synchronization input, information outputs, the signal output when an error occurs, further comprises a second block of OR elements, a second block of elements, a third block of AND elements, and the input is in the zero state, the write input, the read input I, the address inputs are connected respectively to the first, second, third and fourth inputs of the memory node, the information inputs are connected to the fifth inputs of the memory node and to the first inputs of the second block of OR elements, the second inputs of which are connected to the outputs of the second block of AND elements, and the outputs are connected to the inputs of the encoding block, the outputs of which are connected to the sixth inputs of the memory node and to the first inputs of the error detection block, the synchronization input is connected to the seventh input of the memory node and to the first inputs of the first block of AND elements and to the first input for the And element, the first outputs of the memory node are connected to the second inputs of the first block of And elements and to the first inputs of the second block of And elements, the second input of which is connected to the read input, the second outputs of the memory node are connected to the second inputs of the error detection unit, the outputs of which are connected to the inputs the first block of OR elements, the output of which is connected to the second input of the AND element, the outputs of the first block of AND elements are information outputs of the device, the output of the AND element is the signal output when an error occurs.

The drawing shows a block diagram of a device. The device for storing information of increased reliability of operation contains a memory unit 1, an encoding unit 2, an error detection unit 3, a first block of 4 OR elements, a second block of 5 OR elements, a first block of 6 AND elements, a second block of 7 AND elements, an 8 AND element, input 9 zeroing, write input 10, read input 11, address inputs 12, information inputs 13, synchronization input 14, information outputs 15, signal output 16 when an error occurs.

The input 9 is set to zero, input 10 records, input 11 reads, address inputs 12 are connected respectively to the first, second, third and fourth inputs of the memory node 1, information inputs 13 are connected to the fifth inputs of the memory node 1 and to the first inputs of the second block 5 OR elements, the second inputs of which are connected to the outputs of the second block of 7 AND elements, and the outputs are connected to the inputs of the coding unit 2, the outputs of which are connected to the sixth inputs of the memory unit 1 and to the first inputs of the error detection unit 3, the synchronization input 14 is connected to the seventh mu input of the memory node 1 and to the first inputs of the first block of 6 AND elements, and to the first input of the 8 AND element, the first outputs of the memory node 1 are connected to the second inputs of the first block of 6 AND elements and to the first inputs of the second block of 7 AND elements, the second input of which is connected to the read input 11, the second outputs of the memory node 1 are connected to the second inputs of the error detection unit 3, the outputs of which are connected to the inputs of the first block of 4 elements OR, the output of which is connected to the second input of the element 8 AND, the outputs of the first block of 6 elements AND are information outputs and 15 devices, the output 16 of the element 8 And is the output of the signal when an error occurs.

The memory node 1, in this case, is a static semiconductor operational memory device and is designed to store the code sets Y _K = x ₁ x ₂ x ₃ y ₁ y ₂ y ₃ r ₁ r ₂ obtained by encoding the original binary sets Y = x ₁ , x ₂ , x ₃ , y ₁ , y ₂ , y ₃ .

The coding unit 2 is intended for generating the values of the control bits r ₁ , r ₂ by adding mod2 information symbols in accordance with the rule

;

;

and the formation of the values of the test check bits r _1P , r _2P by adding mod2 information symbols (x _iC , Y _iC ) obtained when reading information from the memory node 1 in accordance with the rule

;

;

.

.

Block 3 error detection is designed to detect errors in the code set when reading information from the memory node 1 by adding mod2 values of the control bits r _1C and r _2C , read from the second outputs of the memory node 1, respectively, with the values of the control bits r _1P and r _2P , formed at the outputs of the output coding unit 3:

;

;

.

.

A zero result of the sum indicates the absence of an error and its presence otherwise.

The outputs λ ₁ and λ ₂ of the comparison block 3 are combined into one output by the first block of 4 elements OR, the signal value at this output goes to the second input of element 8 I.

Reading the output information from the outputs 15 of the device is carried out upon receipt of a signal from the input 14 of the synchronization to the first inputs of the first block of 6 elements And element 8 I.

The device operates as follows. Before starting the operation of the device, a single signal is applied to the input 9 of the "zero state", which puts the device into zero state.

When recording information in the node 1 of the memory a single signal is fed to the input 10 of the record, address inputs 12 and information inputs 13.

For example, the information combination receives the code combination x ₁ x ₂ x ₃ y ₁ y ₂ y ₃ corresponding to a value of -000 110.

In this case, the input coding unit 2 generates a vector

;

.

;

.

Accordingly, information is written to the memory node 1

000 110 01.

When reading information at the input 11 of the reading and address inputs 12, signals are given that allow the reading of information from the node 1 memory at the specified address. The information to be read is fed to the second inputs of the first block of 6 AND elements and the inputs of the second block of 7 AND elements, from the outputs of which information is supplied through the second block of 5 OR elements to coding block 2. The coding unit 2 with respect to the information bits generates the values r _1P = 0 and r _2P = 1, which, in the absence of an error, are equal to the values r _1C and r _2C , respectively, therefore, at the output of the comparison unit 3, we have the values λ ₁ = 0, λ ₂ = 0.

Suppose an error occurred in the first information category: 1 * 00 110 01. In this case, at the outputs of coding unit 2, we obtain the signal values r _1P = 1 and r _2P = 1. Since the value of r _1P ≠ r _1C (1 ≠ 0), then at the output of block 3 of comparison we get the values of the signals λ ₁ = l, λ ₂ = 0, respectively, at the output of the first block 4 OR, a single signal value appears, which, when a signal arrives with input 14 synchronization will go to the output of element 8 And, which indicates the occurrence of an error. Similarly, the device works when other errors occur.

Compared with the prototype, the device uses one coding block instead of two. Since the coding block is based on mod2 adders, which contain four simple two-input elements each, its hardware costs will be (k-k / 3-l) 2 * 4, i.e. for six information bits, the hardware cost of the coding unit will be 24 two-input logic elements. The total hardware costs for the additionally introduced the second block of 7 AND elements, the second block of 5 OR elements will be 12 two-input logic elements.

Thus, the proposed device allows to reduce hardware costs compared with the prototype by 12 two-input logic elements.

Information sources

1. B.M. Kogan, I. B. Mkrtumyan. Fundamentals of computer operation. M .: Energoatomizdat, 1988, 430 p., Fig. 4.17.

2. Patent for utility model No. 76479 "Memory device with detection of double errors" / Boroday V.E., Bobkov S.G., Osipenko P.N., Pavlov A.A., Tsarkov A.N., from o4. 2008/04

Appendix to the application for the invention: "A device for storing information of high reliability"

The effectiveness of automated control systems, information systems, computer and measuring equipment, information storage and transmission devices is largely determined by the reliability of the information that is processed in these systems [1].

In turn, the reliability of the operation of digital devices substantially depends on the selected method for detecting errors (the detecting ability of the selected method for monitoring information and hardware costs necessary to implement this method). Currently, for this purpose, the parity check method is most widely used, which requires minimal hardware costs for detecting binary set errors. The disadvantage of this method is its low detecting ability, since only odd errors are detected. At the same time, the experience of operating discrete devices shows that the most probable event is the occurrence of single and double errors (respectively, single errors account for 80-85%, double errors 25–20% and errors of other multiplicity up to 2%) [1, t .e. The main disadvantage of the parity check method is the inability to detect double errors.

The method of controlling information by mod3 has a much greater detecting ability, however, the implementation of this method requires large hardware costs for constructing convolution schemes and time costs associated with the delay in the passage of the signal.

In this regard, there is a need to develop a method of information control that detects 100% of single errors and the maximum number of double errors, with minimal hardware and time costs for decoding.

Justification of the method of coding information

Let the initial binary set be represented by three information bits:

To detect errors of a given multiplicity, it is necessary to ensure that the condition for the code distance d [1] is satisfied:

where t is the number of error bits in the code set.

To detect a double error, it is necessary to provide a code distance d≥3, respectively, for this purpose, it is necessary to use two control bits.

Since the reliability of the operation and the processing speed of the controlled information substantially depend on the hardware costs associated with the formation of the values of the control bits, it becomes necessary to choose a method of encoding information that provides minimal hardware costs.

Due to the fact that the parity check with respect to the known error detection methods requires minimal time and hardware costs, it is advisable to use the information coding method to detect double errors, requiring for its implementation hardware and time costs commensurate with the costs required when using parity control method.

и

.Studies conducted for this purpose have shown that for the task at hand it is advisable to use independent orthogonal checks. So, for a three-digit binary set Y = x ₁ x ₂ x _{3, the} formation of the values of two control bits can be carried out by two checks:

and

.

Accordingly, the code set is represented as

In the table. 1 shows the detecting power of a received code with respect to an error-free code set Y _k = 000 00.

Note: The symbol "*" indicates a sign of a detected error in the corresponding control category, the symbol "-" - undetectable; Undetectable errors are in bold; oblique font represents double errors.

The analysis of Table 1 shows that out of thirty-one erroneous code sets, seven error sets are not detected, while 100% of single errors are detected, and of ten double errors, one error is not detected.

If we take into account that 80% of errors are accounted for by a single error, and ≈ 20% by a double error, then the proposed coding method can significantly increase the probability of detecting errors that arise.

To encode three-bit information by the proposed method, two adders with mod2 are required, i.e. the same number of adders as for parity.

To decode the information (comparing the control bits of the transmitted and received information) for the proposed method with respect to the parity control, one adder is needed more, while the information processing speed is not only not reduced, but also reduced, because on the path of the signals during the encoding and decoding of information by the proposed method, there is one adder (two for parity control).

When encoding a binary set with an arbitrary number of information bits (let the number of information bits be a multiple of three), we divide the binary set into blocks of information, three bits in each block:

As a result of encoding the binary set in question by the proposed method, we obtain a code set

or

Example: Let the number of information bits be six, then for the considered number of information bits we have a code set

Table 2 shows the error code sets for single and double errors with respect to error-free code set: 000000 00.

An analysis of Table 2 shows that single errors are detected 100%, of the twenty-six double errors, six are not detected. The binary method coding by the proposed method will require six mod2 adders (for parity testing, five mod2 adders). Decoding the code set for the proposed method will require eight adders mod2 (for parity six adders mod2).

The total hardware cost for the proposed coding method will be fourteen adders mod2, and for parity - eleven adders mod2.

In this case, for the proposed method, when decoding information on the signal path, there are four adders by mod2 (the formation of the values of two control bits is carried out in parallel), and for adder parity by six adders by mod2.

Thus, the proposed error detection method allows to detect all single errors and the maximum number of double errors with a slight increase in hardware costs in relation to the parity control method without reducing the processing speed of information.

Table 1 Information storage device with increased reliability of operation No. p / p Error Code Set: 000000 No. p / p Error Code Set: 000000 Invalid Code Sets Sign of error: Invalid Code Sets Error sign r ₁ r ₂ r ₁ r ₂ one 000 01 - * 17 100 01 * * 2 000 10 * - eighteen 100 10 - - 3 000 11 * * 19 100 11 - - four 001 00 - - * twenty 101 00 * * 5 001 01 * - 21 101 01 * - 6 001 10 * * 22 101 10 - * 7 001 11 * - 23 101 11 - - 8 010 00 * * 24 110 00 - * 9 010 01 - - 25 110 01 - - 10 010 10 - * 26 110 10 * * eleven 010 11 * * 27 110 11 * - 12 011 00 * - 28 111 00 - - 13 011 01 - * 29th 111 01 - * fourteen 011 10 - - thirty 111 10 * - fifteen 011 11 * * 31 111 11 * * 16 100 00 -

table 2 Information storage device with increased reliability of operation No. p / p Error Code Set 000 000 00 Error sign No. p / p Error Code Set 000 000 00 Error sign Invalid Code Set r ₁ r ₂ Invalid Code Set r ₁ r ₂ one 000 000 01 - * 19 001 000 10 * * 2 000 000 10 * - twenty 010 000 10 - * 3 000 001 00 - * 21 100,000 10 - - four 000 010 00 * * 22 000 011 00 * - 5 000 100 00 * - 23 000 101 00 * * 6 001 000 00 - * 24 001 001 00 - - 7 010 000 00 * * 25 010 001 00 * - 8 100,000 00 * - 26 100 001 00 * * 9 000 000 11 * * 27 000 110 00 - * 10 000 001 01 - - 28 001 010 00 * - eleven 000 010 01 * - 29th 010 010 00 - - 12 000 100 01 * * thirty 100 010 00 - * 13 001 000 01 - - 31 001 100 00 * * fourteen 010 000 01 * - 32 010 100 00 - * fifteen 100 000 01 * - 33 100 100 00 - - 16 000 001 10 * * 34 011 000 00 * - 17 000 010 10 - * 35 101 000 00 * * eighteen 000 100 10 - - 36 110 000 00 - *

Claims (1)

A device for storing information of increased reliability of operation, containing a memory node, an input coding unit that generates the values of the control bits r1 and r2 by adding modulo 2 information symbols x ₁ , x ₂ , x ₃ , y ₁ , y ₂ , y ₃ to the inputs input coding block, in accordance with the rule: r1 = x1⊕x2⊕y1⊕y2; r2 = х2⊕х3⊕y2⊕у3, the output coding unit that generates the values of the test check bits r1 _p , r2 _p by adding modulo 2 information symbols x1 _s , x2 _s , x3 _s , y1 _c , y2 _c , y3 _c to the inputs of the output coding block and the information obtained when reading information from the information outputs of the memory node in accordance with the rule: r1 _p = x1 _with ⊕x2 _with ⊕y1 _c ⊕y2 _c ; r2 _n = x2 _c ⊕х3 _s ⊕y2 _c ⊕y3 _c , error detection block, first block of AND elements, element AND, first block of OR elements, input to set the device to zero, write input, read input, address inputs, information inputs , a synchronization input, information outputs, a signal output when an error occurs, characterized in that it further comprises a second block of OR elements, a second block of AND elements, a third block of AND elements, and the input to the zero state, write input, read input, address inputs are connected respectively to p the first, second, third and fourth inputs of the memory node, the information inputs are connected to the fifth inputs of the memory node and to the first inputs of the second block of OR elements, the second inputs of which are connected to the outputs of the second block of AND elements, and the outputs are connected to the inputs of the encoding block, the outputs of which are connected to the sixth inputs of the memory node and to the first inputs of the error detection unit, the synchronization input is connected to the seventh input of the memory node and to the first inputs of the first block of AND elements and to the first input of the AND element, the first outputs of the memory node are connected They are connected to the second inputs of the first block of AND elements and to the first inputs of the second block of AND elements, the second input of which is connected to the read input, the second outputs of the memory node are connected to the second inputs of the error detection unit, the outputs of which are connected to the inputs of the first block of OR elements, the output of which is connected to the second input of the AND element, the outputs of the first block of AND elements are information outputs of the device, the output of the AND element is the signal output when an error occurs.