RU175054U1 - STORAGE AND TRANSMISSION DEVICE WITH SINGLE AND DOUBLE ERRORS - Google Patents

Abstract

The proposed utility model is intended to increase the reliability of the operation of information storage and transmission devices by detecting single and double errors while reducing hardware costs. This is achieved by encoding the source binary information based on the organization of checks and by introducing an input coding unit 2, an output coding unit 3, an error detection unit 4, an AND element 5 block, an AND element 6, an OR element block 7. 1 ill.

Description

A useful model of a device for storing and transmitting data with the detection of single and double errors relates to computer technology and can be used to increase the reliability of the functioning of storage devices.

A memory device with detection of double errors [1] is known, comprising a memory node, an input coding unit generating the values of the control bits r ₁ , r ₂ and r ₃ , an output coding unit that generates the values of the checking control bits r _1p , r _2p , r _3p , error detecting unit, OR element block, AND element block, AND element, device input to zero state, write input, read input, address inputs, information inputs, synchronization input, information outputs, signal output when an error occurs, installation input zero state, write input, read input, address inputs, synchronization input are connected respectively to the first, second, third and fourth, fifth inputs of the memory node, information inputs are connected to the sixth inputs of the memory node and to the inputs of the input encoder, the outputs of which are connected to the seventh the inputs of the memory node, the information outputs of the memory node are connected to the inputs of the output coding block and to the first inputs of the block of elements AND, the outputs of the output coding block are connected to the first inputs of the block detect ibs, the second inputs of which are connected to the control bits output of the memory node, and the outputs are connected to the inputs of the OR block, the output of which is connected to the first input of the AND element, the second input of the AND block and the second input of the AND element are connected to the synchronization input, the outputs of the first block of elements And are the information outputs of the device, the output of the element And is the output of the "Error" signal, the input coding unit generates the value of the control bits r ₁ by adding modulo 2 Information symbols y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ , y ₁₂ received at its inputs, in accordance with the rule: r ₁ = y _{3 3} y ₄ ⊕ y ₅ ⊕ y ₆ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ ⊕ y ₁₂ , the value of the control digit r ₂ - by adding modulo 2 information symbols y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ , y ₁₂ , arriving at its inputs, in accordance with the rule: r ₂ = y ₃ ⊕ y ₆ ⊕ y ₇ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ ⊕ y ₁₂ , the value of the control discharge r ₃ - by adding module 2 information symbols y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ , y ₁₂ coming to its inputs, in accordance with the rule: r ₃ = y ₁ ⊕ y ₂ ⊕ y ₄ ⊕ y ₅ ⊕ y ₇ ⊕ y ₈ ⊕ y ₁₀ ⊕ y ₁₁ , output a coding unit generating the values of the check check bits r _1p , r _2p , r _3p by adding modulo 2 information symbols y _1p , y _2p , y _3p , y _4p , y _5p , y _6p , y _7p , y _8p , y _9p , y _10p , y _11p , y _12p coming to its inputs when reading information from the information outputs of the memory node in accordance with the rule: r _1p = y _3p ^⊕ y _4p ^⊕ y _5p ^⊕ y _6p ^⊕ y _9p ^⊕ y _10p ^⊕ y _11p ^⊕ y _12p ; r _2p = y _3p ^⊕ y _6p ^⊕ y _7p ^⊕ y _8p ^⊕ y _9p ^⊕ y _10p ^⊕ y _11p ^⊕ y _12p ; r _3p = y _1p ^⊕ y _2p ^⊕ y _4p ^⊕ y _5p ^⊕ y _7p ^⊕ y _8p ^⊕ y _10p ^⊕ y _11p , the error detection unit performs bitwise addition mod2 values of the control bits r _1S , r _2S and r _3S , read from the second the outputs of the memory node 1, respectively, with the values of the control bits r _1p , r _2p , r _3p generated at the outputs of the output coding unit 3.

The disadvantage of this device is the low detecting ability of double errors, since 10% of the number of possible single and double errors is detected (see the appendix).

The closest in technical solution is a device for storing and transmitting data with error detection [2], containing a memory node, an input coding unit that generates the values of the control bits r ₁ , r ₂ and r ₃ , an output coding unit that generates the values of the control control bits r _1p , r _2p , r _3p , error detection block, OR element block, AND element block, AND element, input of the device to the zero state, write input, read input, address inputs, information inputs, synchronization input, information outputs, you the signal flow when an error occurs, the setup input is in the zero state, the write input, read input, address inputs, synchronization input are connected respectively to the first, second, third and fourth, fifth inputs of the memory node, information inputs are connected to the sixth inputs of the memory node and to the inputs input encoding device, the outputs of which are connected to the seventh inputs of the memory node, the information outputs of the memory node are connected to the inputs of the output coding block and to the first inputs of the block of elements AND, the outputs of the output block of code The inputs are connected to the first inputs of the error detection unit, the second inputs of which are connected to the outputs of the control bits of the memory node, and the outputs are connected to the inputs of the element block OR whose output is connected to the first input of the AND element, the second input of the block of AND elements and the second input of the AND element are connected to the input synchronization, the outputs of the first block of the AND outputs are information devices, and an output of the output signal is "Error", the input encoding unit generates the reference value r ₁ of the discharge by adding a modulo-2 information symbols y _1, y _2, y _3, y _4, y _5, y _6, y _7, y _8, y _9, y _10, y _11, y ₁₂ received at its inputs, in accordance with Rule : r ₁ = y ₃ ⊕ y ₆ ⊕ y ₇ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ ⊕ y ₁₂ , the value of the control digit r ₂ - by adding modulo 2 information symbols y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ , y ₁₂ coming to its inputs, in accordance with the rule: r ₂ = y ₂ ⊕ y ₄ ⊕ y ₅ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ ⊕ y ₁₂ , the value of the control digit r ₃ - by adding modulo 2 information symbols y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ , y ₁₂ , arriving at its inputs, in accordance with the rights silt: r ₃ = y ₁ ⊕ y ₄ ⊕ y ₅ ⊕ y ₆ ⊕ y ₇ ⊕ y ₁₀ ⊕ y ₁₁ ⊕ y ₁₂ , the output coding block that generates the values of the test check bits r _1p , r _2p , r _3p , by adding module 2 information symbols y _1p , y _2p , y _3p , y _4p , y _5p , y _6p , y _7p , y _8p , y _9p , y _10p , y _11p , y _12p received at its inputs when reading information from information outputs memory node, in accordance with the rule: r _1p = y _3p ⊕ y _6p ⊕ y _7p ⊕ y _8p ⊕ y _9p ⊕ y _10p ⊕ y _11p ⊕ y _12p ; r _2p = y _2p ⊕ y _4p ⊕ y _5p ⊕ y _8p ⊕ y _9p ⊕ y _10p ⊕ y _11p ⊕ y _12p ; r _3p = y _1p ⊕ y _4p ⊕ y _5p ⊕ y _6p ⊕ y _7p ⊕ y _10p ⊕ y _11p ⊕ y _12p , the error detection unit performs bitwise addition mod2 of the values of the control bits r _1S , r _2S and r _3S , read from the second the outputs of the memory node 1, respectively, with the values of the control bits r _1p , r _2p , r _3p , formed at the outputs of the output coding unit 3.

The disadvantage of this device is the increased hardware redundancy.

The purpose of the utility model is to reduce hardware redundancy due to rational coding of information.

This goal is achieved in that a useful model of a data storage and transmission device with the detection of single and double errors, containing a memory node, an input coding unit that generates the values of the control bits r ₁ , r ₂ and r ₃ , an output coding unit that generates the values of the control control bits r _1p , r _2p , r _3p , error detection block, block of OR elements, block of AND elements, AND element, input of setting the device to zero, write input, read input, address inputs, information inputs, synchronization input, inf formation outputs, signal output in case of an error, zero input, write input, read input, address inputs, synchronization input are connected respectively to the first, second, third and fourth, fifth inputs of the memory node, information inputs are connected to the sixth inputs of the memory node and to the inputs of the input encoder, the outputs of which are connected to the seventh inputs of the memory node, the information outputs of the memory node are connected to the inputs of the output coding block and to the first inputs of the block of elements AND, the output The output coding block is connected to the first inputs of the error detection block, the second inputs of which are connected to the outputs of the control bits of the memory node, and the outputs are connected to the inputs of the block of OR elements, the output of which is connected to the first input of the AND element, the second input of the AND block and the second input of the element And connected to the synchronization input, the outputs of the first block of elements AND are information outputs of the device, the output of the element AND is the output of the "Error" signal, characterized in that the input coding unit generates the control discharge r ₁ by adding modulo 2 information symbols y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ , y ₁₂ its inputs, in accordance with the rule: r ₁ = y ₃ ⊕ y ₆ ⊕ y ₇ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ , the value of the control digit r ₂ - by adding modulo 2 information symbols y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ , y ₁₂ coming to its inputs, in accordance with the rule: r ₂ = y ₂ ⊕ y ₄ ⊕ y ₅ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ , the value of the control digit r ₃ - by adding modulo 2 information symbols y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ , y ₁₂ coming to its inputs, in accordance with the rule: r ₃ = y ₁ ⊕ y ₄ ⊕ y ₅ ⊕ y ₆ ⊕ y ₇ ⊕ y ₁₀ ⊕ y ₁₁ ⊕ y ₁₂ , the output coding block that generates the values of the test check bits r _1p , r _2p , r _3p , by adding modulo 2 information symbols y _1p , y _2p , y _3p , y _4p , y _5p , y _6p , y _7p , y _8p , y _9p , y _10p , y _11p , y _12p , arriving at inputs when reading information from the information outputs of the memory node, in accordance with the rule: r _1p = y _3p ⊕ y ₆ p ⊕ y _7p ⊕ y _8p ⊕ y _9p ⊕ y _10p ⊕ y _11p ; r _2p = y _2p ⊕ y _4p ⊕ y _5p ⊕ y _8p ⊕ y _9p ⊕ y _10p ⊕ y _11p ; r _3p = y _1p ⊕ y _4p ⊕ y _5p ⊕ y _6p ⊕ y _7p ⊕ y _10p ⊕ y _11p ⊕ y _12p , the error detection unit performs bitwise addition mod2 of the values of the control bits r _1S , r _2S and r _3S , read from the second the outputs of the memory node 1, respectively, with the values of the control bits r _1p , r _2p , r _3p , formed at the outputs of the output coding unit 3.

In FIG. 1 is a block diagram of a utility model of a data storage and transmission device with detection of single and double errors. The utility model contains: memory node 1, input coding unit 2, output coding unit 3, error detection unit 4, unit 5 AND, element 6 AND, unit 7 OR, input 8 zeroing, input 9 entries, input 10 readings, address inputs 11, information inputs 12, synchronization input 13, information outputs 14, output 15 "Error".

The zero input 8, the write input 9, the read input 10, the address inputs 11, the synchronization input 13 are connected to the first, second, third and fourth, fifth inputs of the memory node 1, respectively, the information inputs 12 are connected to the sixth inputs of the memory node 1 and to the inputs of the input encoder 2, the outputs of which are connected to the seventh inputs of the memory node 1, the information outputs of the memory node 1 are connected to the inputs of the output coding unit 3 and to the first inputs of the block 5 elements And, the outputs of the output coding unit 3 are connected to the first inputs of the error detection unit 4, the second inputs of which are connected to the outputs of the control bits of the memory unit 1, and the outputs are connected to the inputs of the OR unit 7, the output of which is connected to the first input of the 6 AND element, the second input of the 5 AND element block and the second input of the 6 AND element connected to the input 13 of the synchronization unit 5 outputs of AND gates are outputs information device 6 and an output of the output signal is "Error", characterized in that the input encoding unit generates the discharge control value of addition by r ₁ Ia modulo 2 information symbols y _1, y _2, y _3, y _4, y _5, y _6, y _7, y _8, y _9, y _10, y _11, y ₁₂ received at its inputs, in accordance with rule:

r ₁ = y ₃ ⊕ y ₆ ⊕ y ₇ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ , the value of the control digit r ₂ - by adding modulo 2 information symbols y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ , y ₁₂ supplied to its inputs, in accordance with the rule: r ₂ = y ₂ ⊕ y ₄ ⊕ y ₅ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ , the value of the control digit r ₃ - by adding modulo 2 information symbols y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ , y ₁₂ arriving at its inputs, in accordance with the rule: r ₃ = y ₁ ⊕ y ₄ ⊕ y ₅ ⊕ y ₆ ⊕ y ₇ ⊕ y ₁₀ ⊕ y ₁₁ ⊕ y ₁₂ , the output coding unit 3, which generates the values test check bits r _1p , r _{2 p} , r _3p , by adding modulo 2 information symbols y _1p , y _2p , y _3p , y _4p , y _5p , y _6p , y _7p , y _8p , y _9p , y _10p , y _11p , y _12p , arriving at its inputs when reading information from the information outputs of the memory node in accordance with the rule:

r _1p = y _3p ⊕ y ₆ p ⊕ y _7p ⊕ y _8p ⊕ y _9p ⊕ y _10p ⊕ y _11p ; r _2p = y _2p ⊕ y _4p ⊕ y _5p ⊕ y _8p ⊕ y _9p ⊕ y _10p ⊕ y _11p ; r _3p = y _1p ⊕ y _4p ⊕ y _5p ⊕ y _6p ⊕ y _7p ⊕ y _10p ⊕ y _11p ⊕ y _12p , error detection unit 4 performs bitwise addition mod2 values of the control bits r _1S , r _2S and r _3S read from the second outputs of the memory node 1, respectively, with the values of the control bits r _1p , r _2p , r _3p generated at the outputs of the output coding unit 3.

The memory node 1, in this case, is a static semiconductor operational memory device and is designed to store code words: У _К = y ₁ y ₂ y ₃ y ₄ y ₅ y ₆ y ₇ y ₈ y ₉ , y ₁₀ y ₁₁ y ₁₂ r ₁ r ₂ r ₃ obtained by encoding the source information.

The input coding unit 2 is designed to generate the values of the control bits r ₁ , r ₂ , r ₃ , by adding mod2 information symbols in accordance with the rule:

r ₁ = y ₃ ⊕ y ₆ ⊕ y ₇ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ ;

r ₂ = y ₂ ⊕ y ₄ ⊕ y ₅ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ ;

r ₃ = y ₁ ⊕ y ₄ ⊕ y ₅ ⊕ y ₆ ⊕ y ₇ ⊕ y ₁₀ ⊕ y ₁₁ ⊕ y ₁₂ .

The output coding unit 3 is intended to generate the values of the test check bits r _1p , r _2p , r _3p , by adding mod2 information symbols received when reading information from the memory node 1 in accordance with the rule:

r _1p = y _3p ⊕ y ₆ p ⊕ y _7p ⊕ y _8p ⊕ y _9p ⊕ y _10p ⊕ y _11p ;

r _2p = y _2p ⊕ y _4p ⊕ y _5p ⊕ y _8p ⊕ y _9p ⊕ y _10p ⊕ y _11p ;

r _3p = y _1p ⊕ y _4p ⊕ y _5p ⊕ y _6p ⊕ y _7p ⊕ y _10p ⊕ y _11p ⊕ y _12p .

Block 4 error detection is designed to detect errors in the code word when reading information from the memory node 1 by adding mod2 values of the control bits r _1S , r _2S and r _3S read from the second outputs of the memory node 1, respectively, with the values of the control bits r _1p , r _2p and r _3p formed at the outputs of the output coding unit 3:

λ ₁ = r _1S ⊕ r _1p ;

λ ₂ = r _2S ⊕ r _2p ;

λ ₃ = r _3S ⊕ r _3p .

A zero result of the sum indicates the absence of an error, and its presence otherwise.

The outputs λ ₁ , λ ₂ , λ ₃ of the error detection unit 4 are combined into one output by the first element 7 OR, the signal value at this output receives the first input of element 6 I.

Reading the output information from the outputs 14 of the device is carried out upon receipt of a signal from the input 13 of the synchronization to the second input of the block of 5 elements And and the second input of the element 6 I.

The device operates as follows. Before starting the operation of the device, a single signal is applied to input 8 of the "Set to zero state", which transfers the memory node 1 to the zero state.

When recording information in the memory node 1, a single signal is fed to the recording input 9, address inputs 11 and information inputs 12.

.For example, a twelve-digit word arriving at the information inputs has the following meanings in its ranks:

.

The input coding unit 2 will generate the values of the control bits:

r ₁ = y ₃ ⊕ y ₆ ⊕ y ₇ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ = 0 ⊕ 1 ⊕ 1 ⊕ 0 ⊕ 1 ⊕ 1 ⊕ 1 = 1;

r ₂ = y ₂ ⊕ y ₄ ⊕ y ₅ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ = 1 ⊕ 0 ⊕ 0 ⊕ 0 ⊕ 1 ⊕ 1 ⊕ 1 = 0;

r ₃ = y ₁ ⊕ y ₄ ⊕ y ₅ ⊕ y ₆ ⊕ y ₇ ⊕ y ₁₀ ⊕ y ₁₁ ⊕ y ₁₂ = 1 ⊕ 0 ⊕ 0 ⊕ 1 ⊕ 1 ⊕ 1 ⊕ 1 ⊕ 1 = 0.

(последние четыре разряда являются контрольными разрядами), которое записывается в узле 1 памяти.As a result, we have a codeword:

(the last four digits are the control digits), which is recorded in the memory node 1.

When reading information from the memory node 1, the second coding unit 3, relative to the received information, will generate the values of the control bits: R _p = {r _1p , r _2p , r _3p ,} = {100}

If there are no errors, then we have the result: R = (100), R _p = (100), R _S = (100), λ = (000).

.Let there be a single error in the first information category:

.

At the output of the second coding unit 3, we have the result: R _p = (101), and the values of the transmitted control bits R _S = (100) are read from the second outputs of the memory unit 1.

In this case, the signals at the output of the error detection unit 4 take the value: λ = (001).

Accordingly, at the output of the OR block 5, a single signal value will appear, which, when a signal is received from the synchronization input 13, will go to the input of element 6 And the output of which will display the "Error" signal value.

Similarly, the device works when double errors occur.

INFORMATION SOURCES

1. Patent for utility model No. 161373 "Controlled device for storing and transmitting information" / Butranov A.S., Pavlov A.A., Tsarkov A.N. et al. dated March 29, 2016

2. Patent for utility model No. 169207 "Data storage and transmission device with error detection" / Korsunsky DA, Lebedev V.L., Mashevich P.R. Pavlov A.A., Plis N.I., Steshenko V.B., Khamaganov K.B., Tsarkov A.N. Tsarkov A.N. and others from 10.17.2016.

Appendix to the application for the utility model “Storage and data transmission device with detection of single and double errors”

1. Introduction

With the increasing complexity of modern information management and processing systems (ICS), as well as in extreme working conditions (exposure to electromagnetic or radiation radiation, etc.), the likelihood of errors in the processed information increases.

The correct operation of the entire computing channel of the SDMS to a large extent depends on the error-free operation of the memory device.

One of the promising directions of ensuring the reliability of the operation of an IMSS is the development of controlled storage devices based on linear algebraic codes that provide automatic error detection.

In this regard, the correction code used to protect these devices must satisfy at least the following requirements:

provide minimum time for encoding and decoding information;

have minimal information redundancy;

have minimal hardware costs associated with encoding and decoding information and storing the values of the control bits.

To fulfill the first requirement, algebraic linear correction codes with syndromic decoding are used (a cyclic encoding procedure and information decoding is time-consuming).

If an error of multiplicity t is detected, for the code distance d, it is necessary to satisfy the condition:

d≥t + 1.

Currently, codes that correct single and double errors, in particular, perfect systematic Hamming codes, are widely used to protect information storage devices. In this case, the number of check bits r for the code correcting a single error is determined by the expression:

where n = k + r, k is the number of information bits.

In this case, the verification matrix of the Hamming code consists of all different nonzero vectors of length r.

Since d = 3 for a given code, it can be used to detect double errors in the event of malfunctions in information storage and transmission devices.

At the same time, to ensure the fault tolerance of information storage devices, there is a need to develop methods for constructing corrective linear codes with syndrome decoding that detect all single (odd) errors and the maximum number of double (even) errors with minimal hardware and information redundancy.

Consider the rules for constructing codes with a high detecting ability of double errors.

2. Rules for constructing corrective codes, increased detecting ability

To form the control bits of the correction code with the indicated properties, we first use the well-known procedure for constructing a two-dimensional iterative code, which is as follows.

Rule 1. A binary word Y containing k information symbols is divided into m = k / b information blocks (by an information block we mean the number of information bits that do not exceed the value of b). Let b be a multiple of k.

The resulting information blocks are presented in the form of an information matrix:

As a result, we have an information matrix having m-rows and b-columns. Let: z = (b + m) be an odd number; m≥b + 1.

Then the information is encoded using the parity method (by adding mod 2 characters of rows and columns of the resulting matrix). As a result, we have a coding matrix of a two-dimensional iterative code that allows us to detect and correct any single error:

where {s ₁ , s ₂ , ..., s _b } is the column parity vector; {s _{b + 1} , s _{b + 2} , ..., s _z } is the line parity vector.

The parity vectors of rows and columns form a set of checks for the control bits of the iterative code

R _l = {r ₁ , r ₂ , ..., r _z } or R _l = r _h + r _u , r _h = log ₂ b, r _u = log ₂ (b + z + 1).

.When correcting a single error

.

.Upon receipt of a code combination with respect to information bits, the values of the control bits are re-formed

.

The difference between the transmitted values of the control bits and received after receiving the information forms the syndrome of error E.

R _l = {r ₁ , r ₂ , ..., r _z }

In this case, the bits of the error syndrome {e ₁ , e ₂ , ..., e _b } (obtained with respect to the column parity vector) indicate an erroneous bit in the information block, and the bits {e _{b + 1} , e _{b + 2} , ..., e _z } ( obtained with respect to the line parity vector) indicate the module of information having an error.

If the bits of the error syndrome {e ₁ , e ₂ , ..., e _b } have zero values, and in the bits {e _{b + 1} , e _{b + 2} , ..., e _z } there are single values (and vice versa), then this indicates the presence of errors in the control bits.

The disadvantage of the considered correction code is the large redundancy.

Rule 2. The minimization of the number of control bits for the proposed method of encoding information is carried out by logarithm of the sum of the rows and columns of the encoding matrix of the two-dimensional iterative code (2).

In this case, the number of control bits is determined by the expression:

Moreover:

While maintaining the code length n, reducing the check characters in the check matrix inevitably leads to the appearance of duplicate columns and, as a result, to the inability to detect some double errors.

The number of repetitions of the same column is:

if n is divisible without remainder.

If during division we have the remainder β, then we have β columns for which the number of repetitions is α + 1.

In this case, the number of undetected errors is determined by the expression:

Therefore, the probability of occurrence of undetected code combinations is:

Example. Suppose we have twelve information bits for which we construct a coding matrix:

The number of rows and columns of the coding matrix is seven.

The required number of control bits: r ^* = log ₂ 7 = 3, Accordingly, the code length is 15.

The verification matrix H of the code has the following form:

Checks for the formation of the values of the control bits are determined by the expression:

r ₁ = y ₃ ⊕ y ₆ ⊕ y ₇ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ ⊕ y ₁₂ ;

r ₂ = y ₂ ⊕ y ₄ ⊕ y ₅ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ ⊕ y ₁₂ ;

r ₃ = y ₁ ⊕ y ₄ ⊕ y ₅ ⊕ y ₆ ⊕ y ₇ ⊕ y ₁₀ ⊕ y ₁₁ ⊕ y ₁₂ .

.Table 1 presents the values of the syndromes when single and double errors occur in the information and control bits relative to the code word:

.

Note.

1. Of the 120 single and double errors, 9 double errors are not detected, or 7.5% of the possible number of errors (undetected double errors are shown in bold).

Thus, when encoding twelve information bits by the proposed method, it will require three control bits to detect single and double errors.

When using the proposed method for constructing an encoding device, 21 adders of mod 2 are required. To construct a decoding device, 21 adders of mod 2 and three adders of mod 2 are required to form an error syndrome, total 45 adders of mod 2.

Rule 3. To reduce hardware costs for the construction of the decoding device, it is desirable to supplement the columns of the verification matrix containing the least number of units.

In this case, the verification matrix H ₂ for the code in question has the form:

Checks for forming the values of the control bits contain two adders with mod 2 less and are determined by the expression:

r ₁ = y ₃ ⊕ y ₆ ⊕ y ₇ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ ;

r ₂ = y ₂ ⊕ y ₄ ⊕ y ₅ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ ;

r ₃ = y ₁ ⊕ y ₄ ⊕ y ₅ ⊕ y ₆ ⊕ y ₇ ⊕ y ₁₀ ⊕ y ₁₁ ⊕ y ₁₂ .

.For the code in question, table 2 presents the values of the syndromes when single and double errors occur in the information and control bits relative to the code word:

.

Thus, when constructing an encoding (decoding) device, 19 adders, i.e. hardware costs will be reduced by four adders mod 2.

Claims (1)

A device for storing and transmitting data with the detection of single and double errors, comprising a memory node, an input coding unit generating the values of the control bits r ₁ , r ₂ and r ₃ , an output coding unit generating the values of the checking control bits r _1p , r _2p , r _3p , an error detection unit, an OR element block, an AND element block, an AND element, an input for setting the device to zero, a write input, a read input, address inputs, information inputs, a synchronization input, information outputs, a signal output when an error occurs CRAs; the input to the zero state, the write input, the read input, the address inputs and the synchronization input are connected respectively to the first, second, third, fourth and fifth inputs of the memory node, the information inputs are connected to the sixth inputs of the memory node and to the inputs of the encoding input block, the outputs of which connected to the seventh inputs of the memory node, the information outputs of the memory node are connected to the inputs of the output coding block and to the first inputs of the block of elements AND, the outputs of the output coding block are connected to the first inputs of the block in Errors are detected, the second inputs of which are connected to the outputs of the control bits of the memory node, and the outputs are connected to the inputs of the OR block, the output of which is connected to the first input of the AND element, the second input of the AND block and the second input of the AND element are connected to the synchronization input, the outputs of the first block elements And are the information outputs of the device, the output of the element And is the output of the "Error" signal, characterized in that the input coding unit generates the value of the control bit r ₁ by adding modulo 2 information The symbols y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ , y ₁₂ received at its inputs, in accordance with the rule: r ₁ = y ₃ ⊕ y ₆ ⊕ y ₇ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ , the value of the control digit r ₂ - by adding modulo 2 information symbols y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ , y ₁₂ entering its inputs, in accordance with the rule: r ₂ = y ₂ ⊕ y ₄ ⊕ y ₅ ⊕ y ₈ ⊕ y ₉ ⊕ y ₁₀ ⊕ y ₁₁ , the value of the control digit r ₃ - by adding modulo 2 information symbols y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ , y ₁₂ , arriving at its inputs, in accordance with the rule: r ₃ = y ₁ ⊕ y ₄ ⊕ y ₅ ⊕ y ₆ ⊕ y ₇ ⊕ y ₁₀ ⊕ y ₁₁ ⊕ y ₁₂ , the output coding block (3) generates the values of the test check bits r _1p , r _2p , r _3p , by modulo 2 adding information symbols y _1p , y _2p , y _3p , y _4p , y _5p , y _6p , y _7p , y _8p , y _9p , y _10p , y _11p , y _12p , coming to its inputs when reading information from the information outputs of the memory node, in accordance with the rule: r _1p = y _3p ⊕ y _6p ⊕ y _7p ⊕ y _8p ⊕ y _9p ⊕ y _10p ⊕ y _11p ; r _2p = y _2p ⊕ y _4p ⊕ y _5p ⊕ y _8p ⊕ y _9p ⊕ y _10p ⊕ y _11p ; r _3p = y _1p ⊕ y _4p ⊕ y _5p ⊕ y _6p ⊕ y _7p ⊕ y _10p ⊕ y _11p ⊕ y _12p , the error detection unit (4) performs bitwise addition modulo 2 values of the control bits r _1S , r _2S and r _3S read from the second outputs of the memory node (1), respectively, with the values of the control bits r _1p , r _2p , r _3p generated at the outputs of the output coding block (3).

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