RU107606U1 - STORAGE AND TRANSMISSION DEVICE WITH SINGLE ERROR CORRECTION IN THE BYTE OF INFORMATION AND DETECTION OF ARRIVAL ERRORS IN THE BYTE OF INFORMATION - Google Patents

Abstract

 A device for storing and transmitting data with the correction of single errors in the byte of information and the detection of arbitrary errors in the bytes of information, containing a memory node, input coding unit, output coding unit, error syndrome calculation unit, decoder, switch, switch unit, corrector, corrector unit, the fact that it further comprises a first block of OR elements, a second block of OR elements, an inverter, an AND element, a block of AND elements, an input for setting the device to zero, a write input, a read input I, address inputs, 24-bit information inputs, synchronization input, information outputs, error signal output, zero input, write input, read input, address inputs, are connected to the first, second, third and fourth inputs of the node, respectively memory, the synchronization input is connected to the fifth input of the memory node and to the first input of the block of elements AND, information inputs are connected to the sixth inputs of the memory node and to the inputs of the input coding block, which generates the values of the control bits r1, r2, r3, r4, r5, r6 p Then we add modulo 2 information symbols x1x2x3, z1z2z3, a1a2a3, c1c2c3, e1e2e3, f1f2f3, g1g2g3, h1h2h3., received at the inputs of the input coding block, in accordance with the rule: r1 = x1⊕z1⊕a1⊕1⊕c g1⊕h1; r2 = x2⊕z2⊕a2⊕c2⊕e2⊕f2⊕g2⊕h2; r3 = x3⊕z3⊕a3⊕с3⊕e3⊕f3⊕g3⊕h3; r4 = x1⊕z3⊕a2⊕с2⊕c3⊕e1⊕e3⊕f1⊕f2⊕g1⊕g2⊕g3; ! r5 = x2⊕z1⊕a3⊕с1⊕c3⊕e1⊕e2⊕f2⊕f3⊕g1⊕g2⊕g3; r6 = x3⊕z2⊕a1⊕с1⊕c2⊕e2⊕e3⊕f1⊕f3⊕g1⊕g2⊕g3, which are fed to the seventh inputs of the memory node, the information outputs of the memory node are connected respectively to the first inputs of the corrector, the corrector block and the inputs output coding unit which for

Description

The utility model relates to computer technology and can be used to increase the reliability of the functioning of storage devices.

A self-correcting device is known [1], using a correction code (the most frequently used Hamming code is a single error correction and detecting a double error).

The disadvantage of this device is the low detecting ability of the code, since only double errors are detected.

The closest in technical solution is a fail-safe data storage and transmission device that implements codes correcting single errors, detecting double independent errors and detecting single error bytes [2], containing a memory node, an input encoding block, an output encoding block, an error syndrome calculation block, decoder, byte error switches, corrector, device inputs are connected to the inputs of the memory node and to the inputs of the input encoding device, the outputs of which are connected to the first inputs calculating eye syndrome, memory unit outputs are connected to second inputs of syndrome calculation unit and to first inputs of corrector unit outputs syndrome calculation are connected to inputs of the decoder, their outputs connected to second inputs of the equalizer, the equalizer output is the output device.

A disadvantage of the device is the low error detection capacity of the device, since only double independent errors and single error bytes are detected.

The purpose of the utility model is to increase the reliability of the device by correcting single errors, and detecting arbitrary errors bytes of information.

This goal is achieved in that the device containing a memory node, an input coding unit, an output coding unit, an error syndrome calculation unit, a decoder, a switch, a switch unit, a corrector, a corrector unit, characterized in that it further comprises a first block of OR elements, a second block of OR elements, inverter, AND element, block of AND elements, input to set the device to zero, write input, read input, address inputs, twenty-four bit information inputs, synchronization input, information output outputs, error output, zero input, write input, read input, address inputs are connected respectively to the first, second, third and fourth inputs of the memory node, the synchronization input is connected to the fifth input of the memory node and to the first input block of elements AND, information inputs are connected to the sixth inputs of the memory node and to the inputs of the input coding block which generates the values of the control bits r ₁ , r ₂ , r ₃ , r ₄ , r ₅ , r ₆ by adding modulo 2 information symbols x ₁ x ₂ x ₃ , z ₁ z ₂ z ₃ , a ₁ a ₂ a ₃ , c ₁ c ₂ c ₃ , e ₁ e ₂ e ₃ , f ₁ f ₂ f ₃ ; g ₁ g ₂ g ₃ , h ₁ h ₂ h ₃ , received at the inputs of the input coding block, in accordance with the rule: r ₁ = x ₁ ⊕z ₁ ⊕a ₁ ⊕с ₁ ⊕e ₁ ⊕f ₁ ⊕g ₁ ⊕ h ₁ ; r ₂ = x ₂ ⊕z ₂ ⊕a ₂ ⊕с ₂ ⊕e ₂ ⊕f ₂ ⊕g ₂ ⊕h ₂ ; r ₃ = x ₃ ⊕z ₃ ⊕a ₃ ⊕с ₃ ⊕e ₃ ⊕f ₃ ⊕g ₃ ⊕h ₃ ; r ₄ = x ₁ ⊕z ₃ ⊕a ₂ ⊕с ₂ ⊕c ₃ ⊕e ₁ ⊕e ₃ ⊕f ₁ ⊕f ₂ ⊕g ₁ ⊕g ₂ ⊕g ₃ ; r ₅ = x ₂ ⊕z ₁ ⊕a ₃ ⊕с ₁ ⊕c ₃ ⊕e ₁ ⊕e ₂ ⊕f ₂ ⊕f ₃ ⊕g ₁ ⊕g ₂ ⊕g ₃ ; r ₆ = x ₃ ⊕z ₂ ⊕a ₁ ⊕c ₁ ⊕c ₂ ⊕e ₂ ⊕e ₃ ⊕f ₁ ⊕f ₃ ⊕g ₁ ⊕g ₂ ⊕g ₃ which are fed to the seventh inputs of the memory node, information outputs of the memory node connected respectively to the first inputs of the corrector, the corrector block and the inputs of the output coding block, which generates the values of the test check bits r _1P , r _2P , r _3P , r _4P , r _5P , r _6P by adding modulo 2 information symbols x _1P x _2P x _3P , z _1P z _2P z _3P , a _1P a _2P a _3P , c _1P c _2P c _3P , e _1P e _2P e _3P , f _1P f _2P f _3P , g _1P g _2P g _3P , h _1P h _2P h _3P received at the inputs of the input coding block from the information outputs evil memory, in accordance with the rule: r _1P = x _1P ⊕z _1P ⊕a _1P ⊕s _1P ⊕e _1P ⊕f _1P ⊕g _1P ⊕h _1P ; r _2P = x _2P ⊕z _2P ⊕a _2P ⊕s _2P ⊕e _2P ⊕f _2P ⊕g _2P ⊕h _2P ; r _3P = x _3P ⊕z _3P ⊕a _3P ⊕s _3P ⊕e _3P ⊕f _3P ⊕g _3P ⊕h _3P ; r _4P = x _1P ⊕z _3P ⊕a _2P ⊕c _2P ⊕c _3P ⊕e _1P ⊕e _3P ⊕f _1P ⊕f _2P ⊕g _1P ⊕g _2P ⊕g _3P ; r _5P = x _2P ⊕z _1P ⊕a _3P ⊕c _1P ⊕c _3P ⊕e _1P ⊕e _2P ⊕f _2P ⊕f _3P ⊕g _1P ⊕g _2P ⊕g _3P ; r _6P = x _3P ⊕z _2P ⊕a _1P ⊕c _1P ⊕c _2P ⊕e _2P ⊕e _3P ⊕f _1P ⊕f _3P ⊕g _1P ⊕g _2P ⊕g _3P ; the outputs of the output coding unit are connected to the first inputs of the error syndrome calculation unit to the second inputs of which the outputs of the control bits of the memory node are connected, the first outputs of the error syndrome calculation unit are connected to the first inputs of the decoder, to the first inputs of the switch, to the inputs of the first block of OR elements, and to the first the inputs of the switch block, the second outputs of the error syndrome calculation block are connected to the second inputs of the decoder and to the second inputs of the first block of OR elements, the outputs of the decoder are connected to the WTO inputs of the second block of OR elements, with the first output of the decoder connected to the second input of the switch, and the second outputs connected to the second inputs of the block of switches, the output of the second block of OR elements through an inverter connected to the first input of the AND element, the second input of which is connected to the output of the first block of OR elements , the output of the AND element is the output of the “error” signal, the switch outputs are connected to the second inputs of the corrector, the outputs of the switch block are connected to the second inputs of the corrector block, the outputs of the corrector and the corrector block under lyucheny to second inputs of the AND block whose outputs are information device outputs.

Figure 1 presents a block diagram of a utility model. A device for storing and transmitting data with the correction of single errors in the byte of information and the detection of arbitrary errors in the bytes of information contains: memory node 1, input coding block 2, output coding block 3, error syndrome calculation block 4, decoder 5, switch 6, switch block 7 , corrector 8, corrector block 9, first element 10 OR, second element 11 OR, inverter 12, element 13 AND, block 14 elements AND, input 15 to zero, input 16 records, input 17 read, address inputs 18, information inputs 19, input 20 sync ronization, information outputs 21, output 22 of the error signal.

The input 15 is set to zero, input 16 records, input 17 read, address inputs 18 are connected respectively to the first, second, third and fourth inputs of the memory node 1, the synchronization input 20 is connected to the fifth input of the memory node 1 and to the first input of block 14 elements And, the information inputs 19 are connected to the sixth inputs of the memory node 1 and to the inputs of the encoding input unit 2, which generates the values of the control bits r ₁ , r ₂ , r ₃ , r ₄ , r ₅ , r ₆ by adding modulo 2 information symbols x ₁ x ₂ x ₃ , z ₁ z ₂ z ₃ , a ₁ a ₂ a ₃ , c ₁ c ₂ c ₃ , e ₁ e ₂ e ₃ , f ₁ f ₂ f ₃ ; g ₁ g ₂ g ₃ , h ₁ h ₂ h _3. , coming to the inputs of the input coding block 2, in accordance with the rule: r ₁ = x ₁ ⊕z ₁ ⊕a ₁ ⊕с ₁ ⊕e ₁ ⊕f ₁ ⊕g ₁ ⊕h ₁ ; r ₂ = x ₂ ⊕z ₂ ⊕a ₂ ⊕с ₂ ⊕e ₂ ⊕f ₂ ⊕g ₂ ⊕h ₂ ; r ₃ = x ₃ ⊕z ₃ ⊕a ₃ ⊕с ₃ ⊕e ₃ ⊕f ₃ ⊕g ₃ ⊕h ₃ ; r ₄ = x ₁ ⊕z ₃ ⊕a ₂ ⊕с ₂ ⊕c ₃ ⊕e ₁ ⊕e ₃ ⊕f ₁ ⊕f ₂ ⊕g ₁ ⊕g ₂ ⊕g ₃ ; r ₅ = x ₂ ⊕z ₁ ⊕a ₃ ⊕с ₁ ⊕c ₃ ⊕e ₁ ⊕e ₂ ⊕f ₂ ⊕f ₃ ⊕g ₁ ⊕g ₂ ⊕g ₃ ; r ₆ = x ₃ ⊕z ₂ ⊕a ₁ ⊕с ₁ ⊕c ₂ ⊕e ₂ ⊕e ₃ ⊕f ₁ ⊕f ₃ ⊕g ₁ ⊕g ₂ ⊕g ₃ , which are fed to the seventh inputs of the memory node 1, information outputs of the memory node are connected respectively to the first inputs of the corrector, 8 block 9 of the corrector and to the inputs of the output coding block 3, which generates the values of the test check bits r _1P , r _2P , r _3P , r _4P , r _5P , r _6P by modulo 2 information characters x _1P x _2P x _3P , z _1P z _2P z _3P , a _1P a _2P a _3P , c _1P c _2P c _3P , e _1P e _2P e _3P , f _1P f _2P f _3P , g _1P g _2P g _3P , h h _{1P 2P 3P} h fed to the input of the input unit 3 coding information O rows of memory unit 1 in accordance with the rule: r = x _{1P 1P 1P} ⊕z ⊕a ⊕s _{1P 1P 1P} ⊕e ⊕f ⊕g _{1P 1P 1P} ⊕h; r _2P = x _2P ⊕z _2P ⊕a _2P ⊕s _2P ⊕e _2P ⊕f _2P ⊕g _2P ⊕h _2P ; r _3P = x _3P ⊕z _3P ⊕a _3P ⊕s _3P ⊕e _3P ⊕f _3P ⊕g _3P ⊕h _3P ; r _4P = x _1P ⊕z _3P ⊕a _2P ⊕c _2P ⊕c _3P ⊕e _1P ⊕e _3P ⊕f _1P ⊕f _2P ⊕g _1P ⊕g _2P ⊕g _3P ; r _5P = x _2P ⊕z _1P ⊕a _3P ⊕c _1P ⊕c _3P ⊕e _1P ⊕e _2P ⊕f _2P ⊕f _3P ⊕g _1P ⊕g _2P ⊕g _3P ; r _6P = x _3P ⊕z _2P ⊕a _1P ⊕c _1P ⊕c _2P ⊕e _2P ⊕e _3P ⊕f _1P ⊕f _3P ⊕g _1P ⊕g _2P ⊕g _{3P the} outputs of the encoding output unit 3 are connected to the first inputs of the calculation unit 4 an error syndrome, to the second inputs of which the outputs of the control bits of the memory node 1 are connected, the first outputs of the calculation unit 4 of the error syndrome are connected to the first inputs of the decoder 5, to the first inputs of the switch 6, to the inputs of the first block of 10 OR elements and to the first inputs of block 7 of the switches , the second outputs of the error syndrome calculation unit 4 are connected to the second inputs of the decoder 5 and to the second inputs the first block of 10 OR elements, the outputs of the decoder 5 are connected to the inputs of the second block 11 of the OR elements, while the first output of the decoder 5 is connected to the second input of the switch 6, and the second outputs are connected to the second inputs of the block 7 of the switches, the output of the second block of 11 OR elements through an inverter 12 is connected to the first input of the element 13 AND, the second input of which is connected to the output of the first block of 10 elements OR, the output of the element 13 And is the output of the error signal, the outputs of the switch 6 are connected to the second inputs of the corrector 8, the outputs of the block 7 switch a second input connected to the unit 9 correctors, the outputs of the corrector 8 and the block 9 are connected to the inputs of corrector unit 14 of AND gates, whose outputs are data outputs 21 of the device.

The memory node 1, in this case, is a static semiconductor operational memory device and is designed to store code sets: _K = x ₁ x ₂ x ₃ , z ₁ z ₂ z ₃ , a ₁ a ₂ a ₃ , c ₁ c ₂ c ₃ , e ₁ e ₂ e ₃ f ₁ f ₂ f ₃ , g ₁ g ₂ g ₃ , h ₁ h ₂ h ₃ r ₁ r ₂ r ₃ r ₄ r ₅ r ₆ obtained by encoding the original twenty-four bit binary sets.

The input coding unit 2 is intended for generating the values of the control bits r ₁ , r ₂ , r ₃ , r ₄ , r ₅ , r ₆ by adding mod2 information symbols in accordance with the rule:

r ₁ = x ₁ ⊕z ₁ ⊕a ₁ ⊕с ₁ ⊕e ₁ ⊕f ₁ ⊕g ₁ ⊕h ₁ ; r ₂ = x ₂ ⊕z ₂ ⊕a ₂ ⊕с ₂ ⊕e ₂ ⊕f ₂ ⊕g ₂ ⊕h ₂ ; r ₃ = x ₃ ⊕z ₃ ⊕a ₃ ⊕с ₃ ⊕e ₃ ⊕f ₃ ⊕g ₃ ⊕h ₃ ; r ₄ = x ₁ ⊕z ₃ ⊕a ₂ ⊕с ₂ ⊕c ₃ ⊕e ₁ ⊕e ₃ ⊕f ₁ ⊕f ₂ ⊕g ₁ ⊕g ₂ ⊕g ₃ ; r ₅ = x ₂ ⊕z ₁ ⊕a ₃ ⊕с ₁ ⊕c ₃ ⊕e ₁ ⊕e ₂ ⊕f ₂ ⊕f ₃ ⊕g ₁ ⊕g ₂ ⊕g ₃ ; r ₆ = x ₃ ⊕z ₂ ⊕a ₁ ⊕с ₁ ⊕c ₂ ⊕e ₂ ⊕e ₃ ⊕f ₁ ⊕f ₃ ⊕g ₁ ⊕g ₂ ⊕g ₃ .

The output coding unit 3 is intended for generating the values of the test check bits r _1P , r _2P , r _3P , r _4P , r _5P , r _6P , by adding mod2 information symbols received when reading information from the memory node 1 in accordance with the rule:

r _1P = x _1P ⊕z _1P ⊕a _1P ⊕s _1P ⊕e _1P ⊕f _1P ⊕g _1P ⊕h _1P ; r _2P = x _2P ⊕z _2P ⊕a _2P ⊕s _2P ⊕e _2P ⊕f _2P ⊕g _2P ⊕h _2P ; r _3P = x _3P ⊕z _3P ⊕a _3P ⊕s _3P ⊕e _3P ⊕f _3P ⊕g _3P ⊕h _3P ; r _4P = x _1P ⊕z _3P ⊕a _2P ⊕c _2P ⊕c _3P ⊕e _1P ⊕e _3P ⊕f _1P ⊕f _2P ⊕g _1P ⊕g _2P ⊕g _3P ; r _5P = x _2P ⊕z _1P ⊕a _3P ⊕c _1P ⊕c _3P ⊕e _1P ⊕e _2P ⊕f _2P ⊕f _3P ⊕g _1P ⊕g _2P ⊕g _3P ; r _6P = x _3P ⊕z _2P ⊕a _1P ⊕c _1P ⊕c _2P ⊕e _2P ⊕e _3P ⊕f _1P ⊕f _3P ⊕g _1P ⊕g _2P ⊕g _3P ,

Block 4 of the calculation of the error syndrome is designed to detect errors in the code set when reading information from the memory node 1 by adding mod2 values of the control bits r ₁ , r ₂ , r ₃ , r ₄ , r ₅ and r ₆ read from the second outputs of the memory node 1 , respectively, with the values of the control bits r _1P , r _2P , r _3P , r _5P , and r _6P generated at the outputs of the output coding unit 3.

The result of bitwise addition:

λ ₁ = r ₁ ⊕r _1P ;

λ ₂ = r ₂ ⊕r _2P ;

λ ₃ = r ₃ ⊕r _3P ;

λ ₄ = r ₄ ⊕r _4P ;

λ ₅ = r ₅ ⊕r _5P ;

λ ₆ = r ₆ ⊕r _6P .

A zero result of the sum indicates the absence of an error, and its presence otherwise.

The outputs λ ₁ , λ ₂ λ ₃ of the error syndrome calculation unit 4 allow one to determine the error configuration (error vector λ ₁ λ ₂ λ ₃ containing unit values in those bits that correspond to the error bits in the information block), outputs λ ₄ , λ ₅ λ ₆ determine the block of information bits in which an error occurred.

The decoder 7 generates a single signal value at one of its outputs in accordance with the table:

Table. one Syndrome values for code (30.6) correcting single errors. No. p / p Error-free block infor - and 000 The value of the first part of the control bits Values of checks of the second part of the control bits Incorrect information block X Z A C E F G H one one hundred one hundred one hundred 010 001 011 110 101 111 000 2 010 010 010 001 one hundred 101 011 110 111 000 3 001 001 001 one hundred 010 110 101 011 111 000

If the value of the error syndrome does not correspond to the values presented in the table, then an uncorrectable error has occurred (the signals at the decoder output have zero values).

In this case, the presence of a non-correctable error is indicated by the presence of a single signal value at the output of the first block of 10 OR elements and the absence of a single signal value at the output of the second OR element 11.

Corrector 8 (block 9 of correctors) are intended to correct a correctable error by adding mod2 of the same bits of the information block having an error with the value of the error vector.

The device operates as follows. Before starting the operation of the device, a single signal is input to the input 15 of the "zero state", which puts the device into a zero state.

When recording information in the memory node 1, single signals are supplied to the synchronization input 20, recording input 16, address inputs 18 and information inputs 19.

The input information block 2 generates the values of the control bits according to the rule:

r ₁ = x ₁ ⊕z ₁ ⊕a ₁ ⊕с ₁ ⊕e ₁ ⊕f ₁ ⊕g ₁ ⊕h ₁ ; r ₂ = x ₂ ⊕z ₂ ⊕a ₂ ⊕с ₂ ⊕e ₂ ⊕f ₂ ⊕g ₂ ⊕h ₂ ; r ₃ = x ₃ ⊕z ₃ ⊕a ₃ ⊕с ₃ ⊕e ₃ ⊕f ₃ ⊕g ₃ ⊕h ₃ ; r ₄ = x ₁ ⊕z ₃ ⊕a ₂ ⊕с ₂ ⊕c ₃ ⊕e ₁ ⊕e ₃ ⊕f ₁ ⊕f ₂ ⊕g ₁ ⊕g ₂ ⊕g ₃ ; r ₅ = x ₂ ⊕z ₁ ⊕a ₃ ⊕с ₁ ⊕c ₃ ⊕e ₁ ⊕e ₂ ⊕f ₂ ⊕f ₃ ⊕g ₁ ⊕g ₂ ⊕g ₃ ; r ₆ = x ₃ ⊕z ₂ ⊕a ₁ ⊕с ₁ ⊕c ₂ ⊕e ₂ ⊕e ₃ ⊕f ₁ ⊕f ₃ ⊕g ₁ ⊕g ₂ ⊕g ₃ .

Example. Let's say you need to encode a binary set:

Then the first part and the second part of the control bits formed relative to the received code set are respectively equal to:

r ₁ = 1, r ₂ = 0, r ₃ = 1, r ₄ = 1, r ₅ = 1, r ₆ = 1.

If there is no error, the value of the code set recorded in the memory node 1 is equal to the read value (transmitted to the code set):

In this case, at the output of the error syndrome calculation unit 4, we have zero signal values.

Suppose that a single error has occurred in the first bit of the third block of information (A = 0 ^* 01), then the output coding unit 3 will generate, relative to the received code set, the values of the control bits:

r _1P = 0, r _2P = 0, r _3P = 1.

r _3P = 0⊕0⊕0⊕0⊕0⊕1⊕1⊕0⊕1⊕1⊕1⊕0 = 1;

r _4P = 0⊕1⊕1⊕1⊕0⊕1⊕1⊕1⊕1⊕1⊕1⊕0 = 1;

r _6P = 1⊕1⊕1⊕0⊕0⊕1⊕1⊕0⊕1⊕1⊕1⊕0 = 0;

In block 4, the calculations of the error syndrome are added, the transmitted control bits with the control bits formed relative to the received code set, as a result, we obtain the error syndrome:

In this case, the first part of the syndrome has an erroneous discharge of an information block, the second part of the syndrome indicates an erroneous block A (see Table 1).

At the output of the decoder 7, a single signal value appears, which opens the AND elements of the switch block 7, while the error vector values are fed to the inputs of the corrector block 9 where it is added mod2 to the values of the bits of the third information block:

As a result, we have the correct value of the information.

Let there be a single error in the first bit of the first block of information, a single error in the second bit of the fourth block of information and a triple error in the fifth block of information.

In this case, the values of the control bits generated by the output coding unit 3 relative to the received binary set are:

r _1P = 0, r _2P = 1, r _3P = 0,

r _3P = 0, r _4P = 1, r _6P = 1.

The value of the error syndrome obtained by block 4 of the calculation of the error syndrome is equal to: .

In this case, at the output of the first block of 10 OR elements, a single signal value appears, at all outputs of the decoder 7 there is a zero signal value, therefore, at the output of the second block 11 of OR elements, we also have a zero signal value, and at the output of the inverter 12 a single value signal, which opens the element 12 And the output of which is removed the signal "error".

Thus, in the proposed information storage device, single errors are corrected in a separate information unit and error bytes are detected, with the exception of errors that are transformed into correctable.

INFORMATION SOURCES

1. Scherbakov N.S. The reliability of digital devices. M: Mechanical Engineering, 1989, p. 82, fig. 39., 224 p.

2. Scherbakov N.S. The reliability of digital devices. M: Mechanical Engineering, 1989, p. 122, fig. 45., 224 p.

application

1. Introduction and statement of the problem

In many cases, codes for detecting and correcting errors are used with the detection and correction of error bytes (in this case, the error byte means errors whose multiplicity does not exceed the number of bits b of the information block).

These codes include codes [1]:

- correcting single errors and detecting single bytes of errors;

- codes correcting single errors, detecting double independent errors and detecting single bytes of errors;

- codes correcting single error bytes;

- codes correcting single and detecting double bytes of errors.

Reed-Solomon codes are widely used, having cyclic properties and having the highest detecting and correcting ability.

Reed-Solomon code (PC) is a block code (w, N) that allows the detection and correction of errors in bytes. The input word for it is a block of w bytes, the output is a code word of N bytes, consisting of w source and N-w test bytes. It is guaranteed that during decoding, t = (N-w) / 2 bytes will be detected and corrected in the codeword, regardless of their location inside the codeword. PC encoder is implemented based on a shift register with 2t byte memory elements and feedbacks. The process of encoding and decoding is reduced to the operations of addition and multiplication modulo.

The use of these codes is associated with large time costs, which is a significant drawback when using them for systems operating in real time, therefore there is a need to develop a simpler linear procedure for constructing corrective codes that solve this problem.

2. Development of a linear corrective code with the correction of single errors in an information byte and the detection of arbitrary errors in information bytes

A method for constructing a correcting code that corrects single and detecting double bytes of errors is proposed that implements a linear procedure for constructing a corrective code with syndromic decoding.

To obtain a code distance that allows correcting single bytes and detecting double bytes of errors, we use 2b control bits (the optimal number of control bits for Reed-Solomon codes that solve this problem), which implement mod2 addition of the same bits of blocks (bytes) of information.

As a result, we will teach a code set:

The value of the control bits , , allow to form the value of the error syndrome in this case, the first part of the control bits determines the error vector (erroneous bits in the information block), and the value of the second part of the control bits is intended to determine the number of an erroneous block (byte) of information.

In this case, the number of bytes of information is determined by the formula:

w = 2 ^b

In this regard, there is a need to form a set of checks (develop a rule for encoding information), which allows to determine an information block containing an error.

For this purpose, for each block of information, we choose our own set of checks that detect an error using the dimension coding matrix

b × b.

For the first block of information, the encoding matrix has the form:

In this case, for the first block of information, the values of the control bits are respectively equal ; ; .

For the second and third information blocks, the encoding matrix has the form, respectively:

It is not difficult to notice that the next coding matrix is obtained by cyclically replacing the rows of the coding matrix.

As a result, we get b source coding matrices containing one unit in their rows.

For information blocks, starting with b + 1 block, coding matrices include various combinations of two units in the information block:

The values of the control bits are formed by adding mod2 column elements corresponding to unit values.

So, for example, if the first column no longer contains units, then the value of the first control bit is: .

Each successive coding matrix for information blocks, starting with b + 2 blocks by information is obtained by cyclic replacement of the rows of the matrix by analogy with a matrix containing one unit in each row.

Similarly, coding matrices are constructed that contain in their rows various combinations of three units, etc.

Finally, we have a coding matrix, each element of which contains a unit. We also construct an additional coding matrix, each element of which contains zeros.

The values of the control bits obtained in this way allow one to construct a code that corrects single errors and to detect errors of higher multiplicity.

To correct errors in a block of information of multiplicity b, we modify the resulting coding matrices (except for matrices containing all ones and all zeros), for which we divide the resulting set of coding matrices in pairs and, in each pair, change (invert) one element of the same name.

Using the modified coding matrices, we obtain checks that determine the values of the control bits for each block of information by adding mod2 elements corresponding to unit values in the columns of the obtained matrices.

Combining modulo mod2 modulo control checks of the same name for all blocks of information, we obtain the values of the control bits for the second part of the control bits of the code set.

Thus, the code set is transmitted in the form:

The result of mod2 addition of the transmitted values of the control bits , and control bits , formed relative to the received information bits will give the value of the error syndrome, which includes two parts:

The value of the error syndrome S ^f determines the error vector (erroneous bits in the information block), and the value of the error syndrome S ^g determines the number of the error information block (byte).

The decoding strategy is based on the following provisions:

1.S ^f = 0; S ^g = 0. There are no errors. 2. S ^f = 0; S ^g ≠ 0. An error has occurred in the check bits. 3. S ^f ≠ 0; S ^g ≠ 0 (S ^g = 0). An error occurred in the information bytes (in one byte - correctable, in two - detectable).

Thus, the developed code, with the optimal number of control bits 2b, has the properties characteristic of Reed-Solomon codes and allows:

- use the linear coding procedure;

- increase the speed of encoding and decoding information.

Example: Suppose we have twenty-four bit binary sets that we break into blocks of information of three bits in each block:

Y = x ₁ x ₂ x ₃ , z ₁ z ₂ z ₃ , a ₁ a ₂ a ₃ , c ₁ c ₂ c ₃ , e ₁ e ₂ e ₃ , f ₁ f ₂ f ₃ ; g ₁ g ₂ g ₃ , h ₁ h ₂ h ₃ .

We construct the source coding matrix for each block of information:

Adding, according to mod2, the elements of the matrix columns corresponding to unit values, we obtain checks that allow us to obtain the values of the control bits for the corresponding blocks of information.

As a result, the values of the second part of the control bits are formed by checks:

The obtained values of the control bits, together with the values of the first part of the control bits formed by adding the same information bits of information blocks, allow one to have a correction code that corrects single errors in any information block and to detect errors of higher multiplicity.

As a result, we have a code (30.6) correcting single errors and detecting errors of higher multiplicity.

Table. one Syndrome values for code (30.6) correcting single errors. No. p / p Error-free infor-000 block The value of the first part of the control bits Values of checks of the second part of the control bits Incorrect information block X Z A C E F G H one one hundred one hundred one hundred 010 001 011 110 101 111 000 2 010 010 010 001 one hundred 101 011 110 111 000 3 001 001 001 one hundred 010 110 101 011 111 000 four 110 110 110 011 101 110 101 011 000 000 5 101 101 101 110 011 101 011 110 000 000 6 011 011 011 101 110 011 110 101 000 000 111 111 111 111 111 000 000 000 111 000

Analysis of the presented table shows that in the event of a single error, the values of the second part of the syndromes for information blocks differ from each other, which allows you to adjust these errors.

If errors of a greater multiplicity occur or in several information blocks, the values of the syndromes are indistinguishable, in this case an error is detected.

At the same time, the selected syndromes indicate the presence of an uncorrectable error, the non-distinguished syndromes indicate an information block containing the corresponding single correctable error.

Example. Let's say you need to encode a binary set:

Substituting, into the obtained expressions, the formation of the second part of the control bits, the values of the corresponding bits of the binary set will receive:

Adding, the same information bits of information blocks, we get the first part of the control bits 101.

Thus, an error-free code set is transmitted in the form:

Let there be a single error in the first bit of the third block of information (A), then the first part and second part of the control bits formed relative to the received code set are equal, respectively:

Adding the transmitted control bits to the control bits formed relative to the received code set, we obtain the error syndrome:

In this case, the first part of the syndrome has an erroneous discharge of an information block, the second part of the syndrome indicates an erroneous block (see Table 1).

Thus, the proposed method for constructing corrective codes that detect and correct errors in information bytes allows us to exclude the division and multiplication procedure necessary when using cyclic codes and replace it with a linear one, increase the speed of information encoding and decoding, and provide the required level of error detection and correction.

Literature:

1. Scherbakov N.C. The reliability of digital devices. M: Mechanical Engineering, 1989, p. 122, fig. 45., 224 p.

Claims (1)

A device for storing and transmitting data with the correction of single errors in the byte of information and the detection of arbitrary errors in the bytes of information, containing a memory node, an input coding unit, an output coding unit, an error syndrome calculation unit, a decoder, a switch, a switch unit, a corrector, an error corrector, the fact that it further comprises a first block of OR elements, a second block of OR elements, an inverter, an AND element, a block of AND elements, an input for setting the device to zero, a write input, a read input I, address inputs, 24-bit information inputs, synchronization input, information outputs, error signal output, zero input, write input, read input, address inputs, connected to the first, second, third and fourth inputs of the node, respectively memory, the synchronization input is connected to the fifth input of the memory node and to the first input of the block of elements AND, information inputs are connected to the sixth inputs of the memory node and to the inputs of the input coding block, which generates the values of the control bits r ₁ , r ₂ , r ₃ , r ₄ , r ₅ , r ₆ by adding modulo 2 information symbols x ₁ x ₂ x ₃ , z ₁ z ₂ z ₃ , a ₁ a ₂ a ₃ , c ₁ c ₂ c ₃ , e ₁ e ₂ e ₃ , f ₁ f ₂ f ₃ , g ₁ g ₂ g ₃ , h ₁ h ₂ h _3. , received at the inputs of the input coding unit, in accordance with the rule: r ₁ = x ₁ ⊕z ₁ ⊕a ₁ ⊕с ₁ ⊕e ₁ ⊕f ₁ ⊕g ₁ ⊕h ₁ ; r ₂ = x ₂ ⊕z ₂ ⊕a ₂ ⊕с ₂ ⊕e ₂ ⊕f ₂ ⊕g ₂ ⊕h ₂ ; r ₃ = x ₃ ⊕z ₃ ⊕a ₃ ⊕с ₃ ⊕e ₃ ⊕f ₃ ⊕g ₃ ⊕h ₃ ; r ₄ = x ₁ ⊕z ₃ ⊕a ₂ ⊕с ₂ ⊕c ₃ ⊕e ₁ ⊕e ₃ ⊕f ₁ ⊕f ₂ ⊕g ₁ ⊕g ₂ ⊕g ₃ ; r ₅ = x ₂ ⊕z ₁ ⊕a ₃ ⊕с ₁ ⊕c ₃ ⊕e ₁ ⊕e ₂ ⊕f ₂ ⊕f ₃ ⊕g ₁ ⊕g ₂ ⊕g ₃ ; r ₆ = x ₃ ⊕z ₂ ⊕a ₁ ⊕с ₁ ⊕c ₂ ⊕e ₂ ⊕e ₃ ⊕f ₁ ⊕f ₃ ⊕g ₁ ⊕g ₂ ⊕g ₃ , which are fed to the seventh inputs of the memory node, information outputs of the node the memory is connected respectively to the first inputs of the corrector, the corrector block and the inputs of the output coding block, which generates the values of the test check bits r _1P , r _2P , r _3P , r _4P , r _5P , r _6P by modulo 2 adding information symbols x _1P x _2P x _3P , z _1P z _2P z _3P , a _1P a _2P a _3P , c _1P c _2P c _3P , e _1P e _2P e _3P , f _1P f _2P f _3P , g _1P g _2P g _3P , h _1P h _2P h _3P supplied to the inputs of the input coding block from the information outputs memory node, in accordance with the rule: r _1P = x _1P ⊕z _1P ⊕a _1P ⊕s _1P ⊕e _1P ⊕f _1P ⊕g _1P ⊕h _1P ; r _2P = x _2P ⊕z _2P ⊕a _2P ⊕s _2P ⊕e _2P ⊕f _2P ⊕g _2P ⊕h _2P ; r _3P = x _3P ⊕z _3P ⊕a _3P ⊕s _3P ⊕e _3P ⊕f _3P ⊕g _3P ⊕h _3P ; r _4P = x _1P ⊕z _3P ⊕a _2P ⊕c _2P ⊕c _3P ⊕e _1P ⊕e _3P ⊕f _1P ⊕f _2P ⊕g _1P ⊕g _2P ⊕g _3P ; r _5P = x _2P ⊕z _1P ⊕a _3P ⊕c _1P ⊕c _3P ⊕e _1P ⊕e _2P ⊕f _2P ⊕f _3P ⊕g _1P ⊕g _2P ⊕g _3P ; r _6P = x _3P ⊕z _2P ⊕a _1P ⊕c _1P ⊕c _2P ⊕e _2P ⊕e _3P ⊕f _1P ⊕f _3P ⊕g _1P ⊕g _2P ⊕g _3P ;, the outputs of the output coding unit are connected to the first inputs of the calculation unit an error syndrome to the second inputs of which the outputs of the control bits of the memory node are connected, the first outputs of the error syndrome calculation unit are connected to the first inputs of the decoder, to the first inputs of the switch, to the inputs of the first block of OR elements and to the first inputs of the switch block, the second outputs of the error syndrome calculation unit are connected to the second inputs of the decoder and to the second inputs of the first bl eye of the OR elements, the outputs of the decoder are connected to the inputs of the second block of OR elements, while the first output of the decoder is connected to the second input of the switch unit, the outputs of the second block of OR elements through the inverter are connected to the first input of the AND element, the second the input of which is connected to the output of the first block of OR elements, the output of the AND element is the output of the “error” signal, the outputs of the switch are connected to the second inputs of the corrector, the outputs of the block of switches are connected to the second inputs the corrector block, the corrector outputs and the corrector block are connected to the second inputs of the AND block, the outputs of which are information outputs of the device.