CN108664362B

CN108664362B - Memory mirror image processing method, memory controller and user equipment

Info

Publication number: CN108664362B
Application number: CN201710210810.3A
Authority: CN
Inventors: 王焕东
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2017-03-31
Filing date: 2017-03-31
Publication date: 2021-06-15
Anticipated expiration: 2037-03-31
Also published as: CN108664362A

Abstract

The invention provides a memory mirror image processing method, a memory controller and user equipment. The memory mirror image processing method comprises the following steps: the method comprises the steps that a memory controller obtains a data writing instruction, wherein the data writing instruction comprises first data to be written; the memory controller determines at least two target write memory modules positioned on the same channel in the memory and controls an input signal of a chip selection end of a chip included in each target write memory module to be an effective level signal; and the memory controller writes the first data into the chips respectively included by the target write memory modules through the determined channels where the target write memory modules are located. The memory mirror image processing method, the memory controller and the user equipment provided by the invention ensure the utilization rate of bandwidth on the basis of realizing the data mirror image memory.

Description

Memory mirror image processing method, memory controller and user equipment

Technical Field

The present invention relates to memory technologies, and in particular, to a method for processing a memory mirror image, a memory controller, and a user equipment.

Background

The internal memory system is an indispensable part of modern computer systems, and currently, mainly used internal memory systems are DDR, DDR2, DDR3, DDR4 and the like. The internal memory system is controlled by a memory controller, which may be integrated within the processor or may exist as a physically separate structure from the processor.

The memory mirror image is to put the main data and the redundant data corresponding to the main data into different memory modules respectively, the memory module for storing the main data can be called as a main memory, and the memory module for storing the redundant data can be called as a mirror image memory. The device adopted by the method for realizing the mirror image storage of the data in the prior art is as follows: the memory controller is provided with a first memory channel interface and a second memory channel interface, the memory controller is connected with the first channel through the first channel interface, and the memory controller is connected with the second channel through the second channel interface; the method for realizing the mirror image storage of the data comprises the following steps: after determining a first storage assembly (a memory module) corresponding to the main data and a second storage assembly corresponding to the redundant data, the memory controller writes the main data into the first storage assembly through a first channel and writes the redundant data into the second storage assembly through a second channel.

However, the method must be used in a multi-channel memory device system, and two channels are simultaneously adopted to realize the mirror image storage of data, so that the actual utilization rate of the double bandwidth of the original two channels is only half, and the bandwidth utilization rate is low.

Disclosure of Invention

The invention provides a memory mirror image processing method, a memory controller and user equipment, which aim to solve the technical problem of low bandwidth utilization rate caused by the memory mirror image processing method in the prior art.

The invention provides a processing method of a memory mirror image, which is applied to a memory controller, wherein a memory controlled by the memory controller comprises at least two memory modules, and each memory module comprises at least one chip; the method comprises the following steps:

the memory controller acquires a data writing instruction, wherein the data writing instruction comprises first data to be written;

the memory controller determines at least two target write memory modules positioned on the same channel in the memory and controls an input signal of a chip selection end of a chip included in each target write memory module to be an effective level signal; the at least two target write memory modules are connected to the same data bus and the same address bus, and the channel is determined by the data bus and the address bus;

the memory controller writes the first data into chips included in the target write memory modules through the channels; in each target write memory module, the first data written in one target write memory module is main data, and the first data written in the rest target write memory modules are mirror image data.

According to the method, the data writing instruction further includes a writing linear address corresponding to the first data; the memory controller determines at least two target write memory modules located on the same channel in the memory, and the method comprises the following steps:

the memory controller determines a first target write memory module according to the write linear address;

the memory controller determines at least one second target write memory module which is positioned on the same channel as the first target write memory module from the rest memory modules of the memory;

and the memory controller determines at least two target write memory modules according to the first target write memory module and the second target write memory module.

In the method, the writing, by the memory controller, the first data into the chip included in each target write memory module includes:

the memory controller determines a write physical address of the first data according to the write linear address;

the memory controller obtains first check data corresponding to the first data according to the first data;

and the memory controller writes the first data and the first check data into chips respectively included in the target write memory modules through the channel according to the write physical address.

The method as described above, further comprising:

the memory controller receives a data reading instruction sent by data reading equipment, wherein the data reading instruction comprises a reading linear address;

the memory controller determines a read physical address of second data to be read and each target read memory module corresponding to the second data according to the read linear address, and if the read linear address is the same as the write linear address, the second data corresponds to the first data;

the memory controller reads second data and second check data from the first target read memory module according to the read physical address; the first target memory reading module is any one target memory reading module;

the memory controller obtains third check data according to the second data read from the first target read memory module;

and the memory controller judges whether the second data read from the first target read memory module is correct or not according to the second check data and the third check data, and if so, sends the second data read from the first target read memory module to the data reading equipment.

The method as described above, further comprising:

if the second data read from the first target read memory module is wrong, the memory controller judges whether the second data read from the first target read memory module can be corrected or not according to the second check data and the third check data, if so, the second data read from the first target read memory module is corrected, and the corrected second data read from the first target read memory module is sent to the data reading equipment;

alternatively, the first and second electrodes may be,

if the second data read from the first target read memory module is wrong, the memory controller reads the second data and the second check data from the second target read memory module; the second target read memory module is any one of the target read memory modules, and is different from the first target read memory module;

the memory controller obtains fourth check data according to the second data read from the second target read memory module;

and the memory controller judges whether the second data read from the second target read memory module is correct or not according to the second check data and the fourth check data, and if so, sends the second data read from the second target read memory module to the data reading equipment.

The method as described above, further comprising:

the memory controller respectively reads second data from the first target read memory module and reads the second data from the second target read memory module according to the read physical address; the first target read memory module and the second target read memory module are any two target read memory modules;

and the memory controller judges whether the second data read twice are the same, and if so, the memory controller sends the second data to the data reading equipment.

The invention also provides a memory controller, wherein the memory controlled by the memory controller comprises at least two memory modules, and each memory module comprises at least one chip; the memory controller includes:

the data writing method comprises the steps that a receiving module is used for obtaining a data writing instruction, wherein the data writing instruction comprises first data to be written;

the target memory module determining module is used for determining at least two target write memory modules positioned on the same channel in the memory and controlling an input signal of a chip selection end of a chip included in each target write memory module to be an effective level signal; the at least two target write memory modules are connected to the same data bus and the same address bus, and the channel is determined by the data bus and the address bus;

the data writing module is used for writing the first data into chips included in the target write memory modules through the channels; in each target write memory module, the first data written in one target write memory module is main data, and the first data written in the rest target write memory modules are mirror image data.

The memory controller, the target memory module determination module is specifically configured to,

determining a first target write memory module according to the write linear address;

determining at least one second target write memory module which is positioned on the same channel with the first target write memory module in the rest memory modules of the memory;

and determining at least two target write memory modules according to the first target write memory module and the second target write memory module.

As described above, the data writing module is specifically configured to:

determining a write physical address of the first data according to the write linear address;

obtaining first check data corresponding to the first data according to the first data;

and writing the first data and the first verification data into chips respectively included in each target write memory module through the channel according to the write physical address.

The memory controller further comprises a data reading module, a check data generating module and a judging module;

the receiving module is further configured to receive a data reading instruction sent by a data reading device, where the data reading instruction includes a read linear address;

the target memory module determining module is further configured to determine, according to the read linear address, a read physical address of second data to be read and each target read memory module corresponding to the second data, where if the read linear address is the same as the write linear address, the second data corresponds to the first data;

the data reading module is used for reading second data and second check data from the first target read memory module according to the read physical address; the first target memory reading module is any one target memory reading module;

the check data generation module is used for obtaining third check data according to the second data read from the first target read memory module;

the judging module is used for judging whether the second data read from the first target read memory module is correct or not according to the second check data and the third check data, and if yes, sending the second data read from the first target read memory module to the data reading equipment;

if the second data read from the first target read memory module is incorrect, the judging module is further configured to judge whether the second data read from the first target read memory module can be corrected according to the second check data and the third check data, correct the second data read from the first target read memory module if the second data read from the first target read memory module is incorrect, and send the corrected second data read from the first target read memory module to the data reading device;

alternatively, the first and second electrodes may be,

if the second data read from the first target read memory module is wrong, the data reading module is further used for reading the second data and the second check data from the second target read memory module; the second target read memory module is any one of the target read memory modules, and is different from the first target read memory module;

the check data generation module is further used for obtaining fourth check data according to the second data read from the second target read memory module;

the judging module is further configured to judge whether the second data read from the second target read memory module is correct according to the second check data and the fourth check data, and if yes, send the second data read from the second target read memory module to the data reading device.

The memory controller further comprises a data reading module and a judging module;

the target memory module determining module is used for determining a reading physical address of second data to be read and each target read memory module corresponding to the second data according to the reading linear address, and if the reading linear address is the same as the writing linear address, the second data corresponds to the first data;

the data reading module is used for respectively reading second data from the first target read memory module and reading the second data from the second target read memory module according to the read physical address; the first target read memory module and the second target read memory module are any two target read memory modules;

the judging module is used for judging whether the second data read twice are the same or not, and if yes, sending the second data to data reading equipment.

The present invention also provides a user equipment comprising the memory controller as described above.

The memory mirror image processing method comprises the following steps: the method comprises the steps that a memory controller obtains a data writing instruction, wherein the data writing instruction comprises first data to be written; the memory controller determines at least two target write memory modules positioned on the same channel in the memory and controls an input signal of a chip selection end of a chip included in each target write memory module to be an effective level signal; the at least two target write memory modules are connected to the same data bus and the same address bus, and the channel is determined by the data bus and the address bus; the memory controller writes first data into chips respectively included in each target write memory module through a channel where the determined target write memory module is located; in each target write memory module, the first data written in one target write memory module is main data, and the first data written in the rest target write memory modules are mirror image data. The processing method of the memory mirror image ensures the utilization rate of the bandwidth on the basis of realizing the memory of the data mirror image.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a first schematic architecture diagram of a memory system according to the present invention;

fig. 2 is a second schematic diagram of the architecture of the memory system provided in the present invention;

fig. 3 is a flowchart of a first embodiment of a method for processing a memory mirror image according to the present invention;

FIG. 4 is a diagram illustrating a memory module according to the present invention;

fig. 5 is a flowchart of a second embodiment of a memory mirror processing method provided in the present invention;

fig. 6 is a flowchart of a third embodiment of a method for processing a memory mirror image according to the present invention;

fig. 7 is a flowchart of a fourth embodiment of a method for processing a memory mirror image according to the present invention;

FIG. 8 is a schematic structural diagram of a memory controller according to a first embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a second embodiment of a memory controller according to the present invention;

fig. 10 is a schematic structural diagram of a user equipment provided in the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a schematic diagram of a memory system according to the first embodiment of the present invention, and referring to fig. 1, the memory system includes at least one memory controller 11, a channel 12 is disposed outside each memory controller, at least two memory modules 13 are disposed on each channel 12, the memory controller 11 is connected to the memory modules 13 through the channels 12, and a plurality of memory modules located on the same channel may also be referred to as a plurality of memory modules connected to the same address bus and the same data bus. The memory module 0-1 refers to the 1 st memory module on the 0 th channel, the memory module 1-1 refers to the 1 st memory module on the 1 st channel, and the meanings of the labels of the rest memory modules are the same.

The flow of the processing method of the memory mirror image of the memory system shown in fig. 1 is as follows: a processor or other equipment sends a data writing instruction to any memory controller 11 in a memory system, the memory controller 11 determines at least two memory modules 13 after receiving the data writing instruction, and the determined at least two memory modules 13 are necessarily located in the same channel; and then, the data to be written included in the data writing instruction is written into the at least two determined memory modules 13 through the channel, so that the mirror image storage of the data to be written is realized. For example, data 1 in fig. 1 is data to be written, the memory modules 0-0 and 0-1 are located on the same channel, and data 1 is written into the memory modules 0-0 and 0-1 at the same time.

Fig. 2 is a schematic diagram of a second architecture of the memory system provided by the present invention, and referring to fig. 2, the memory system includes a memory controller 21, a plurality of channels 22 are provided outside the memory controller, each channel 22 is provided with at least two memory modules 23, the memory controller 21 is connected with the memory modules 23 provided on its respective channel through each channel 22, and a plurality of memory modules located on the same channel may also be said to be connected on the same address bus and the same data bus.

The flow of the processing method of the memory mirror image of the memory system shown in fig. 2 is as follows: the processor or other equipment sends a data writing instruction to the memory controller 21, and the memory controller 21 determines at least two memory modules located on the same channel after receiving the data writing instruction; and then, simultaneously writing the data to be written in the data writing instruction into the determined at least two memory modules through the channel, thereby realizing the mirror image storage of the data to be written. For example, data 1 in fig. 2 is data to be written, the memory modules 0-0 and 0-1 are located on the same channel, and data 1 is written into the memory modules 0-0 and 0-1 at the same time.

The system architecture applied in the present embodiment is described above with reference to fig. 1 and fig. 2 as an example. It will be understood by those skilled in the art that the applicable system architecture of the present embodiment is not limited to the above two architectures, and a memory system having at least two memory modules on the same channel can be applied to the present embodiment.

A detailed description is given below to a specific implementation process of the memory mirror processing method by using a specific embodiment.

Fig. 3 is a flowchart of a first embodiment of a method for processing a memory mirror image according to the present invention, as shown in fig. 3, the method of the present embodiment is applied to a memory controller, and the method of the present embodiment may include:

step S101, a memory controller obtains a data writing instruction, wherein the data writing instruction comprises first data to be written;

step S102, a memory controller determines at least two target write memory modules located on the same channel in a memory and controls input signals of chip selection ends of chips included in each target write memory module to be effective level signals; the at least two target write memory modules are connected to the same data bus and the same address bus, and the channel is determined by the data bus and the address bus;

step S103, the memory controller writes the first data into the chips of each target write memory module through the channel where the target write memory module is located; in each target write memory module, the first data written in one target write memory module is main data, and the first data written in the rest target write memory modules are mirror image data.

Specifically, the memory controlled by the memory controller in this embodiment includes at least two memory modules, and each memory module includes at least one chip.

In this embodiment, a bit width of the processor data bus is 64 bits, chips constituting the memory module are 16K × 8 bits, and each memory module includes 8 chips with 16K × 8 bits. Those skilled in the art can understand that the bit width of the processor data bus may also be 128 bits or 32 bits, which is implemented in a similar manner and will not be described herein again.

Fig. 4 is a schematic diagram of a memory module according to the present invention. As shown in fig. 4, one memory module 41 includes 8 chips 42. The number of memory modules included in the memory is determined by the memory units of the memory, for example, a 128K × 64-bit memory requires 64 chips (128/16) × (64/8), that is, the memory includes 8 memory modules.

In the actual processing process of the mirror image memory, a memory controller acquires a data writing instruction, wherein the data writing instruction comprises first data to be written; the data writing instruction may be sent by a controller of the processor or other external device. It is understood by those skilled in the art that in the memory system shown in fig. 1, the memory controller in the embodiment is any memory controller in the memory system.

After the memory controller receives the data write-in command, the memory controller determines at least two target write-in memory modules located on the same channel in the memory and controls input signals of chip selection ends of chips included in the target write-in memory modules to be effective level signals. The at least two target write memory modules located on the same channel may also be described as at least two target write memory modules connected to the same data bus and connected to the same address bus, where the channel is determined by the data bus and the address bus, and the memory controller performs information transmission with the memory through the channel.

The memory controller determines that at least two target write memory modules in the memory have the following two possible implementation manners.

One possible implementation is: the memory controller acquires a write linear address corresponding to the first data, wherein the write linear address is included in the data write command; the memory controller determines a first target write memory module according to the write linear address; the memory controller determines a second target write memory module located on the same channel as the first target write memory module in the remaining memory modules of the memory, or the second target write memory module is a memory module on the channel where the first target write memory module is located; the memory controller determines at least two target write memory modules according to the first target write memory module and the second target write memory module. The second target write memory module and the first target write memory module are located in the same channel, which can also be described as follows: each second target write memory module and the first target write memory module are connected to the same data bus and the same address bus.

For this implementation, in the memory system shown in fig. 1, because the memory controller that receives a certain data write instruction is any memory controller, a channel is provided outside each memory controller, and at least two memory modules determined by the memory controller are certainly located in the same channel; in the memory system shown in fig. 2, after the memory controller determines the first target write memory module according to the write linear address, the determined at least one second target write memory module needs to be located in the same channel as the first target write memory module, for example, the first target write memory module is determined to be the memory module 1-1, and the at least one second target write memory module may be any one or more of the memory modules 1-2, 1-3, and 1-4.

The method for determining that the first target writes to the memory module by the memory controller according to the write linear address may refer to the method in the prior art, and is not described in detail in this embodiment.

Another possible implementation is: the memory controller acquires a write linear address corresponding to the first data, wherein the write linear address is included in the data write command; and the memory controller determines at least two target write memory modules on the same channel according to the write linear address.

For this implementation, in the memory system shown in fig. 2, the method for the memory controller to determine at least two target write memory modules according to the write linear address may be: the memory controller selects

channel

0 or 1 linearly according to the first, if channel 0 is selected, when two target write memory modules are determined, two numbers are arbitrarily selected in the write linear address, for example, two numbers are selected to be 0 and 2, then memory module 0-0 and memory module 0-2 are the two target write memory modules, and in this case, of course, the arbitrarily selected two numbers must be between 0 and 3. In the memory system shown in fig. 1, if the channel corresponding to the memory controller receiving a certain data write command is 0, when determining that two target write memory modules are written, two numbers can be arbitrarily selected from the write linear address, for example, two numbers are selected to be 0 and 2, then the memory module 0-0 and the memory module 0-2 are the two target write memory modules, and in this case, the two arbitrarily selected numbers also need to be between 0 and 3.

After the memory controller determines each target write memory module, the memory controller controls the input signal of the chip selection end of the chip included in each target write memory module to be an effective level signal, and when the input signal of the chip selection end of the chip is the effective level signal, the chip is indicated to be the target chip, and data can be written into the target chip. Specifically, the periphery of the chip includes a chip selection terminal, an address line pin, a data line pin, and the like, and in general, when a signal input from the chip selection terminal is a low level signal, it indicates that an input signal from the chip selection terminal is an active level signal, and the chip is a target chip. The chips included in a memory module share the same chip selection signal, that is, the signals input to the chip selection terminals of the chips included in a memory module are the same, which is determined by the way of writing data into the memory. The data writing mode into the memory is as follows: when 64-bit data (corresponding to the bit width of the data bus) transmitted in one transmission cycle of the processor is written into the memory, if there are 8 chips of 16K × 8 bits in the memory module, 8-bit data is written into each chip of the memory module.

As will be understood by those skilled in the art, if the input signals of the chip select terminals of the chips included in the plurality of memory modules located on the same channel are all active level signals, the data to be written will be written into the plurality of memory modules simultaneously.

Then, the memory controller writes the first data into the chip included in each target write memory module through the channel where the target write memory module is located, and the method specifically includes: the memory controller determines a write physical address of the first data according to the write linear address; and the memory controller writes the first data into the chips respectively included by the target write memory modules through the channels where the target write memory modules are located according to the write physical addresses. In each target write memory module, the first data written in one target write memory module is main data, and the first data written in the rest target write memory modules are mirror image data.

Specifically, the memory controller obtains a write physical address according to a mapping relationship between the write linear address and the write physical address, where the write physical address includes a row address and a column address, for example, if the write physical address determined by the memory controller according to the write linear address is a 2 nd row and a 3 rd column, the first data is written into the storage unit corresponding to the 2 nd row and the 3 rd column of the chip included in each target write memory module.

For example, when 64 bits of data transmitted in one transmission cycle of the processor are written into the memory, if the memory module has 8 chips with 16K × 8 bits, 8 bits of data are written into each chip of the memory module, and each chip is composed of 8 banks, and 1 bit of data is written into the memory cell corresponding to the 2 nd row and the 3 rd column of each bank.

Because each target write memory module is connected to the same data bus and address bus and is written in simultaneously, the utilization rate of the bandwidth is not reduced, and the utilization rate of the bandwidth is ensured on the basis of realizing the data mirror memory.

It should be understood by those skilled in the art that the first data referred to in the present embodiment may be data transmitted within one transmission cycle of the processor. For example, if the data that can be transmitted by the processor in one transmission cycle is 64 bits, and the data to be written is larger than 64 bits, for example, 128 bits, the data to be written is stored in each target write memory module twice; firstly, 64 bits of data (first data) are sent to a memory controller through a processor, after the memory controller determines at least two target write memory modules and physical addresses, the 64 bits of data are written into storage units of a 2 nd row and a 3 rd column (taking the example) of a chip included in each target write memory module, and then the remaining 64 bits of data (first data) are written into storage units of a 2 nd row and a 4 th column of the chip included in each target write memory module after passing through the processor and the memory controller.

The memory mirror image processing method of the embodiment includes: the method comprises the steps that a memory controller obtains a data writing instruction, wherein the data writing instruction comprises first data to be written; the memory controller determines at least two target write memory modules positioned on the same channel in the memory and controls an input signal of a chip selection end of a chip included in each target write memory module to be an effective level signal; the at least two target write memory modules are connected to the same data bus and the same address bus, and the channel is determined by the data bus and the address bus; the memory controller writes first data into chips respectively included in each target write memory module through a channel where the determined target write memory module is located; in each target write memory module, the first data written in one target write memory module is main data, and the first data written in the rest target write memory modules are mirror image data. The memory mirror image processing method of the embodiment ensures the utilization rate of the bandwidth on the basis of realizing the data mirror image memory.

In order to ensure that the data read by the subsequent data reading process is correct data, the present embodiment is further improved based on the previous embodiment. Fig. 5 is a flowchart of a second embodiment of a method for processing a memory mirror image, as shown in fig. 5, the method of this embodiment may include:

step S201, a memory controller obtains a data writing instruction, wherein the data writing instruction comprises first data to be written;

step S202, a memory controller determines at least two target write memory modules located on the same channel in a memory and controls input signals of chip selection ends of chips included in each target write memory module to be effective level signals; the at least two target write memory modules are connected to the same data bus and the same address bus, and the channel is determined by the data bus and the address bus;

step S203, the memory controller determines a write physical address of the first data according to the write linear address, and obtains first check data corresponding to the first data according to the first data;

step S204, the memory controller writes the first data and the first check data into chips respectively included in each target write memory module through a channel where the target write memory module is located according to the write physical address; in each target write memory module, the first data written in one target write memory module is main data, and the first data written in the rest target write memory modules are mirror image data.

Specifically, steps S201 to S202 are the same as those in the previous embodiment, and are not described again in this embodiment. The meaning of the first data in this embodiment is the same as that in the previous embodiment.

In step S203, the method for the memory controller to determine the write physical address of the first data according to the write linear address is the same as that in the previous embodiment, and the description is omitted in this embodiment. For the memory controller, according to the first data, obtaining first check data corresponding to the first data, an Error Checking and Correcting (ECC) check method or a parity check method may be adopted, and other methods may also be adopted, which is not limited in this embodiment. It will be appreciated by those skilled in the art that for each first datum a corresponding first check datum is generated. Such as the example in the previous embodiment: the data that can be transmitted in one transmission cycle of the processor is 64 bits, and if the data to be written is larger than 64 bits, for example, 128 bits, the data to be written is stored in the target write memory module twice, that is, the data to be written has two first data. The first 64-bit data written first will generate a first check data, and the second 64-bit data written later will also generate a first check data.

In step S204, the memory controller writes the first data and the first verification data into the chip included in each target write memory module through the channel where the target write memory module is located according to the write physical address.

Next, a process in which the memory controller writes the first data and the first check data into the chips included in each target write memory module through the channel in which the target write memory module is located according to the write physical address by taking a storage process of the first check data obtained by the ECC check method as an example.

The first check data obtained by the ECC check method is check data with a word length of 8 bits, and an 8-bit chip needs to be added to the memory module in the memory, for example: if the bit width of the processor data bus is 64 bits, the chips forming the memory modules are 16K × 8 bits, and each memory module needs to include 8 chips of 16K × 8 bits, at this time, in order to store the check bits, one chip needs to be added, that is, each memory module includes 9 chips of 16K × 8 bits, where one chip is used to store the check data with a word length of 8 bits.

If the memory controller determines that the first data is stored in the storage unit with the write physical address of the 2 nd row and the 3 rd column in the chip corresponding to each target write memory module, the check data is also stored in the storage unit with the write physical address of the 2 nd row and the 3 rd column in the chip corresponding to each target write memory module.

The memory mirror image processing method of the embodiment can ensure that the data read in the subsequent data reading process is correct data by writing the verification data into the memory.

Fig. 6 is a flowchart of a third embodiment of a processing method for memory mirroring provided by the present invention, as shown in fig. 6, the method of this embodiment may be directed to a reading process of data written by using the data writing method of the embodiment corresponding to fig. 3 or fig. 5, and the method of this embodiment may include:

step S301, a memory controller receives a data reading instruction sent by a data reading device, wherein the data reading instruction comprises a reading linear address;

step S302, the memory controller determines a read physical address of second data to be read and each target read memory module corresponding to the second data according to the read linear address, and if the read linear address is the same as the write linear address, the second data corresponds to the first data;

step S303, the memory controller reads second data from the first target read memory module and reads the second data from the second target read memory module respectively according to the read physical address; the first target read memory module and the second target read memory module are any two target read memory modules;

step S304, the memory controller determines whether the second data read twice are the same, and if yes, sends the second data to the data reading device.

In the data reading process of this embodiment, if the check data is not written in the data writing process, the data stored in the plurality of memory modules needs to be read, and whether the data read from the plurality of memory modules is the same or not is compared to determine whether the read data is correct data or whether the read data is data to be read.

Specifically, the memory controller receives a data reading instruction sent by the data reading device, where the data reading instruction includes a read linear address. The data reading device may be a processor or other external device, and the data reading instruction includes a linear address of the data to be read, which is used to indicate a specific location where the data to be read is stored.

After receiving the data reading instruction, the memory controller determines a reading physical address of second data to be read and each target reading memory module corresponding to the second data according to a reading linear address included in the data reading instruction. And if the written second data to be read does not change in the memory, the second data to be read stored in each target read memory module is the same.

It should be understood by those skilled in the art that the method for determining each target read memory module corresponding to the second data according to the read linear address is the same as the method for determining each target write memory module corresponding to the first data according to the write linear address in the embodiment corresponding to fig. 3, and the method for determining the read physical address of the second data according to the read linear address is the same as the method for determining the write physical address of the first data according to the write linear address in the embodiment corresponding to fig. 3. That is, for the same memory system, the rule followed in data reading corresponds to the rule followed in data writing. Therefore, if the read linear address and the write linear address are the same, the second data corresponds to the first data.

After determining each target memory reading module for storing the second data and the reading physical address, the memory controller respectively reads the second data from the first target memory reading module and reads the second data from the second target memory reading module according to the reading physical address; the first target read memory module and the second target read memory module are any two target read memory modules.

For example, if the read physical address is column 3, column 4, and the first target read memory module and the second target read memory module are the memory modules 0-2 and 0-3 in fig. 1, data is read from the memory cells in column 3, column 4 of the chip included in the memory modules 0-2 and 0-3, respectively.

After the memory controller reads data from the first target read memory module and the second target read memory module respectively, whether the second data read twice are the same or not is judged, and if yes, the second data are sent to the data reading equipment. The method for determining whether the second data read twice is the same may be a method in the prior art, and this embodiment is not limited.

If the second data read from the first target read memory module is the same as the second data read from the second target read memory module, which indicates that the second data read from the first target read memory module or the second data read from the second target read memory module is the data to be read, and the originally written data is not lost or tampered, the second data read from the first target read memory module or the second data read from the second target read memory module may be sent to the data reading device.

If the second data read from the first target read memory module is different from the second data read from the second target read memory module, it is described that the second data read from the first target read memory module and/or the second data read from the second target read memory module are not data which are wanted to be read, and the originally written data are lost or tampered; if there are only two target read memory modules, after determining that the second data read twice are different, it needs to send a data error report to the data reading device, and if the number of the target read memory modules is greater than two, the following method may be used for operation.

The number of the target read memory modules is 3, and the 3 target read memory modules are respectively as follows: the first target read memory module, the second target read memory module, and the third target read memory module are used to describe subsequent operations in the case where the second data read from the first target read memory module is different from the second data read from the second target read memory module.

Reading second data from a storage unit at a read physical address of a chip included in the third target read memory module, and sequentially judging whether the second data read from the third target read memory module is the same as the second data read from the second target read memory module and whether the second data read from the third target read memory module is the same as the second data read from the first target read memory module; if the second data read from the third target read memory module is the same as the second data read from the second target read memory module, it is indicated that the second data read from the third target read memory module or the second data read from the second target read memory module is the data to be read, and the second data read from the third target read memory module or the second data read from the second target read memory module is sent to the data reading device; if the second data read from the third target read memory module is the same as the second data read from the first target read memory module, the second data read from the third target read memory module or the second data read from the first target read memory module is the data to be read, and the second data read from the third target read memory module or the second data read from the first target read memory module is sent to the data reading equipment; and if the second data read from the third target read memory module is not the same as the second data read from the second target read memory module and the second data read from the third target read memory module is not the same as the second data read from the first target read memory module, sending a data error report to the data reading equipment.

It can be understood by those skilled in the art that if the data is 64 bits written at a time, the data reading process is also 64 bits read at a time, that is, the second data is data with a word length of 64 bits, and the second data read at each time is read according to the same reading method until the data with the required word length is read.

In the memory mirror image processing method of this embodiment, whether the determined data is correct is determined by reading data from the plurality of memory modules into which the same data is written, so that it is ensured that the read data is correct.

Fig. 7 is a flowchart of a fourth embodiment of a processing method of a memory mirror image provided by the present invention, as shown in fig. 7, the method of this embodiment is a reading process of data written by using the data writing method of the embodiment corresponding to fig. 5, and the method of this embodiment may include:

step S401, a memory controller receives a data reading instruction sent by a data reading device, wherein the data reading instruction comprises a reading linear address;

step S402, the memory controller determines a read physical address of second data to be read and each target read memory module corresponding to the second data according to the read linear address, and if the read linear address is the same as the write linear address, the second data read from the first target read memory module corresponds to the first data;

step S403, the memory controller reads the second data and the second check data from the first target read memory module according to the read physical address; the first target read memory module is any one target read memory module;

step S404, the memory controller obtains third check data according to the second data read from the first target read memory module;

step S405, the memory controller determines whether the second data read from the first target read memory module is correct according to the second check data and the third check data, and if yes, sends the second data read from the first target read memory module to the data reading device.

In the data reading process of this embodiment, since the check data is written in the data writing process, only the data stored in one memory module can be read at a time, and whether the data read from the memory module is correct or not is determined through the check data, or whether the read data is the data to be read is determined. Of course, the data reading process of the previous embodiment may also be employed.

It should be understood by those skilled in the art that the method for determining each target read memory module corresponding to the second data according to the read linear address is the same as the method for determining each target write memory module corresponding to the first data according to the write linear address in the embodiment corresponding to fig. 5, and the method for determining the read physical address of the second data according to the read linear address is the same as the method for determining the write physical address of the first data according to the write linear address in the embodiment corresponding to fig. 5, that is, for the same memory system, the rule followed when reading the data corresponds to the rule followed when writing the data. In addition, the read linear address and the write linear address may be the same, and if the read linear address and the write linear address are the same, the second data corresponds to the first data.

After determining each target memory reading module for storing the second data and the reading physical address, the memory controller reads the second data and the second check data from the first target memory reading module according to the reading physical address; the first target read memory module is any one target read memory module. And the second check code is generated according to the data written into the reading physical address in the first target reading memory module in the data writing process.

For example, if the read physical address is column 3, column 4, and the first target read memory module is the memory module 0-2 in fig. 1, the data is read from the memory cells in column 3, column 4 of the chip included in the memory module 0-2.

And then, the memory controller regenerates the check code, called as a third check code, according to the second data read from the first target read memory module, wherein the generation method of the third check code is the same as that of the second check code.

And judging whether the second data read from the first target read memory module is correct or not according to the second check code and the third check code, and if so, sending the second data to the data reading equipment.

Specifically, if the generation method of the check code is the ECC check method, the second check code and the third check code are subjected to an exclusive-or operation, and whether the second data read from the first target read memory module is correct is determined according to a result of the exclusive-or operation. If the generation method of the check code is the parity bit check method, whether the second check code and the third check code are the same or not is directly judged, and if the second check code and the third check code are the same, the second data read from the first target read memory module is determined to be correct.

If the second data read from the first target read memory module is judged to be incorrect according to the second check code and the third check code, and the generating method of the check code is an ECC check method, since the ECC check method can correct one bit, the following operations can be performed: judging whether the second data read from the first target read memory module can be corrected or not according to the second check data and the third check data, if so, correcting the second data read from the first target read memory module, and sending the corrected second data read from the first target read memory module to the data reading equipment; if not, reading second data and second check data from the second target read memory module; the second target read memory module is any one target read memory module, and is different from the first target read memory module; obtaining fourth verification data according to the second data read from the second target read memory module; judging whether the second data read out from the second target read memory module is correct or not according to the second check data and the fourth check data, if so, sending the second data read out from the second target read memory module to data reading equipment; if the second data read from the second target read memory module is not correct, the same operation is repeated until the second data read from the Nth target read memory module is correct or correctable or each target read memory module is read.

If the second data read from the first target read memory module is judged to be incorrect according to the second check code and the third check code, and the generating method of the check code is not an ECC check method, directly performing the following operations: reading second data and second check data from the second target read memory module; the second target read memory module is any one target read memory module, and is different from the first target read memory module; obtaining fourth verification data according to the second data read from the second target read memory module; judging whether the second data read from the second target read memory module is correct or not according to the second check data and the fourth check data, if so, sending the second data read from the second target read memory module to data reading equipment; and if the second data read from the second target read memory module is incorrect, repeating the same operation until the second data read from the Nth target read memory module is correct or all target read memory modules are read.

Fig. 8 is a schematic structural diagram of a memory controller according to a first embodiment of the present invention, and as shown in fig. 8, the apparatus of the present embodiment may include: the data writing method comprises a receiving module 81, a target memory module determining module 82 and a data writing module 83, wherein the receiving module 81 is used for acquiring a data writing instruction, and the data writing instruction comprises first data to be written; the target memory module determining module 82 is configured to determine at least two target write memory modules located in the same channel in a memory, and control an input signal of a chip selection end of a chip included in each target write memory module to be an active level signal; the at least two target write memory modules are connected to the same data bus and the same address bus, and the channel is determined by the data bus and the address bus; the data writing module 83 is configured to write the first data into each chip included in each target write memory module through the channel where the target write memory module is located; in each target write memory module, the first data written in one target write memory module is main data, and the first data written in the rest target write memory modules are mirror image data.

The target memory module determining module 82 is specifically configured to obtain a write linear address corresponding to the first data; determining a first target write memory module according to the write linear address; determining at least one second target write memory module which is positioned on the same channel with the first target write memory module in the rest memory modules of the memory; and determining at least two target write memory modules according to the first target write memory module and the second target write memory module.

The data writing module 83 is specifically configured to determine a writing physical address of the first data according to the writing linear address; obtaining first check data corresponding to the first data according to the first data; and writing the first data and the first verification data into the chips respectively included in the target write memory modules through the channel where the target write memory modules are located according to the write physical address.

The apparatus of this embodiment may be configured to implement the technical solutions of the above method embodiments, and the implementation principles and technical effects are similar, which are not described herein again.

Fig. 9 is a schematic structural diagram of a second embodiment of a memory controller according to the present invention, and as shown in fig. 9, the apparatus of this embodiment may further include, on the basis of the embodiment shown in fig. 8: a data reading module 84, a verification data generating module 85 and a data judging module 86.

The receiving module 81 is further configured to receive a data reading instruction sent by the reading device, where the data reading instruction includes a read linear address.

The target memory module determining module 82 is further configured to determine, according to the read linear address, a read physical address of the second data to be read and each target read memory module corresponding to the second data.

If the data is written in, the check data is written in, and the data reading module 84 is configured to read the second data and the second check data from the first target read memory module according to the read physical address; the first target read memory module is any one target read memory module; the verification data generating module 85 is configured to obtain third verification data according to the second data read from the first target read memory module; the data determining module 86 is configured to determine whether the second data is correct according to the second check data and the third check data, and if so, send the second data read from the first target read memory module to the data reading device.

If the second data read from the first target read memory module is incorrect, the data determining module 86 is further configured to determine whether the second data read from the first target read memory module can be corrected according to the second check data and the third check data, correct the second data read from the first target read memory module if the second data read from the first target read memory module is incorrect, and send the corrected second data read from the first target read memory module to the data reading device.

If the second data read from the first target read memory module is incorrect and the second data read from the first target read memory module cannot be corrected, the data reading module 84 is further configured to read the second data and the second check data from the second target read memory module; the second target read memory module is any one target read memory module, and is different from the first target read memory module; the verification data generating module 85 is further configured to obtain fourth verification data according to the second data read from the second target read memory module; the data determining module 86 is further configured to determine, by the memory controller, whether the second data read from the second target read memory module is correct according to the second check data and the fourth check data, and if so, send the second data read from the second target read memory module to the data reading device.

If the verification data is not written in the data writing process, the data reading module 84 is further configured to read the second data from the first target read memory module and read the second data from the second target read memory module according to the read physical address; the first target read memory module and the second target read memory module are any two target read memory modules; the data determining module 86 is further configured to determine whether the second data read twice are the same, and if yes, send the second data to the data reading device.

Fig. 10 is a schematic structural diagram of a user equipment provided in the present invention, and as shown in fig. 10, the user equipment of this embodiment includes: the memory controller 91, wherein the memory controller 91 may adopt the structure of the corresponding embodiment in fig. 8 or fig. 9, the memory controller 91 may be integrated on a control chip 93 inside the user equipment 92, and the control chip 93 may be a processor.

The user equipment includes, but is not limited to, a mobile phone, a computer, a tablet, and the like.

Correspondingly, the technical solutions of the above method embodiments may be implemented, and the implementation principles and technical effects are similar, which are not described herein again.

Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. The processing method of the memory mirror image is characterized by being applied to a memory controller, wherein a memory controlled by the memory controller comprises at least two memory modules, and each memory module comprises at least one chip; the method comprises the following steps:

the memory controller acquires a data writing instruction, wherein the data writing instruction comprises first data to be written and a writing linear address corresponding to the first data;

the memory controller determines at least one second target write memory module which is positioned on the same channel as the first target write memory module from the rest memory modules of the memory, wherein the second target write memory module is any write memory module which is positioned on the same channel as the first target write memory module;

the memory controller determines at least two target write memory modules according to the first target write memory module and the second target write memory module, and controls input signals of chip selection ends of chips included in each target write memory module to be effective level signals; the at least two target write memory modules are connected to the same data bus and the same address bus, and the channel is determined by the data bus and the address bus;

2. The method as claimed in claim 1, wherein the writing of the first data into the chip included in each of the target write memory modules by the memory controller comprises:

3. The method of claim 2, further comprising:

4. The method of claim 3, further comprising:

alternatively, the first and second electrodes may be,

5. The method according to claim 1 or 2, characterized in that the method further comprises:

6. A memory controller is characterized in that a memory controlled by the memory controller comprises at least two memory modules, and each memory module comprises at least one chip; the memory controller includes:

the data writing method comprises the steps that a receiving module is used for obtaining a data writing instruction, wherein the data writing instruction comprises first data to be written and a writing linear address corresponding to the first data;

the data writing module is used for writing the first data into chips included in the target write memory modules through the channels; in each target write memory module, first data written in one target write memory module is main data, and the remaining first data written in each target write memory module is mirror image data;

the target memory module determining module is specifically configured to determine a first target write memory module according to the write linear address;

determining at least one second target write memory module which is positioned on the same channel as the first target write memory module in the rest memory modules of the memory, wherein the second target write memory module is any write memory module which is positioned on the same channel as the first target write memory module;

7. The memory controller of claim 6, wherein the data write module is specifically configured to:

8. The memory controller of claim 7, further comprising a data reading module, a check data generating module, and a determining module;

the verification data generation module is used for obtaining third verification data according to the second data read from the first target read memory module;

if the second data read from the first target read memory module is incorrect, the judging module is further configured to judge whether the second data read from the first target read memory module can be corrected according to the second check data and the third check data, correct the second data read from the first target read memory module if the second data read from the first target read memory module is incorrect, and send the corrected second data read from the first target read memory module to the data reading device; or if the second data read from the first target read memory module is wrong, the data reading module is further used for reading the second data and the second check data from the second target read memory module; the second target read memory module is any one of the target read memory modules, and is different from the first target read memory module;

9. The memory controller according to claim 6 or 7, wherein the memory controller further comprises a data reading module and a judging module;

the data reading module is further used for respectively reading second data from the first target read memory module and reading the second data from the second target read memory module according to the read physical address; the first target read memory module and the second target read memory module are any two target read memory modules;

10. A user equipment comprising the memory controller of any one of claims 6-9.