JP3158711B2 - Data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data transfer of parallel data in a device such as a digital transmission device.

[0002] In parallel data transfer between packages in a digital transmission device, a data top signal, a synchronization clock, and a data enable signal are also transmitted at the same time as parallel data, and whether the data is valid or invalid is determined. Although the identification method is used, a more efficient data transfer method is required.

[0003]

2. Description of the Related Art A conventional example will be described with reference to FIGS. FIG. 12 is a diagram illustrating an example of a conventional data transfer method, and FIG. 13 is a diagram illustrating an example of a conventional transfer data.

Conventionally, as a general method of data transfer, as shown in FIG. 12, for example, in addition to 8-bit parallel data, a data top signal (frame signal), a synchronization clock, and the data are effective. In order to identify whether the frame is invalid or invalid, a data enable signal is transmitted separately. If the bit of the data enable signal is “H” as shown in the example of FIG. 13, the data of the frame is valid. Yes, and if "L", the data of the frame is invalid.

[0005]

However, this method is an easy method for constructing a system. However, in order to identify validity / invalidity of data, it is necessary to determine the validity / invalidity of the data for the first few clocks of the data. It is only necessary to look at that bit for a while, and for that frame there is no need to refer to that bit thereafter, resulting in meaningless data.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problem, and provides various control signals in an area where a data enable signal is wasted so that data transfer can be checked and system monitoring can be performed. The aim is to provide a method.

[0007]

FIG. 1 is a block diagram showing the principle of a data transfer method according to the present invention. In the figure, 10 is a transmitting side package, 11 is a selector control signal generating unit, 12 is a selector (SEL), 14 is a control information signal generating unit, 20 is a receiving side package, 21 is a DMUX control signal generating unit, 22 is A separation unit (DMUX), 23 is a latch circuit, and 24 is a control information signal processing unit.

According to the present invention, in order to transfer data from the transmission side package 10 to the reception side package 20 in the digital transmission apparatus, a data top signal, a synchronization clock, and a data enable signal are also transmitted in addition to parallel data. In the data transfer method for performing data transfer, a selector control signal generator 11 for generating a selector control signal for controlling a selector, a control information signal generator 14 for generating a control information signal, and And a SEL 12 for selecting either a data enable signal or a control information signal under the control of the selector control signal generation unit 11.

The receiving side package 20 contains a DM.
DMUX for generating control signal for controlling UX22
A control signal generation unit 21, a DMUX 22 for receiving a data enable signal including a control information signal, and separating the data enable signal and the control information signal into a data enable signal and a control information signal; A latch circuit 23 for latching and a control information signal processing unit 24 for processing the control information signal sent separately by the DMUX 22 are provided.

In the transmitting side package 10, instead of the data enable signal of the third and subsequent bits of the data top signal, the SEL 12 is controlled by the selector control signal generation unit 11 and the control information signal generation unit Transmitting the control information signal generated in step 14;
Then, the DMUX control signal generation unit 21 generates the DM
The purpose can be achieved by separating the data enable signal including the control information signal received by the DMUX 22 into the data enable signal and the control information signal by the UX control signal.

Here, in the transmission side package 10,
The selector control signal generator 11, the counter 15,
A parallel / serial conversion circuit 18 and the SEL 12 are provided. Also, in the receiving side package 20, the D
An MUX control signal generation unit 21, the DMUX 22, the latch circuit 23, a counter 25, a serial / parallel conversion circuit 28, and a comparator 31 are provided.

The sequential number generated by the counter 15 is transmitted and received as a control information signal to be transmitted instead of the data enable signal of the third bit and subsequent bits of the data top signal.

As a second method, a parity generation unit 1 is used instead of the counter 15 in the transmission side package 10.
6 and a parity generator 26 is provided in place of the counter 25 in the receiving side package 20.

Then, instead of the sequential number transmitted and received in place of the data enable signal for the third and subsequent bits of the data top signal, the parity generation unit 1
The parity signal generated in step 6 may be transmitted and received.

As a third method, instead of the counter 15 in the transmitting side package 10, a CRC calculating unit 17 is used.
And a CRC operation unit 27 is provided in place of the counter 25 in the receiving side package 20.

Then, instead of the sequential number transmitted and received in place of the data enable signal for the third and subsequent bits of the data top signal, the CRC calculation unit 17
May be transmitted and received.

As a fourth method, the selector control signal generator 11 and the S
In addition to the EL 12, the counter 15, and the parallel / serial conversion circuit 18, the parity generation unit 16 and the parallel / serial conversion circuit 19 are provided.

In the receiving side package 20, the DMUX control signal generator 21, the DMUX 22, the latch circuit 23, the counter 25, the serial /
In addition to the parallel conversion circuit 28 and the comparator 31, the parity generation unit 26 and the serial / parallel conversion circuit 29
And a comparator 32.

Then, in addition to the sequential number transmitted and received in place of the data enable signal for the third and subsequent bits of the data top signal, the parity generation unit 1
The parity signal generated in step 6 may be transmitted and received together.

As a fifth method, in the fourth method,
The parity generation unit 1 in the transmission side package 10
6, the CRC operation unit 17 is provided. In place of the parity generation unit 26 in the receiving side package 20, the CRC operation unit 27 is provided.

Then, instead of the parity signal generated by the parity generation unit 16 and transmitted in place of the data enable signal of the third and subsequent bits of the data top signal, and the sequential number generated by the counter 41,
The parity signal generated by the CRC operation unit 17 and the sequential number generated by the counter 15 may be exchanged.

[0022]

According to the present invention, a selector control signal generator for generating a selector control signal for controlling a selector, a control information signal generator for generating a control information signal, a selector control signal generator, An SEL 12 for selecting either a data enable signal or a control information signal under the control of the unit 11 is provided.

In the receiving side package 20, a DMUX control signal generating section 21 for generating a control signal for separating a data enable signal and a control information signal, and a data enable signal including the control information signal are received. , DMUX2 for separating into a data enable signal and a control information signal
A latch circuit 23 for latching the data enable signal separated and sent by the DMUX 22 with a data latch pulse from the DMUX control signal generator 21;
A control information signal processing unit 24 is provided for processing the control information signal sent separately in the UX 22.

In this way, in the transmitting side package 10, the SEL 12 is controlled by the selector control signal generator 11 instead of the data enable signal of the third bit and subsequent bits of the data top signal. 1
4 can be transmitted. Further, in the receiving side package 20, the DMUX control signal generated by the DMUX control signal
Since the data enable signal including the control information signal received in step 2 can be separated into a data enable signal and a control information signal, this control information signal can be effectively used for monitoring transfer data and the like.

Here, a selector control signal generation unit 11, a counter 15, a parallel / serial conversion circuit 18, and a SEL 12 are provided in the transmission side package 10. In the receiving package 20, a DMUX control signal generation unit 21, a DMUX 22, a latch circuit 23, a counter 25, a serial / parallel conversion circuit 28, and a comparator 31 are provided.

By doing so, the sequential number generated by the counter 15 can be transmitted and received as a control information signal instead of the data enable signal for the third and subsequent bits of the data top signal.

As a second method, a parity generator 16 is used instead of the counter 15 in the transmitting package 10.
Is provided. Also, the counter 2 in the receiving side package 20
5, a parity generation unit 26 is provided.

By doing so, the parity signal generated by the parity generation unit 16 can be transmitted and received instead of the sequential number transmitted and received instead of the data enable signal of the third bit and subsequent bits of the data top signal. it can.

As a third method, a CRC operation unit 17 is provided instead of the counter 15 in the transmission side package 10. Also, the counter 25 in the receiving side package 20
, A CRC operation unit 27 is provided.

By doing so, the CRC signal generated by the CRC operation section 17 can be transmitted and received instead of the sequential number transmitted and received instead of the data enable signal of the third bit and subsequent bits of the data top signal. it can.

Further, as a fourth method, a selector control signal generation unit 11 and a SEL1
2. In addition to the counter 15, the parallel / serial conversion circuit 18, a parity generation unit 15 and another parallel / serial conversion circuit 19 are provided. And the receiving side package 2
0, the DMUX control signal generator 21, the DMUX 22,
In addition to the latch circuit 23, the counter 25, the serial / parallel conversion circuit 28, and the comparator 31, a parity generation unit 84
And another serial / parallel conversion circuit 29 and another comparator 32.

By doing so, the parity signal generated by the parity generation section 16 is transmitted and received in addition to the sequential number transmitted and received instead of the data enable signal of the third and subsequent bits of the data top signal. can do.

As a fifth method, in the fourth method, the parity generation unit 16 in the transmitting side package 10 is used.
, A CRC calculation unit 17 is provided. Also, instead of the parity generation unit 26 in the receiving side package 20, a CRC
An operation unit 27 is provided.

By doing so, instead of the parity signal generated by the parity generation unit 15 and the sequential number generated by the counter 41 instead of the data enable signal of the third and subsequent bits of the data top signal, The parity signal generated by the CRC calculation unit 17 and the sequential number generated by the counter 15 can be exchanged.

[0035]

Next, an embodiment will be described with reference to FIGS. FIG. 2 shows a first embodiment of the data transfer method according to the present invention, FIG. 3 shows a second embodiment of the data transfer method according to the present invention, and FIG. 4 shows a third embodiment of the data transfer method according to the present invention. FIG. 5 shows a fourth embodiment of the data transfer method according to the present invention, and FIG. 6 shows a fifth embodiment of the data transfer method according to the present invention.

FIG. 7 shows the transfer data of the first embodiment, FIG. 8 shows the transfer data of the second embodiment, FIG. 9 shows the transfer data of the third embodiment, and FIG. FIG. 11 shows transfer data according to the fifth embodiment.

In the figure, the same reference numerals as those in FIG.
15 and 25 are counters, 18 and 19 are parallel / serial conversion circuits, 16 and 26 are parity generation units, and 17 and 27.
Is a CRC operation unit, 28 and 29 are serial / parallel conversion circuits, and 31 and 32 are comparators.

First, with respect to the first embodiment shown in FIG.
This will be described with reference to FIG. In the first embodiment, a sequential number (SN) is transmitted as a control information signal to be transmitted instead of an invalid data enable signal.

In the transmitting side package 10, the counter 15
After converting the counter output, which is a parallel signal, into a serial signal, the number is sequentially increased one by one with a delay of one frame and put on the data enable signal line.

The receiving side package 20 has a counter 25 therein. The counter output is converted into a serial number (SN), which is a transmitted serial signal, into a parallel signal and then compared.

By comparing, it can be checked whether or not the data has been correctly transferred and whether or not the data has been lost halfway. Next, in the second embodiment shown in FIGS. 3 and 8, a parity signal is transmitted as a control information signal instead of an invalid data enable signal.

The transmitting side package 10 has a parity generating unit 16 which generates a parity for each bit from the parallel data to be transferred, converts the parity signal which is a parallel signal into a serial signal, and delays by one frame. ,
As shown in FIG. 8, the parity signal for each bit of the parallel data is sequentially put on the data enable signal line.

The receiving side package 20 also has a parity generation unit 27 therein, and generates a parity for each bit from the transferred parallel data. On the other hand, the parity signal for each bit transmitted via the data enable signal line is converted into a parallel signal, and is compared with the parity generated by the parity generation unit 84.

By performing the comparison, it is possible to check whether the data has been correctly transferred or not. As described above, by enabling the transmission and reception of the parity signal, the parity check can be performed without using a separate line for the parity.

Next, in the third embodiment shown in FIGS. 4 and 9, a CRC bit is transmitted as a control information signal instead of an invalid data enable signal. The transmitting side package 10 has a CRC operation unit 17, performs a CRC operation on the parallel data to be transferred, converts the CRC bits that are parallel signals into serial signals,
With a frame delay, as shown in FIG. 9, it is put on the data enable signal line.

The receiving side package 20 also has a CRC inside.
Having an operation unit 27, the C of the transferred parallel data
Perform RC calculation. On the other hand, the CRC bits transmitted through the data enable signal line are converted into parallel signals, and are compared with the CRC bits generated by the CRC operation unit 27.

By performing the comparison, a CRC check can be performed to determine whether or not there is a data bit error.
As described above, by enabling the transmission and reception of the CRC bit, it is possible to perform the CRC check without using the separate CRC bit line.

Next, in the fourth embodiment shown in FIGS. 5 and 10, a sequential number and a parity signal are transmitted as control information signals instead of invalid data enable signals.

In the transmitting side package 10, the counter 15
After converting the counter output, which is a parallel signal, into a serial signal, the number is sequentially increased one by one with a delay of one frame and put on the data enable signal line.

The transmitting side package 10 also has a parity generation unit 16 for generating parity for each bit from the parallel data to be transferred, converting the parity signal which is a parallel signal into a serial signal, As shown in FIG. 10, the parity signal for each bit of the parallel data is sequentially put on the data enable signal line with the frame delay.

The receiving side package 20 has a counter 25 therein, and converts the counter output and the transmitted serial number (SN) into a parallel signal and then compares them.

The receiving side package 20 has a parity generation unit 26 therein, and generates a parity for each bit from the transferred parallel data. On the other hand, the parity signal for each bit transmitted via the data enable signal line is converted into a parallel signal, and is compared with the parity generated by the parity generation unit 26.

In this way, the sequential number (S
By comparing (N), it is possible to check whether or not data has been correctly transferred and whether or not data has been lost in the middle.

Also, by comparing the parity,
A parity check can be performed to determine whether data has been correctly transferred. As described above, by enabling the transmission and reception of the parity signal, the parity check can be performed without using a separate line for the parity.

Next, in the fifth embodiment shown in FIGS. 6 and 11, a sequential number and a parity signal are transmitted as a control information signal instead of an invalid data enable signal.

In the transmitting side package 10, the counter 15
After converting the counter output, which is a parallel signal, into a serial signal, the number is sequentially increased one by one with a delay of one frame and put on the data enable signal line.

The transmitting side package 10 has a CRC
The operation unit 17 also performs a CRC operation on the parallel data to be transferred, converts the CRC bits, which are parallel signals, into serial signals, and puts them on a data enable signal line with a one-frame delay as shown in FIG. .

The receiving side package 20 has a counter 25 therein, and converts the counter output and the transmitted serial number (SN), which is a serial signal, into a parallel signal and compares them.

Further, the receiving side package 20 has a CRC operation unit 27 therein, and performs a CRC operation of the transferred parallel data. On the other hand, the CRC bits sent via the data enable signal line are converted into parallel signals, and are then compared with the CRC bits generated by the CRC calculation unit 85.

In this way, the sequential number (S
By comparing (N), it is possible to check whether or not data has been correctly transferred and whether or not data has been lost in the middle.

Further, by comparing the CRC calculation results, it is possible to check whether there is a bit error in the data or not. As described above, by enabling the transmission and reception of the CRC bit, it is possible to perform the CRC check without using the separate CRC bit line.

[0062]

As described above, according to the present invention,
By transmitting various control information signals to the useless portions of the data enable signal instead, it is possible to check data to be transferred and monitor the system without using a separate line.

By providing a plurality of control information signals to be transmitted on useless portions of the data enable signal, it is possible to more efficiently check transfer data, monitor the system, and the like.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of a data transfer method according to the present invention.

FIG. 2 is a first embodiment of a data transfer method according to the present invention.

FIG. 3 is a second embodiment of the data transfer method according to the present invention.

FIG. 4 is a third embodiment of the data transfer method according to the present invention.

FIG. 5 is a fourth embodiment of the data transfer method according to the present invention.

FIG. 6 is a fifth embodiment of the data transfer method according to the present invention.

FIG. 7 is a diagram illustrating transfer data according to the first embodiment;

FIG. 8 is a diagram illustrating transfer data according to a second embodiment.

FIG. 9 is a diagram illustrating transfer data according to a third embodiment.

FIG. 10 is a diagram illustrating transfer data according to a fourth embodiment.

FIG. 11 is a diagram illustrating transfer data according to a fifth embodiment.

FIG. 12 is a diagram showing a conventional data transfer method.

FIG. 13 is a diagram showing conventional transfer data.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Transmission side package 11 Selector control signal generation part 12 SEL 14 Control information signal generation part 15, 25 Counter 16, 26 Parity generation part 17, 27 CRC calculation part 18, 19 Parallel / serial conversion circuit 20 Receiving side package 21 DMUX control signal Generation unit 22 DMUX 23 Latch circuit 28, 29 Serial / parallel conversion circuit 31, 32 Comparator

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-130066 (JP, A) JP-A-1-177154 (JP, A) JP-A-4-134553 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H04L 29/08 G06F 13/38 330

Claims (6)

(57) [Claims] 1. A data top signal, a synchronization clock, and a data enable signal in addition to parallel data for transferring data from a transmission side package (10) to a reception side package (20) in a digital transmission apparatus. In a data transfer method for simultaneously transmitting and transferring data, a selector control signal generation unit (11) for generating a selector control signal for controlling a selector and a control for generating a control information signal are provided in the transmission side package (10). An information signal generator (14) and a SEL (12) for selecting either a data enable signal or a control information signal under the control of the selector control signal generator (11); A DMUX control signal generator (21) for generating a control signal for controlling the DMUX (22), and a data including a control information signal. Receiving an enable signal, a DMUX for separating the data enable signal and the control information signal (22), the DMUX (22)
And a control information signal processing unit (24) for processing the control information signal separated and sent by the DMUX (22). In the transmitting side package (10), instead of the data enable signal of the third bit and subsequent bits of the data top signal, the S (S) is controlled by the selector control signal generation unit (11).
The EL (12) transmits the control information signal generated by the control information signal generator (14), and the receiving side package (20) uses the DMUX control signal generated by the DMUX control signal generator (21) to transmit the control information signal. A data transfer method comprising: separating the data enable signal including the control information signal received by the DMUX (22) into a data enable signal and the control information signal. 2. The transmission-side package (10) according to claim 1, wherein the selector control signal generator (11), a counter (15), a parallel / serial conversion circuit (18), and the SEL ( 12), wherein the DMUX control signal generator (21), the DMUX (22), the latch circuit (23), the counter (25), and the serial / parallel device are provided in the receiving package (20). A conversion circuit (28), a comparator (31), and a sequential number generated by the counter (15) as a control information signal to be transmitted instead of the data enable signal for the third and subsequent bits of the data top signal. A data transfer method characterized by exchanging data. 3. The counter (1) in the transmitting package (10) according to claim 2, wherein
A parity generation unit (16) is provided instead of 5), and the counter (2) in the reception side package (20) is provided.
A parity generation unit (26) is provided in place of 5), and is generated by the parity generation unit (16) in place of the sequential number transmitted and received in place of the data enable signal for the third and subsequent bits of the data top signal. A data transfer method for transmitting and receiving a parity signal. 4. The counter (1) according to claim 2, wherein the counter (1) in the transmitting package (10) is provided.
5) a CRC operation unit (17) is provided, and the counter (2) in the receiving side package (20) is provided.
A CRC calculation unit (27) is provided instead of 5), and is generated by the CRC calculation unit (17) instead of the sequential number transmitted and received instead of the data enable signal of the third bit and subsequent bits of the data top signal. CRC
A data transfer method comprising transmitting and receiving signals. 5. The transmission-side package (10) according to claim 2, wherein the selector control signal generator (11), the SEL (12), the counter (15), and the parallel / serial converter ( 1
8) In addition to the above, the parity generation unit (16) and another parallel / serial conversion circuit (19) are provided, and the DMUX control signal generation unit (21) is provided in the reception side package (20). In addition to the DMUX (22), the latch circuit (23), the counter (25), the serial / parallel conversion circuit (28), and the comparator (31), the parity generation unit (26) A parallel conversion circuit (29) and another comparator (32), wherein the parity generation unit is used instead of the sequential number transmitted and received in place of the data enable signal of the third and subsequent bits of the data top signal. A data transfer method, wherein the parity signal generated in (16) and the sequential number generated in the counter (15) are exchanged. 6. The reception package (20) according to claim 5, wherein the CRC calculation unit (17) is provided instead of the parity generation unit (16) in the transmission package (10). The CRC calculation unit (27) is provided in place of the parity generation unit (26), and the parity generation unit (1) that transmits the data enable signal of the third bit or more of the data top signal instead of the data enable signal is provided.
6) and the parity signal generated by the CRC operation unit (17) instead of the sequential number generated by the counter (41) and the counter (1).
A data transfer method characterized by transmitting and receiving the sequential number generated in 5).