JPH06104954A - Data transfer method - Google Patents

Abstract

PURPOSE:To check transfer data and to monitor the system or the like by using a useless area of a data enable signal in data transfer. CONSTITUTION:A sender side package 10 has a selector control signal generating section 11, a control information signal generating section 14 and a SEL 12, and a receiver side package 20 has a DMUX control signal generating section 21, a DMUX 22, a latch circuit 23 and a control information signal processing section 24. The sender side package 10 sends a control information signal in place of a data enable signal of 3rd and succeeding bits of the data top signal. The receiver side package 20 demultiplexes the data enable signal including the control information signal received by the DMUX 22 into the data enable signal and the control information signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data transfer of parallel data in a device such as a digital transmission device.

In parallel data transfer between packages in a digital transmission device, in addition to parallel data, a data top signal, a synchronizing clock, and a data enable signal are simultaneously transmitted to determine whether the data is valid or invalid. Although a method of identifying is used, a more efficient data transfer method is required.

[0003]

2. Description of the Related Art A conventional example will be described with reference to FIGS. 12 is a diagram showing an example of a conventional data transfer method, and FIG. 13 is a diagram showing an example of conventional transfer data.

Conventionally, as a general method of data transfer, as shown in FIG. 12, for example, in addition to 8-bit parallel data, a data top signal (frame signal), a synchronization clock, and the data are effective. In order to identify whether the data is valid or invalid, the data enable signal is transmitted separately, and if the bit of the data enable signal is "H" as shown in the example of FIG. 13, the data of the frame is valid. If it is "L", the data of the frame is invalid.

[0005]

However, although this method is an easy method for constructing a system, in order to identify the validity / invalidity of data, the data for several clocks at the beginning of the data is to be identified. It suffices to look at that bit only for a while, and for that frame, there is no need to refer to that bit after that, and it becomes meaningless data.

The present invention solves the above-mentioned problem. Data transfer which enables checking of transfer data and system monitoring by placing various control signals in the wasted area of the data enable signal. The purpose is to provide a method.

[0007]

FIG. 1 is a principle block diagram of a data transfer method according to the present invention. In the figure, 10 is a transmission side package, 11 is a selector control signal generation unit, 12 is a selector (SEL), 14 is a control information signal generation unit, 20 is a reception side package, 21 is a DMUX control signal generation unit, and 22 is a A separation unit (DMUX), 23 is a latch circuit, and 24 is a control information signal processing unit.

According to the present invention, in order to transfer data from the transmitting side package 10 to the receiving side package 20 in the digital transmission device, a data top signal, a synchronizing clock and a data enable signal are simultaneously transmitted in addition to the parallel data. In the data transfer method of performing data transfer by means of a data transfer method, a selector control signal generator 11 for generating a selector control signal for controlling the selector, and a control information signal generator 14 for generating a control information signal are provided in the transmission side package 10. A SEL 12 that selects either a data enable signal or a control information signal under the control of the selector control signal generation unit 11 is provided.

In addition, DM is provided in the receiving side package 20.
DMUX for generating control signals for controlling UX22
The control signal generation unit 21, the DMUX 22 that receives the data enable signal including the control information signal and separates the data enable signal and the control information signal, and the data enable signal that is separated and sent by the DMUX 22. A latch circuit 23 for latching and a control information signal processing unit 24 for processing the control information signal sent separately by the DMUX 22 are provided.

Then, in the transmitting side package 10, the SEL 12 controls the selector control signal generating section 11 instead of the data enable signal of the 3rd bit onward of the data top signal, and the SEL 12 controls the control information signal generating section. The control information signal generated in 14 is transmitted to the receiving side package 20.
Then, the DM generated by the DMUX control signal generation unit 21
The purpose can be achieved by separating the data enable signal including the control information signal received by the DMUX 22 into the data enable signal and the control information signal by the UX control signal.

Here, in the transmitting side package 10,
The selector control signal generator 11, the counter 15, and
A parallel / serial conversion circuit 18 and the SEL 12 are provided. Further, in the receiving side package 20, the D
A MUX control signal generation unit 21, the DMUX 22, the latch circuit 23, a counter 25, a serial / parallel conversion circuit 28, and a comparator 31 are provided.

Then, instead of the data enable signal of the third and subsequent bits of the data top signal, the sequential number generated by the counter 15 is transmitted and received as the control information signal to be transmitted.

As a second method, instead of the counter 15 in the transmission side package 10, the parity generation unit 1 is used.
6, and a parity generation unit 26 is provided instead of the counter 25 in the reception side package 20.

Then, instead of the sequential number transmitted / received in place of the data enable signal of the third and subsequent bits of the data top signal, the parity generator 1
The parity signal generated in 6 may be transmitted and received.

As a third method, instead of the counter 15 in the transmission side package 10, a CRC calculation unit 17 is provided.
Further, a CRC calculation unit 27 is provided in place of the counter 25 in the reception side package 20.

Then, instead of the sequential number transmitted / received in place of the data enable signal of the 3rd bit onward of the data top signal, the CRC calculation unit 17 is provided.
You may make it transmit / receive the CRC signal produced | generated by.

As a fourth method, the selector control signal generator 11 and the S are provided in the transmitter package 10.
In addition to the EL 12, the counter 15, and the parallel / serial conversion circuit 18, the parity generation unit 16 and the parallel / serial conversion circuit 19 are provided.

Further, in the receiving side package 20, the DMUX control signal generating section 21, the DMUX 22, the latch circuit 23, the counter 25, and the serial / serializer.
In addition to the parallel conversion circuit 28 and the comparator 31, the parity generation unit 26 and the serial / parallel conversion circuit 29.
And a comparator 32.

Then, in addition to the sequential number transmitted / received in place of the data enable signal of the third bit onward of the data top signal, the parity generator 1
The parity signal generated in 6 may also be transmitted / received together.

As a fifth method, in the fourth method,
The parity generation unit 1 in the transmission side package 10
6, the CRC calculation unit 17 is provided, and the CRC calculation unit 27 is provided instead of the parity generation unit 26 in the reception side package 20.

Then, in place of the parity signal generated by the parity generation unit 16 which is transmitted instead of the data enable signal of the third bit onward of the data top signal and the sequential number generated by the counter 41,
The parity signal generated by the CRC calculator 17 and the sequential number generated by the counter 15 may be exchanged.

[0022]

According to the present invention, a selector control signal generator 11 for generating a selector control signal for controlling a selector, a control information signal generator 14 for generating a control information signal, and a selector control signal generator are provided in the transmitting side package 10. A SEL 12 is provided for selecting either the data enable signal or the control information signal under the control of the unit 11.

Further, the receiving side package 20 receives a DMUX control signal generating section 21 for generating a control signal for separating a data enable signal and a control information signal, and a data enable signal including the control information signal. , DMUX2 for separating data enable signal and control information signal
2, a latch circuit 23 for latching a data enable signal sent separately by the DMUX 22 by a data latch pulse from the DMUX control signal generation section 21, and DM
A control information signal processing section 24 for processing the control information signal separated and sent in the UX 22 is provided.

By doing so, in the transmission side package 10, the SEL 12 controls the selector control signal generation section 11 instead of the data enable signal of the third and subsequent bits of the data top signal. 1
The control information signal generated in 4 can be transmitted. Further, in the receiving-side package 20, the DMUX 2 is controlled by the DMUX control signal generated by the DMUX control signal generation unit 21.
Since the data enable signal including the control information signal received in 2 can be separated into the data enable signal and the control information signal, the control information signal can be effectively used for monitoring the transfer data.

Here, a selector control signal generator 11, a counter 15, a parallel / serial conversion circuit 18, and a SEL 12 are provided in the transmission side package 10. In addition, a DMUX control signal generation unit 21, a DMUX 22, a latch circuit 23, a counter 25, a serial / parallel conversion circuit 28, and a comparator 31 are provided in the reception side package 20.

By doing so, the sequential number generated by the counter 15 can be exchanged as a control information signal in place of the data enable signal of the third bit onward of the data top signal.

As a second method, instead of the counter 15 in the transmission side package 10, the parity generation section 16 is used.
To provide. In addition, the counter 2 in the receiving package 20
Instead of 5, a parity generation unit 26 is provided.

By doing so, the parity signal generated by the parity generation unit 16 can be transmitted / received instead of the sequential number transmitted / received instead of the data enable signal of the third and subsequent bits of the data top signal. it can.

As a third method, a CRC calculation unit 17 is provided instead of the counter 15 in the transmission side package 10. Also, the counter 25 in the receiving package 20
Instead of this, a CRC calculation unit 27 is provided.

By doing so, the CRC signal generated by the CRC calculation unit 17 can be transmitted / received instead of the sequential number transmitted / received instead of the data enable signal of the 3rd bit onward of the data top signal. it can.

Furthermore, as a fourth method, the selector control signal generator 11 and SEL1 are provided in the transmitter package 10.
In addition to 2, the counter 15 and the parallel / serial conversion circuit 18, the parity generation unit 15 and another parallel / serial conversion circuit 19 are provided. And the receiving package 2
In 0, DMUX control signal generator 21, DMUX 22,
In addition to the latch circuit 23, the counter 25, the serial / parallel conversion circuit 28, and the comparator 31, the parity generation unit 84
, Another serial / parallel conversion circuit 29, and another comparator 32 are provided.

By doing so, the parity signal generated by the parity generation unit 16 is also transmitted / received together with the sequential number transmitted / received in place of the data enable signal of the 3rd bit onward of the data top signal. can do.

As a fifth method, in the fourth method, the parity generation unit 16 in the transmission side package 10 is used.
Instead of this, a CRC calculation unit 17 is provided. Further, instead of the parity generation unit 26 in the reception side package 20, a CRC
A calculation unit 27 is provided.

By doing so, instead of the parity signal generated by the parity generation unit 15 which is transmitted instead of the data enable signal of the third and subsequent bits of the data top signal and the sequential number generated by the counter 41, The parity signal generated by the CRC calculator 17 and the sequential number generated by the counter 15 can be exchanged.

[0035]

EXAMPLES Next, examples will be described with reference to FIGS. 2 is a first embodiment of the data transfer method according to the present invention, FIG. 3 is a second embodiment of the data transfer method according to the present invention, and FIG. 4 is a third embodiment of the data transfer method according to the present invention. 5 shows a fourth embodiment of the data transfer method according to the present invention, and FIG. 6 shows a fifth embodiment of the data transfer method according to the present invention.

FIG. 7 shows the transfer data of the first embodiment, FIG. 8 shows the transfer data of the second embodiment, FIG. 9 shows the transfer data of the third embodiment, and FIG. 10 shows the fourth. FIG. 11 shows transfer data of the embodiment, and FIG. 11 shows transfer data of the fifth embodiment.

In the figure, the same reference numerals as those in FIG.
Reference numerals 15 and 25 are counters, 18 and 19 are parallel / serial conversion circuits, 16 and 26 are parity generation units, and 17 and 27.
Is a CRC calculation unit, 28 and 29 are serial / parallel conversion circuits, and 31 and 32 are comparators.

First, referring to FIG. 7 regarding the first embodiment of FIG.
Will be described with reference to. The first embodiment transmits a sequential number (SN) as a control information signal to be transmitted instead of an invalid data enable signal.

In the transmitting side package 10, the counter 15
The counter output, which is a parallel signal, is converted into a serial signal, and the number is sequentially increased one by one with a delay of one frame, and the number is placed on the data enable signal line.

The receiving-side package 20 has a counter 25 therein, and converts the counter output and the serial number (SN), which is the serial signal transmitted, into a parallel signal and compares the parallel signal.

By making a comparison, it is possible to check whether or not the data has been transferred correctly and whether or not the data has been lost. Next, the second embodiment shown in FIGS. 3 and 8 transmits a parity signal as a control information signal instead of an invalid data enable signal.

The transmission side package 10 has a parity generation unit 16, generates parity for each bit from the parallel data to be transferred, converts the parity signal which is a parallel signal into a serial signal, and delays it by one frame. ,
As shown in FIG. 8, a parity signal for each bit of parallel data is sequentially placed on the data enable signal line.

The receiving side package 20 also has a parity generating section 27 therein and generates a parity for each bit from the transferred parallel data. On the other hand, the parity signal for each bit sent via the data enable signal line is converted into a parallel signal and then compared with the parity generated by the parity generation unit 84.

By comparison, a parity check can be made as to whether the data was transferred correctly. As described above, by allowing the transmission and reception of the parity signal, the parity check can be performed without using a separate line for parity.

Next, the third embodiment shown in FIGS. 4 and 9 transmits a CRC bit as a control information signal instead of an invalid data enable signal. The transmission side package 10 has a CRC calculation unit 17, performs a CRC calculation on the parallel data to be transferred, converts the CRC bit that is a parallel signal into a serial signal, and
It is placed on the data enable signal line with a frame delay, as shown in FIG.

The receiving side package 20 also has a CRC inside.
It has an arithmetic unit 27 and C of the parallel data transferred.
Perform RC calculation. On the other hand, the CRC bit sent via the data enable signal line is converted into a parallel signal and then compared with the CRC bit generated by the CRC calculation unit 27.

By comparing, it is possible to perform a CRC check whether there is a bit error in the data.
By allowing the CRC bits to be transmitted and received in this way, it becomes possible to perform the CRC check without using the separate line for the CRC bits.

Next, in the fourth embodiment shown in FIGS. 5 and 10, a sequential number and a parity signal are transmitted as a control information signal instead of an invalid data enable signal.

In the transmitting side package 10, the counter 15
The counter output, which is a parallel signal, is converted into a serial signal, and the number is sequentially increased one by one with a delay of one frame, and the number is placed on the data enable signal line.

Further, the transmission side package 10 also has a parity generation section 16, which generates a parity for each bit from the parallel data to be transferred and converts the parity signal which is a parallel signal into a serial signal. With a frame delay, as shown in FIG. 10, a parity signal for each bit of parallel data is sequentially placed on the data enable signal line.

The receiving side package 20 has a counter 25 therein, and converts the output of the counter and the serial number (SN), which is the serial signal transmitted, into a parallel signal and compares the parallel signal.

Further, the receiving side package 20 has a parity generating section 26 therein and generates a parity for each bit from the transferred parallel data. On the other hand, the parity signal for each bit sent via the data enable signal line is converted into a parallel signal and then compared with the parity generated by the parity generation unit 26.

In this way, the sequential number (S
By comparing N), it is possible to check whether the data has been transferred correctly and whether it has been lost in the middle.

By comparing the parities,
A parity check can be made to see if the data was transferred correctly. As described above, by allowing the transmission and reception of the parity signal, the parity check can be performed without using a separate line for parity.

Next, in the fifth embodiment shown in FIGS. 6 and 11, a sequential number and a parity signal are transmitted as a control information signal instead of an invalid data enable signal.

In the transmitting side package 10, the counter 15
The counter output, which is a parallel signal, is converted into a serial signal, and the number is sequentially increased one by one with a delay of one frame, and the number is placed on the data enable signal line.

Further, the transmission side package 10 has a CRC
The arithmetic unit 17 is also included, performs CRC calculation of the parallel data to be transferred, converts the CRC bit that is a parallel signal into a serial signal, and puts it on the data enable signal line with one frame delay, as shown in FIG. .

The receiving-side package 20 has a counter 25 therein, and converts the output of the counter and the serial number (SN), which is the serial signal transmitted, into a parallel signal, and compares the parallel signal.

Further, the receiving side package 20 has a CRC calculating section 27 therein and performs CRC calculation of the transferred parallel data. On the other hand, the CRC bit sent via the data enable signal line is converted into a parallel signal and then compared with the CRC bit generated by the CRC calculation unit 85.

In this way, the sequential number (S
By comparing N), it is possible to check whether the data has been transferred correctly and whether it has been lost in the middle.

Also, by comparing the CRC calculation results, it is possible to perform a CRC check whether there is a bit error in the data. By allowing the CRC bits to be transmitted and received in this way, it becomes possible to perform the CRC check without using the separate line for the CRC bits.

[0062]

As described above, according to the present invention,
By transmitting various control information signals instead of the useless portion of the data enable signal and transmitting the data, it is possible to check the data to be transferred and monitor the system without using a separate line.

Further, by placing a plurality of control information signals to be transmitted on the useless portion of the data enable signal, it becomes possible to more efficiently check the transfer data and monitor the system.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of a data transfer method according to the present invention.

FIG. 2 is a first embodiment of a data transfer method according to the present invention.

FIG. 3 is a second embodiment of the data transfer method according to the present invention.

FIG. 4 is a third embodiment of the data transfer method according to the present invention.

FIG. 5 is a fourth embodiment of the data transfer method according to the present invention.

FIG. 6 is a fifth embodiment of the data transfer method according to the present invention.

FIG. 7 is a diagram showing transfer data according to the first embodiment.

FIG. 8 is a diagram showing transfer data according to the second embodiment.

FIG. 9 is a diagram showing transfer data according to the third embodiment.

FIG. 10 is a diagram showing transfer data according to the fourth embodiment.

FIG. 11 is a diagram showing transfer data according to the fifth embodiment.

FIG. 12 is a diagram showing a conventional data transfer method.

FIG. 13 is a diagram showing conventional transfer data.

[Explanation of symbols]

 10 transmission side package 11 selector control signal generation section 12 SEL 14 control information signal generation section 15, 25 counter 16, 26 parity generation section 17, 27 CRC calculation section 18, 19 parallel / serial conversion circuit 20 reception side package 21 DMUX control signal Generation unit 22 DMUX 23 Latch circuit 28, 29 Serial / parallel conversion circuit 31, 32 Comparator

Claims (6)

[Claims] 1. A data top signal, a synchronizing clock, and a data enable signal in addition to parallel data for transferring data from a transmitting side package (10) to a receiving side package (20) in a digital transmission device. In a data transfer method for simultaneously transmitting and transferring data, a selector control signal generation section (11) for generating a selector control signal for controlling a selector and a control for generating a control information signal are provided in the transmission side package (10). An information signal generation unit (14) and a SEL (12) for selecting either a data enable signal or a control information signal under the control of the selector control signal generation unit (11) are provided, and the reception side package (20) A DMUX control signal generator (21) for generating a control signal for controlling the DMUX (22) and a data including a control information signal. Receiving an enable signal, a DMUX for separating the data enable signal and the control information signal (22), the DMUX (22)
And a control information signal processing unit (24) for processing the control information signal separated and sent by the DMUX (22) and the latch circuit (23) which separates and sent the data enable signal. ) Is provided, the transmission side package (10) is controlled by the selector control signal generation unit (11) in place of the data enable signal of the third bit and subsequent bits of the data top signal.
The EL (12) transmits the control information signal generated by the control information signal generation unit (14), and the reception side package (20) uses the DMUX control signal generated by the DMUX control signal generation unit (21). A data transfer method, characterized in that the data enable signal including the control information signal received by the DMUX (22) is separated into a data enable signal and the control information signal. 2. The selector control signal generation unit (11), a counter (15), a parallel / serial conversion circuit (18), and the SEL (in the transmission side package (10) according to claim 1. 12) is provided, and the DMUX control signal generation unit (21), the DMUX (22), the latch circuit (23), the counter (25), and the serial / parallel are provided in the reception side package (20). A conversion circuit (28) and a comparator (31) are provided, and a sequential number generated by the counter (15) as a control information signal to be transmitted instead of the data enable signal of the 3rd bit onward of the data top signal. A data transfer method characterized by transmitting and receiving data. 3. The counter (1) according to claim 2, wherein the counter (1) in the transmission side package (10).
5), a parity generator (16) is provided, and the counter (2) in the receiving side package (20) is provided.
In place of 5), a parity generation section (26) is provided, and the parity generation section (16) generates the parity number instead of the sequential number transmitted / received in place of the data enable signal of the third and subsequent bits of the data top signal. A data transfer method characterized by transmitting and receiving the generated parity signal. 4. The counter (1) according to claim 2, wherein the counter (1) in the transmission side package (10).
In place of 5), a CRC calculation unit (17) is provided, and the counter (2) in the reception side package (20) is provided.
In place of 5), a CRC calculation unit (27) is provided, and the CRC calculation unit (17) is used in place of the sequential number which is transmitted / received instead of the data enable signal of the 3rd bit onward of the data top signal. CRC
A data transfer method characterized by transmitting and receiving signals. 5. The selector control signal generation unit (11), the SEL (12), the counter (15), the parallel / serial conversion circuit () according to claim 2, wherein the transmission side package (10) is provided. 1
In addition to 8), the parity generation unit (16) and another parallel / serial conversion circuit (19) are provided, and the DMUX control signal generation unit (21) and the DMUX control signal generation unit (21) are provided in the reception side package (20). In addition to the DMUX (22), the latch circuit (23), the counter (25), the serial / parallel conversion circuit (28), and the comparator (31), the parity generation unit (26) and another serial A parallel / parallel conversion circuit (29) and another comparator (32) are provided, and the parity generation unit is used instead of the sequential number that is transmitted / received instead of the data enable signal of the third bit and subsequent bits of the data top signal. A data transfer method, wherein the parity signal generated in (16) and the sequential number generated in the counter (15) are transmitted and received. 6. The CRC calculation unit (17) according to claim 5, in place of the parity generation unit (16) in the transmission-side package (10), and in the reception-side package (20). The CRC calculation unit (27) is provided in place of the parity generation unit (26), and the parity generation unit (1) that transmits instead of the data enable signal of the third and subsequent bits of the data top signal.
6), instead of the parity signal generated by the counter (41) and the sequential number generated by the counter (41), the parity signal generated by the CRC calculator (17) and the counter (1
A data transfer method, wherein the sequential number generated in 5) is exchanged.