JPS592461A - Virtual synchronism preventing system - Google Patents

Virtual synchronism preventing system

Info

Publication number
JPS592461A
JPS592461A JP57109909A JP10990982A JPS592461A JP S592461 A JPS592461 A JP S592461A JP 57109909 A JP57109909 A JP 57109909A JP 10990982 A JP10990982 A JP 10990982A JP S592461 A JPS592461 A JP S592461A
Authority
JP
Japan
Prior art keywords
signal
synchronization
pattern
transmission line
code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57109909A
Other languages
Japanese (ja)
Inventor
Michinobu Ohata
大畑　道信
Hiroshi Takeo
竹尾　浩
Masaaki Ogiso
小木曽　正明
Hiroshi Nakade
浩志 中出
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57109909A priority Critical patent/JPS592461A/en
Publication of JPS592461A publication Critical patent/JPS592461A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H04L25/4923—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes
    • H04L25/4925—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes using balanced bipolar ternary codes

Abstract

PURPOSE:To prevent surely virtual synchronism with a simple constitution by applying violation to the alternate order of transmission line codes for transmitting them in a bit location where a synchronising pattern is inserted. CONSTITUTION:An input voice signal is converted into a PCM signal at a coder 1, inputted to a synchronizing pattern inserting section 2, a synchronizing pattern inserting location pulse (a) being a high level at the synchronizing pattern inserting location is applied, a prescribed synchronizing pattern is inserted successively to the syncronizing bit of the signal from the coder 1 and a transmission PCM code (b) is formed. A transmission line code converting section 3 converts the signal (b) into an alternate code, a VL is applied based on a violation VL generating signal (c) from an AND gate 4 and transmitted on a transmission line 5 as an output signal (d). An input signal (e) is converted into the original PCM signal at a transmission code converting section 6 of a receiving section and it is converted into a sound signal at a decoder 8. The converting section 6 detects the VL further, a signal (f) is inputted to a synchronism circuit 7 as a synchronizing pattern. The synchronizing pattern not detected for the VL is detected as a pattern error.

Description

【発明の詳細な説明】 （１）　　発明の技術分野 本発明は、擬似同期防止方式に関し、特に伝送路符号と
して交番符号すなわちバイポーラ符号２用いたデジタル
通信システムにおける擬似同期防止方式に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for preventing pseudo-synchronization, and particularly to a method for preventing pseudo-synchronization in a digital communication system using an alternating code, that is, bipolar code 2, as a transmission line code.

（２）　　技術り）背景 一般に、ＰＣＭ信号あるいは各種のデータ信号を伝送す
るデジタル通信システムにおいては、伝送路符号として
交番符号が用いられ、また核伝送路符号の所定ビット数
例えば１フレームごとにあらかじめ定めらｎだ同期パタ
ーン用Ｑ〕ビットを挿入する。こσ〕ようなデジタル通
信システムにおいては、受信側で該同期パターンを検出
して同期状態を確立し、同期パターンの挿入されたビッ
ト位置２基準として受信信号の取り出しが行なわれる。(2) Technology) Background Generally, in digital communication systems that transmit PCM signals or various data signals, alternating codes are used as transmission line codes, and a predetermined number of bits of the nuclear transmission line code, for example, are set in advance for each frame. Insert a predetermined Q] bit for a synchronization pattern. In such a digital communication system, the receiving side detects the synchronization pattern to establish a synchronization state, and the received signal is extracted based on bit position 2 where the synchronization pattern is inserted.

ところが、同期パターンの挿入されたビット以外０Ｊビ
ット位置に同期パターンと同じがま７ｃは類似のパター
ンが存在する場合は同期パターンの挿入されたビット位
ｌｉｔ以外のビット位置を同期ビットと判断していわゆ
る擬似向、期を生ずることがある。この工うな擬似同期
が生ずると送信された信号が正常に受信されないことと
なるので、擬似同期２適確に防止することが要求される
。However, if a similar pattern exists in the 0J bit position other than the bit where the synchronization pattern was inserted, 7c determines that the bit position other than the bit position lit where the synchronization pattern is inserted is the synchronization bit. So-called pseudo-direction and periods may occur. If pseudo-synchronization occurs without this means, the transmitted signal will not be received normally, so it is required to properly prevent pseudo-synchronization 2.

（３）　　従来技術と問題点 、このため従来、上述の工うなデジ、タル通信システム
においては、同期パターンにｃ１ζＣ（サイクリック９
ダンダンシーコード）チェックビットを・付加し、受信
側において１６４期パターンと共に該ＣＩζＣチェック
ピントｅ抽出し７てパターン誤りを検出し、そｒムにＪ
：り擬似同期を防止していＴ、、。(3) Prior art and problems: Therefore, conventionally, in the above-mentioned digital and digital communication systems, c1ζC (cyclic 9C) is used as a synchronization pattern.
A check bit (dundancy code) is added, and the receiving side extracts the CIζC check pinpoint along with the 164th period pattern to detect a pattern error, and then J
: Prevents pseudo-synchronization.

しかしながら、ｉＩＩ記従来形においては、送信側およ
び受（ｆｌ　ｆｌｌｌｌｌｌｌ知力ＲＣチェックピット
の挿入およびＦＡ９判だ等Ｑ）処理回路？設ける必要が
あるとともに、同期誤りが検出さ／−１，７こ揚台に１
１１〕ビット位置に同期パターンと同じパターンが挿入
され°Ｃいるか否か３判定する副同期０，１」路３設け
、該副同期回路によって検出さＩＩＪＣ同期パターンの
ビット位置が新１こな同期ビットきなるように切換えを
行なう必要がある。この丸め、従来形においてはハード
ウェアの規模が大きくなり１ｆｆｉ係システムのコスト
が上昇するとともに信頼性が低下すると。However, in the conventional type described in III, the transmitting side and the receiving (flllllllllll intelligence RC check pit insertion and FA9 size Q) processing circuit? In addition, it is necessary to set up a synchronization error detection/-1.
11] A sub-synchronization circuit 3 is provided to determine whether the same pattern as the synchronization pattern is inserted at the bit position. It is necessary to switch the bits in a rapid manner. In the conventional type, this rounding increases the scale of the hardware, increases the cost of the 1ffi system, and reduces reliability.

いう不都合があった。There was an inconvenience.

本発明の目的は、前述の従来形における問題点に鑑み、
伝送路符号として交番、符号を用いるデジタル通信シス
テムの擬似同期防止方式において、同期パターンが挿入
されたビット位置において、伝送路符号の交番順序にバ
イオレーションをかけるさいう構想に基づき、簡単なハ
ードウェアにエフ適確に擬似同期の防止を打なうことに
ある。In view of the problems in the conventional type described above, the purpose of the present invention is to
In a pseudo-synchronization prevention method for digital communication systems that use alternating codes as transmission line codes, we have developed a simple hardware based on the concept of applying a violation to the alternating order of transmission line codes at the bit position where a synchronization pattern is inserted. The key to this is to accurately prevent pseudo-synchronization.

（５）　　発明の構成 そしてこの目的は、本発明によれば、伝送路符号として
交番符号を用い、所定のビット位置ｆこ同期パターン２
挿入してデジタル信号の同期伝送を行なうデジタル通信
システムの擬似同期防止方式におりて、同期パターンが
挿入さｎたビット位置にオイて伝送路符号の交番順序に
バイオレーション２かけ、受信側でバイオレーション？
検出しない同期パターンはパターンＲＡＪ）として検出
することにエフ擬似同ルＪ２防止することを特徴とする
擬似同期防止方式２提供することによって達成される。(5) Structure and object of the invention According to the present invention, an alternating code is used as a transmission path code, and a synchronization pattern 2 is set at a predetermined bit position f.
In a pseudo-synchronization prevention method for a digital communication system that performs synchronized transmission of digital signals by inserting a synchronization pattern, the bit position where the synchronization pattern is inserted is multiplied by 2 violations in the alternating order of the transmission line code, and the receiving side Ration?
This is achieved by providing a false synchronization prevention method 2 characterized in that it prevents undetected synchronization patterns from being detected as patterns RAJ).

（６ン　発明の実施例 μ下図面を用いて本発明の詳細な説明する。(6) Examples of the invention The present invention will be described in detail using the drawings below.

第１図Ｖｉ、本発明の方式を実施するためのデジタル通
信システムの概略の構Ｒを示す、同図において、五は例
えば音声（ｉｆ号等をＰＣＭ符号等のデジタル符号に変
換する符号器、２は同期パターン挿入部、３は例えばＮ
Ｒ，Ｚ形式のデジタル信号を交番符号に変換する伝送路
符号変換部、そしてｉｔアンドゲートであｔ以上は送信
部を構成する、５は交番符号を伝送する伝送路である。FIG. 1 Vi shows a schematic structure R of a digital communication system for implementing the method of the present invention. 2 is a synchronization pattern insertion section, 3 is, for example, N
A transmission line code converter converts R, Z format digital signals into alternating codes, and an IT and gate with t or more constitutes a transmitter. 5 is a transmission line for transmitting alternating codes.

また、６は受（ＮＬｚ交番符号をＮＲＺ符号等のデジタ
ル信号に変換する伝送路符号変換部、７は同期パターン
の検出等を行なう同期回路、そして８は受信したＰＣＭ
信号等を元の音声信号に変換する復合器であり以上の装
置ｔこよりて受信部が構成さｎる。In addition, 6 is a receiver (a transmission line code converter that converts the NLZ alternating code into a digital signal such as an NRZ code, 7 is a synchronization circuit that detects a synchronization pattern, etc., and 8 is a received PCM
It is a decoder that converts a signal etc. into an original audio signal, and the above-mentioned device constitutes a receiving section.

次に、第２図２参照して第１図の通信システムの動作を
説明する。符号器ｌに入力された音声信号は該符号器１
内のＡ／Ｄ変換器等に工ってＰＣＭ信号に変換され同期
パターン挿入部２に入力される。同期パターン挿入部２
には、例えばフレームごと＆Ｊ　同期パターン挿入位置
において高レベルとなる同期パターン挿入位置パルスａ
が印加されており、このパルスに基づき符号器ｌから入
力されたＰＣＭ信号の同期ビットに所定の同期パターン
が順次挿入されて送信用ＰＣＭ信号すが作取される。伝
送路符号変換部３はこの送信用ＰＣＭ信号すを交番符号
すなわちバイポーラ符号に変換するものであるが、９：
番符号を発生する際にアンドゲート４から人力されるバ
イオレーション発生信号Ｃに基づきバイオレーションを
発生する。アンドゲート４０）入力には送信用ＰＣＭ信
号すお工び同期パターン挿入位欧パルスａが入力されて
おり、同期パターンの挿入位置において同期パターンの
挿入さ７またＰＣＭ信号が「１」の時、バイオレーシラ
ン発注の指令を伝送路符号変換部３に入力する。シ１こ
がって、伝送路符号変換部３の出力信号（ｌは第２図に
示すようにバイオレージ日ン発生信号Ｃの位置において
バイオレーションががけられた交番符号となる。Next, the operation of the communication system shown in FIG. 1 will be explained with reference to FIG. 2. The audio signal input to the encoder l is
The signal is converted into a PCM signal using an A/D converter, etc., and input to the synchronization pattern insertion section 2. Synchronization pattern insertion section 2
For example, for each frame &J, the synchronization pattern insertion position pulse a which becomes high level at the synchronization pattern insertion position
is applied, and based on this pulse, a predetermined synchronization pattern is sequentially inserted into the synchronization bits of the PCM signal input from the encoder 1 to produce a PCM signal for transmission. The transmission line code converter 3 converts this transmission PCM signal into an alternating code, that is, a bipolar code.
A violation is generated based on a violation signal C input manually from the AND gate 4 when the number code is generated. The AND gate 40) inputs the transmitting PCM signal and synchronization pattern insertion position pulse a, and when the synchronization pattern is inserted at the synchronization pattern insertion position and the PCM signal is "1", A command for ordering bioresilan is input to the transmission line code converter 3. As a result, the output signal of the transmission line code converter 3 (l becomes an alternating code with a violation added at the position of the violation date signal C, as shown in FIG. 2).

こＱ〕ような出力信号ｄは伝送路５を介して入力信号ｅ
として受信部に入力される。該入力信号ｅり魚送路符号
変換部６において例えばＮＲＺ形弐〇）元のＰＣＭ信号
に変換され、かつ復合器８において該ＰＣＭ信号が元の
音声信号に変換される。This Q] output signal d is transmitted to the input signal e via the transmission line 5.
is input to the receiving section as The input signal is converted into the original PCM signal, for example, NRZ type, in the fish feed path code converter 6, and the PCM signal is converted into the original audio signal in the decoder 8.

伝送路符号変換部６はさらに、入力信号ｅｃｌ）バイ゛
オレージョン２検出し、バイオレージ賓ンが検出さｎ、
ｌこ位置で例えば高、レベルとなるノくイオレーション
検出イ言号ｆを出力する。このバイオレージ画ン検出イ
３号ｆは同期バター、ンとして同期回路７に入力され、
所定フレーム分のパターンがあらかじめ定められＩＣ同
期パターンと一致しているか否かを検出することによっ
て同期検出が行なわれる。The transmission path code conversion unit 6 further detects the input signal ecl) violation 2, and detects the violation n of the input signal ecl).
At this position, for example, the iolation detection signal f is output, which becomes a high level. This biorage image detection number f is input to the synchronization circuit 7 as a synchronization butter.
Synchronization detection is performed by detecting whether a pattern for a predetermined frame is predetermined and matches an IC synchronization pattern.

同期回路７において正常に同期検出が行なわれている場
合には同期回路７から復合器８に制御信号が入力さｆ’
Ｌる。この制御信号に基づき復合器８は入力され九ＰＣ
Ｍ信号のＤ／Ａ変換等の動作を行ない音声信号を出力す
ることができる。もし、同期回路７において同期検出が
行なわれず、したがって同期外れの状態になっている場
合には、復合器８に前記制御信号が入力されずしたがっ
て音声信号が出力さｎ、ない。When synchronization detection is performed normally in the synchronization circuit 7, a control signal is input from the synchronization circuit 7 to the decoder 8 f'
L. Based on this control signal, the decoder 8 is input
It is possible to perform operations such as D/A conversion of the M signal and output an audio signal. If synchronization detection is not performed in the synchronization circuit 7 and the synchronization is out of synchronization, the control signal is not input to the decoder 8 and therefore no audio signal is output.

上述において、仮に伝送路エラーにより受信部における
入力信号ｅにおいて同期ノくターン以外の位置でバイオ
レーションが発生し７こ場合、このノゝイオレーシ９ン
が発生したピット位置で同期ノ（ターンの検出が開始さ
Ｔｔても、後続ｔｈフレームにおいて同じピット位置で
同期パターンが連続する確立は極めて低く、し罠がって
擬似同期に引き込１れる確立も極めで低くなる。In the above, if a violation occurs in the input signal e in the receiving section at a position other than the synchronous turn due to a transmission path error, 7 then the synchronous turn is detected at the pit position where this violation occurs. Even if Tt is started, the probability that the synchronization pattern will continue at the same pit position in the subsequent th frame is extremely low, and the probability that it will be trapped into pseudo synchronization is also extremely low.

なお、上述においては送イハ部において同期ビット位［
ｉｆにバイオレーションをかける際にＰＣＭ信号が「］
」であることを検出し、該ＰＣＭ信号がｒｌＪＣ））場
合にσ）みパイオレーシロンをかけているが、本発明は
これに限らず例えばＰＣＭ（ｆ１号が「Ｉ」でなくても
バイオレーションをかけるという方式も実現可能である
ことは明らかである。例えば、ｐｃＭ（＝号が「０」の
場合には同期ピット０＞後に最初に「Ｊ」になっ１こピ
ット位置でバイオレーションをかけることも可能である
。In addition, in the above, the synchronization bit position [
When applying a violation to if, the PCM signal is
", and when the PCM signal is rlJC)), the present invention is not limited to this. It is clear that it is also possible to apply a system of applying rations. For example, if pcM (= is "0", synchronization pit 0 > then "J" first and a violation occurs at the 1st pit position). It is also possible to apply

（７）発明の効果 このように本発明によ１ｔば、ＣＲＣチェックビット等
によって同期検出を行なう従来形に比し、極めて簡単な
ノ・−ドウエアによって同期検出を行なうことが可能で
あるととも昏乙極めて適確に、擬似同期を防止すること
ができる。(7) Effects of the Invention As described above, according to the present invention, it is possible to perform synchronization detection with extremely simple hardware, compared to the conventional type that performs synchronization detection using CRC check bits, etc. Pseudo-synchronization can be prevented very accurately.

第１図は、本発明０）　ｌ実施例に係る方式を実施する
罠めの通信システムＣｌｌ　１例を示すブロック回路図
、そして 第２図は、第１図のシステノ、　ＣＪＪ動作を説明する
１ｃめの波形図である。FIG. 1 is a block circuit diagram showing an example of a trap communication system Cll implementing the system according to the present invention 0)l embodiment, and FIG. 2 is a block circuit diagram illustrating the system CJJ operation of FIG. FIG.

ｌ・・・・・・符号器、２・・・・・・同期ノ（ターン
挿入部、３・・・・・・伝送路符号変換部、４・・・・
・・アンドゲート、５・・・・・・伝送路、６・・・・
・・伝送路符号変換部、７・・・・・・同期回路、８・
・・・・・復合器。l... Encoder, 2... Synchronization section (turn insertion section, 3... Transmission line code conversion section, 4...
...And gate, 5...Transmission line, 6...
...Transmission path code conversion unit, 7...Synchronization circuit, 8.
... Decoupler.

（７）発明の効果 このように本発明によれば、ＣＲＣチェックビット等に
よって同期検出を行なう従来形に比し、極めて簡単なノ
・−ドウエアによって同期検出を行なうことが可能であ
るとともに、極めて適確【こ、擬似同期を防止すること
ができる。(7) Effects of the Invention As described above, according to the present invention, it is possible to perform synchronization detection using extremely simple software compared to the conventional type that performs synchronization detection using CRC check bits, etc. [This can prevent false synchronization.]

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明ＣＪＪ　１実施例に係る方式を実施す
る罠めの通信シ２テムＣＬＪ　１例を示すブロック回路
図、そして 第４図は、第１図のシステムの動作を説明する罠めの波
形図である。 １・・・・・・符号器、２・・・・・・同期ノ（ターン
挿入部、３・・・・・・伝送路符号変換部、４・・・・
・・アンドゲート、５・・・・・・伝送路、６・・・・
・・伝送路符号変換部、７・・・・・・同期回路、８・
・・・・・復合器。 第１図 第′２図 同期バタン 挿ヵ位置　。−ｍ−「Ｌ−一一一、−−−−−□−−丁
ゴー−−Ｐ　ＣＭイ□っｂ　　　　　　−−−−−−−
−一口」−シバイオレー／ヨ／。、［］−一−１−一一
一発生信号FIG. 1 is a block circuit diagram showing an example of a trap communication system CLJ implementing the system according to the first embodiment of the present invention, and FIG. 4 is a trap circuit diagram illustrating the operation of the system of FIG. FIG. 1... Encoder, 2... Synchronization section (turn insertion section, 3... Transmission line code conversion section, 4...
...And gate, 5...Transmission line, 6...
...Transmission path code conversion unit, 7...Synchronization circuit, 8.
... Decoupler. Figure 1 Figure '2 Synchronous button insertion position. -m-"L-111,-----□--Ding Go--P CM I□b----
-Bite” -Shibiore/Yo/. , []-1-1-111 generated signal

Claims (1)

【特許請求の範囲】[Claims] 伝送路符号として交番符号を用い、所定クツビット位置
に同期パターンを挿入してデジタル信号の同期伝送２行
なうデジタル通信システムの擬似同期防止方式において
、同期パターンが挿入され、たビット位置において伝送
路ｎ号力交番順序にバイオレーションをかけ、受信側で
バイオレーションを検出しない同期パターンはパターン
誤りとして検出することにより擬似同期Ｐ防止すること
を特徴とする擬似同期防止方式。In a pseudo synchronization prevention method for a digital communication system that uses an alternating code as a transmission line code and inserts a synchronization pattern at a predetermined bit position to perform two synchronous transmissions of digital signals, the synchronization pattern is inserted and the transmission line n number is inserted at the bit position. A pseudo synchronization prevention method characterized in that a violation is applied to the power alternation order, and a synchronization pattern in which no violation is detected on the receiving side is detected as a pattern error to prevent pseudo synchronization P.
JP57109909A 1982-06-28 1982-06-28 Virtual synchronism preventing system Pending JPS592461A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57109909A JPS592461A (en) 1982-06-28 1982-06-28 Virtual synchronism preventing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57109909A JPS592461A (en) 1982-06-28 1982-06-28 Virtual synchronism preventing system

Publications (1)

Publication Number Publication Date
JPS592461A true JPS592461A (en) 1984-01-09

Family

ID=14522218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57109909A Pending JPS592461A (en) 1982-06-28 1982-06-28 Virtual synchronism preventing system

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Country Link
JP (1) JPS592461A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6444651A (en) * 1987-08-13 1989-02-17 Matsushita Electric Works Ltd Home bus system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6444651A (en) * 1987-08-13 1989-02-17 Matsushita Electric Works Ltd Home bus system
JP2511469B2 (en) * 1987-08-13 1996-06-26 松下電工株式会社 Home bus system

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