JPH0352350A - Data communication controller - Google Patents

Abstract

PURPOSE:To prevent the destruction of a transmission frame data by burying the data of a prescribed bit location with a logic value with lower priority on a bus till the establishment of synchronization of a multi-frame is decided and forming the transmission frame. CONSTITUTION:A circuit 101 decomposes a reception frame and extracts the reception value of FA (auxiliary frame) bit and M (multi-framing) bit from the reception frame. A circuit 104 has a parallel/serial conversion function outputting a 4-bit Q bit data set freely by the user at every prescribed timing one by one bit and sends the serial bit data to a circuit 105. A Q bit data transmission control circuit 105 controls whether the Q bit data set by the user is sent or the FA bit received from a network terminator is sent as Q bit data like an echo depending whether FA bit synchronization is taken or not. Thus, the prescribed bit location data of a transmission frame sent by a terminal equipment whose multi-frame synchronization is already established is not destroyed.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a terminal-side data communication control device that transmits and receives multi-frames in a network such as an ISDN user network interface. The present invention relates to a technique for preventing transmission frame data from a terminal that has already achieved multi-frame synchronization from being destroyed until a terminal that has not achieved multi-frame synchronization achieves synchronization. More specifically, the present invention also relates to preventing corruption of Q-bit data in ISDN.

[Prior Art] In ISDN, a subscriber terminal equipment (TE) receives a multi-frame signal from a network terminal equipment (NT).
is supposed to be able to transmit Q-bit data after synchronization is established. ■Multi-frame in SDN is described in CC ITT Recommendation I430,
The outline is shown in the figure. Further, FIG. 3 shows the format of one frame.

In Figure 3, F=Framing Pit L = DC parallel bit D=D channel bit E=D echo channel bit FA = auxiliary frame bit N = Bit set in FA (DSU to TE direction) B, = bit in B channel 1 B. = bit in B channel 2 A = bit used for activation S = Reserve bit for future use M=Multi-flaming pit It is.

In I430, a multiframe consists of 20 frames, identified by the FA bit and M bit in the frame sent from the NT to the TE. And N.T.
(In the example in Figure 2, the FA bit positions of the 1st, 6th, ... 16th frames
"1" is transmitted at the bit position (bit position), and "1" is transmitted at the M bit position of every 20 frames (in the example of FIG. 2, the M bit position of the 1st and 21st frames).

On the other hand, on the TE side, the FA bit for every 5 frames = 1,
Identifies that it is the reception of a frame in which Q bit data should be transmitted to the NT side, and M bit = 1 for every 20 frames.
Identifies reception of the first frame of a multiframe.

In other words, in the case of multi-frame, when one M bit = 1 is detected, four F bits are detected by the next M bit = 1.
A bit=1 will be detected. In other words, if the Q-bit data to be transmitted is a 4-bit set, detecting M bit = 1 means identifying the timing to transmit the first bit data of the 4-bit Q-bit data. Become.

In order to identify the Q bit position, the conventional Q bit transmitting circuit uses a so-called FA to check that the received FA bit position is ゛゜1゜ every 5 frames.
A counter is provided, and Q-bit data is transmitted only when the counter is synchronized with FA bit=1. When it is not detected that multiframe synchronization has been established, a method is used in which Q bit="o" is transmitted.

[Problems to be Solved by the Invention] However, if multi-frame synchronization is not established as described above, if a method is adopted in which Q bit = "O" is transmitted, the problem shown in FIGS. 4A and 4B will occur. The inventor has discovered that such problems can occur.

Consider a point-to-multipoint connection (a case where a plurality of TEs 2 and 3 are connected to one NTI) as shown in FIGS. 4A and 4B. As shown in FIG. 4A, it is assumed that one TE2 has already established multi-frame synchronization (hereinafter referred to as rFA bit synchronization) and is transmitting Q-bit data. At this time, as shown in Figure 4B,
When another TE3 connected to the bus is powered on and starts its device, that TE3 will transmit the Q bit = “O” until FA bit synchronization is established, and the TE3 that has already been This will prevent Q-bit data transmission.

This means that in the line, the value "O" is a pulse state, and when multiple TEs are connected to the bus, the signal "O"
” and “1” collide, “O” will be detected on the bus.

According to the present invention, when multiple terminals are connected to one bus, as in the case of the above-mentioned ISDN interface, transmission frame data from a terminal that has already been synchronized with multiple frames is The present invention proposes a data communication control device that can prevent terminals that are out of frame synchronization from being destroyed until synchronization is achieved.

[Means for Solving the Problems] The configuration of the present invention for achieving the above problems is a data communication control device for a plurality of terminals connected on one bus, which transmits and receives multi-frames to and from a center, l
In a data communication control device that sends a transmission frame in which a predetermined bit position in the frame is open as a data area to a center, there is a determining means for determining whether multi-frame synchronization is established, and a determination unit that determines whether multi-frame synchronization is established. The transmitter is characterized by comprising a forming means for filling the data at the predetermined bit position with a logical value of a lower priority level on the bus to form a transmission frame.

Since the predetermined bit position in the frame sent by a terminal that is about to establish multiframe synchronization is filled with the logical value of the lower priority level, the terminal that has already established multiframe synchronization The predetermined bit position data of the transmission frame sent by the transmitter will not be destroyed.

[Embodiment] An embodiment in which the present invention is applied to a Q-bit exit device in an ISDN bus interface will be described below with reference to the accompanying drawings.

The Q bit is data that the terminal side can freely set in the bit position in the transmission frame corresponding to the FA bit position of every five received frames in the transmission and reception of multi-frames as shown in Figure 2. In the example in Figure 2, Q1
~Q4, the terminal side can send a total of 4 bits of data, 1 bit each, to the NT side. That is, the 4-bit Q-bit data is open to users for free use in the I430 recommendation.

In this embodiment, when FA synchronization is not established, the received FA bit from the NT side is sent back to the NT side at the Q bit timing of the transmission frame without transmitting Q bit = "O". , to prevent interference with Q-bit data transmission by other TEs. Then, the original Q-bit data is transmitted only after FA synchronization is established.

FIG. 1 is a block circuit diagram of this embodiment.

In the figure, signal A is a received frame signal. A circuit 101 is a circuit that decomposes a received frame,
This is a circuit that extracts the received value of the FA bit and M bit from the received frame, and the signal D is the received value of the FA bit and M bit.
This is a signal indicating that a bit has been extracted. The circuit 103 receives the FA bit=゛l'' received every 5 frames,
This circuit synchronizes with M bits=゜゛1゜' received every 20 frames and outputs a signal F for identifying a frame transmitting Q-bit data, and is called an FA/M counter circuit.

The circuit 102 is an FA bit synchronization detection circuit that determines whether the Q bit position is correctly identified.
It monitors whether the circuit 103 and the circuit 103 are synchronized over several frames, and outputs a signal E when synchronization is certainly achieved. At this point, it is assumed that "multiframe synchronization has been achieved."

Signal B is Q-bit data freely set by the user and is input to circuit 104. This circuit lO4 is the above-mentioned 4
It has a parallel-to-serial conversion function that outputs Q-bit data one bit at a time at a predetermined timing, and sends this serial bit data to the circuit 105.

The Q-bit data transmission control circuit 105 is the central part of this device, and depending on whether or not the FA bits are synchronized, it either transmits the Q-bit data set by the user or directly echoes the FA bits received from the NT side. This controls whether the data is transmitted as Q-bit data. That is, signal E
If E is "1" (FA synchronization is established), the Q bit data set by the user is sent, and if E is "0" (FA synchronization is not established), the FA received from the NT side.
The bits are sent out as they are as Q-bit data. This situation is shown in FIG.

In FIG. 5, the terminal TE2, which has already achieved FA bit synchronization, uses the Q bit transmission timing set by itself as the Q bit transmission timing.
The FA that has just been started is sending out bit data.
The terminal 3, for which bit synchronization has not been established, sends out the FA bit received from the NT side as Q-bit data, like an echo.

In this way, Q=1 is sent from the terminal 3 that has just started up at the Q bit timing of every 4 frames. As mentioned above, the logical value “l” indicates the ISDN
Since the priority level is low on the interface bus, the Q data from terminal 2 with which synchronization has been previously established reaches the NT side without being destroyed.

FIG. 6 shows a time chart of the operation of the terminal 3 in FIG. 5.

The circuit 101 samples the FA bit and M bit from the signal A and outputs the signal D. In signal D in FIG. 6, the upper part shows the FA bit extraction signal, and the lower part shows the M bit extraction signal. In this example, the FA bit is ゜゜1゜゜ every 5 frames, and the M bit is ゛゜l゜゜ every 20 frames, indicating a multi-frame configuration.

The circuit 103 is synchronized with the signal D, and outputs the signal F=“l” when the count value of the FA counter is ゛゜4゜.

This signal F=“1” represents a frame in which Q bits are transmitted. Circuit 102 connects signal D and circuit 10
When synchronization is achieved, signal E is output.

In the example of FIG. 6, terminal 3 continues to operate F until signal E is output.
A bit = “4 1° are received.

Signal B, which is Q-bit data, is a timing signal that is output when the count value of circuit 103 is FA counter = 4 and M counter = 2, and is loaded into circuit 104. Then, from the circuit 104, the FA counter transmits Q bit data one bit every five frames to the control circuit 105.
(signal G).

The circuit 105 includes the outputs of the circuits 102 to 104 and the signal D.
The FA bit extraction signal is manually input.

When the signal E is not output, that is, when the FA bits are not synchronized, the circuit 105 outputs the signal D as is, and when the signal E is output, that is, when the FA bits are synchronized, the circuit 105 outputs the signal D as is. , the signal G is output at the timing of the signal F.

The present invention can be modified in various ways without departing from the spirit thereof.

In the above embodiment, the present invention has been explained as an example in which the present invention is applied to ISDN. , is applicable to any bus interface. Therefore, this area of the invention is not limited to the Q-bit area. Also,
The present invention can also be applied to a bus interface in which there is a priority level for either ゜゛1゜゜ or "O" on the bus.

[Effects of the Invention] As explained above, the data communication control device of the present invention has the following effects:
When applied to multiple terminals connected to one bus, such as transmitting and receiving multi-frames to and from the center, and sending frames with predetermined bit positions in one frame open as data areas to the center. , a determining means for determining the establishment of multi-frame synchronization; and a determining means for determining the establishment of multi-frame synchronization; Since the terminal is equipped with a forming means for filling in and forming a transmission frame, a logical value of the lower priority level is set at a predetermined bit position in a frame sent by a terminal that is about to establish multi-frame synchronization. Therefore, the predetermined bit position data of the transmission frame sent by the terminal with which multi-frame synchronization has already been established will not be destroyed.

In particular, according to the third aspect of the invention, when applied to an ISDN bus interface, the FA bit sent from the center side is sent as Q-bit data as is until multi-frame synchronization is established.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a Q-bit transmission circuit in an embodiment in which the present invention is applied to ISDN, Fig. 2 is a diagram illustrating an overview of the multi-frame configuration and Q-bit position identification, and Fig. 3 is an explanation of an interface in ISDN. Figures 4A and 4B are diagrams explaining the problems of the conventional example, Figure 5 is a diagram explaining the outline of the operation of the embodiment device shown in Figure 1, and Figure 6 is a diagram explaining the operation of the present embodiment. This is a timing chart. In the figure, 1 O 1 ... Frame decomposition circuit 1 O 2 ... FA bit peer detection circuit l 03 ... FA, M bit counter circuit O4 ... Q bit data transmission section 05 ... Q bit data Control circuit A... Reception frame signal B... Q bit data signal (parallel) C... Transmission Q bit signal D... Reception FA bit, M bit signal E... FA bit synchronization detection signal

Claims (3)

[Claims] (1) A data communication control device for multiple terminals connected on one bus, which transmits and receives multi-frames to and from the center, and transmits frames in which a predetermined bit position within one frame is open as a data area. In the data communication control device that sends the data to the center, there is a determining means for determining whether multi-frame synchronization has been established; forming means for forming a transmission frame by filling it with the lower logical value of the data communication control device. (2) The data communication control device according to claim 1, wherein the data communication control device is connected to an ISDN bus interface, and the logical value of the lower priority level is "1". Device. (3) The predetermined bit position is the Q bit in the ISDN interface, the data communication control device has detection means for detecting the FA bit in the frame received from the center, and the forming means According to claim 2, the same logical value as the FA bit of the received frame is inserted into the Q bit position of the transmitted frame until it is determined that the multi-frame synchronization is established after the synchronization is established. The data communication control device described.