JPH05324545A - Bus controller - Google Patents

Abstract

PURPOSE:To provide the bus controller which easily realizes initial connection procedures of broadcast. CONSTITUTION:A bus controller 1 on the transmission side is provided with a group address encoding circuit 2 which encodes a group address to output it to a data bus, a device address encoding circuit 3 which encodes a device address to output it to the data bus, and a control circuit 4 which shakes hands with the reception side through the data bus. A bus controller 5 on the reception side is provided with a group address decoder 6 which takes in the group address from the data bus to discriminate whether the group address coincides with the group to which the device belongs or not, a device address decoder 7 which decodes the device address, and a control circuit 8 which shakes hands with the transmission side through the data bus. Thus, addresses can be transferred to plural devices on the reception by one handshake even in the case of broadcast, and the increase of overhead of a parallel data transfer bus and the degradation of throughput are suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus controller for a digital data transfer path.

[0002]

2. Description of the Related Art A conventional structure of a bus control device in a parallel data transfer bus will be described with reference to FIG. In the figure, the parallel data transfer bus 42 includes a data signal line 41 for transmitting a device address signal and a data signal, a strobe signal line 38 for transmitting a strobe signal indicating that the data signal is valid, and preparation for receiving data is completed. On the data signal 41, the ready signal line 39 for transmitting the ready signal for notifying the transmitting side that the reception side has transmitted, the acknowledge signal line 40 for transmitting the acknowledge signal for notifying the transmitting side of the completion of the data reception Is formed by a device address / data identification signal line 37 or the like that transmits a device address / data identification signal indicating whether a device address signal is output or a data signal is output. In this data transfer bus 42, when the device address / data identification signal is at "L" level, the address signal of the device that should receive the data is output to the data signal line 41, and the device address / data identification signal is " When it is at H level, it means that a data signal is input / output.

The bus control device 30 on the transmitting side, which sends out various signals to the parallel data transfer bus 42, performs a handshake of the device address and data with a device address encoding circuit 31 which encodes the device address of the receiving device to which the data is to be sent. The control circuit 32 is provided for the reception side. The bus controller 33 on the receiving side, which takes in various signals from the parallel data transfer bus 42, has a device address decoding circuit 35 which decodes a device address signal from the data signal line 41,
A control circuit 36 for handshaking device addresses and data with the transmitting side is provided.

The transfer procedure of the device address will be described with reference to FIG. In the figure, the bus control device 30 on the transmission side
After confirming that the ready signal line 39 is at the “H” level, the device address encoding circuit 31 sends a device address signal indicating the device to which the data is sent to the data signal line 4.
Send to 1. The device address / data identification signal line 37 is set to "L" level to indicate that the device address signal is transmitted, and at the same time, the strobe signal is set to "L" level to indicate that the data signal line 41 is valid. The bus control device 33 on the receiving side constantly monitors the level of the control signal line of the parallel data transfer bus 42. The bus controller 33
When it is detected that the device address / data identification signal line 37 is at "L" level and the strobe signal line 38 is at "L" level, the device address signal on the data signal line 41 is sent to the device address decoding circuit 35. Then, the control circuit 36 sets the ready signal line 39 to the “L” level. The device address decoding circuit 35 decodes the taken-in device address signal and determines whether or not the device address signal matches the preset device address of itself. If they match,
The output of the device address decoding circuit 35 is set to the "H" level to inform the control circuit 36 that the data destination has been designated. Upon completion of receiving the device address, the bus control device 33 on the receiving side sends an acknowledge signal of “H” level to the acknowledge signal line 40 of the parallel data transfer bus 42 to inform the transmitting side that the designation of the device address has been confirmed. Send out. The bus control device 30 on the transmission side is "H"
When the level acknowledge signal is received, the strobe signal line 38 is returned to the "H" level. By performing the handshake in this way, a data transmission path between the transmission side and the reception side via the parallel data transfer bus 42 is established. After this,
Data transmission is started from the transmission side.

[0005]

In a parallel processing type computer system, a multiprocessor system, etc., it is necessary to perform a broadcast in which a data signal is sent from one transmitting side device to a plurality of receiving side devices at the same time. In this case, the above-mentioned handshake for establishing a data transmission path between the transmitting side device and each receiving side device to receive the data signal is repeated by the number of the corresponding receiving devices. However, in the above-described data bus control system, the number of handshakes increases as the number of devices to be broadcast increases, and as a result, the overhead required to transfer the device address increases and the throughput decreases. Therefore, an object of the present invention is to provide a bus control device that easily realizes a handshake in broadcasting.

[0006]

To achieve the above object, a bus controller of the present invention transmits a data signal in a bus controller for controlling data transfer between a plurality of devices connected to a parallel data transfer bus. A group address decoder provided in the device for sending a group address signal indicating a plurality of devices that should simultaneously receive the data signal prior to sending the data signal, to the parallel data transfer bus;
The data signal of the device that receives the data signal is provided in the device that receives the data signal, and the group address signal is fetched from the parallel data transfer bus to determine the match with the group address held by itself. And a group address decoder that enables reception.

[0007]

According to the present invention having the above structure, the plurality of devices on the receiving side connected to the data transfer bus have the group address assigned to the device group in advance in addition to the addresses of the individual devices. The transmitting side outputs a group address indicating a group of devices to be broadcast from the encoding unit to the data transfer bus. The decoding unit of each device takes in the address generated on the bus and determines whether the address matches the group to which the device belongs. The matched device prepares to receive data. When all the applicable devices have completed the determination, it becomes possible to broadcast. As a result, it is not necessary to repeat the handshake for each device that receives data, and it is possible to prevent an increase in overhead required for device address transfer and a decrease in throughput.

[0008]

EXAMPLE An example of the present invention will be described with reference to FIG. In the figure, the bus control device includes a bus control device 1 on the transmission side, a parallel data transfer bus 20, and a bus control device 5 on the reception side. The bus control device 1 includes a group address encoding circuit 2 for transmitting a group address signal indicating a group address of a device, a device address encoding circuit 3 for transmitting a device address signal indicating a device address to a data signal line, a group address, a device address, and The control circuit 4 performs a data handshake with the receiving side. Due to the handshake, the control circuit 4 controls the device address, which indicates which of the address signal and the data signal is present on the signal line.
Output a data identification signal. In addition, the group address signal to be transmitted, the device address signal and the strobe signal indicating that the data signal is valid are transmitted to the receiving side, and the receiving side device notifies the transmitting side that the preparation for receiving the data is completed. A ready signal for notifying and an acknowledge signal for notifying the transmitting side that the data reception is completed are received from the receiving side device. The bus control device 1 sets the device address / data identification signal to the “L” level, sends at least one of the group address and the device address, sets the device address / data identification signal to the “H” level, and outputs the data. Is sent.

The parallel data transfer bus 20 includes group address signal lines 13a to 13c for transmitting the group address signal to another device, a data signal line 14 for transmitting the device address signal and the data signal to another device, and the strobe. Strobe signal line 1 for transmitting signals to other devices
0, a ready signal line 11 for transmitting a ready signal, an acknowledge signal line 12 for transmitting an acknowledge signal, and the like.

The bus control device 5 on the receiving side includes a group address decoding circuit 6, a device address decoding circuit 7 and a control circuit 8. Group address decoding circuit 6
Takes in the group address signal sent to the group address signal lines 13a to 13c, judges whether the decoded group address matches the group to which the device belongs, and gives the judgment result to the control circuit 8. The device address decoding circuit 7 takes in the device address signal transmitted through the data signal line 14, decodes it to determine whether or not it matches the device address preset in the receiving side device, and the determination result is the control circuit. Give to eight. The discrimination outputs of the group address decoding circuit 6 and the device address decoding circuit 7 are ORed and input to the control circuit 8. The control circuit 8 performs a group address, a device address, a data handshake, and the like with the transmitting side.

The structures of the data transmitting device and the data receiving device using the bus control device of the present invention will be described with reference to FIG. In the figure, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and description of such parts will be omitted. The transmitting device 21 is
The transmission side bus control device 1 and the data register 22 are provided. The receiving device 24 includes a bus controller 5 on the receiving side, a data register 23, and a bus transceiver 25. The data registers 22 and 23 are connected via the data signal line 14 of the parallel data transfer bus 20 and hold the addresses to be sent to the parallel data transfer bus 20 and the data sent from the parallel data transfer bus 20, respectively. I do. The bus transceiver 25 has an open collector output, and it is possible to take a logical product on the parallel data transfer bus 20 with respect to ready signals and acknowledge signals of a plurality of receiving devices. By the operation of taking the logical product, all the receiving devices connected to the parallel data transfer bus 20 have finished decoding the address, and the receiving device addressed is ready to take in the data to be transferred. Notify the bus controller 1 of the transmitter 21.

FIG. 3 shows the configuration of a system using this bus control device. This system includes a transmitter 21
And the receiving devices 24a to 24i are connected to each other by the parallel data transfer bus 20. For each receiving device, for example,
9 device addresses are assigned. Also, each receiving device is divided into three groups according to functions and the like.

That is, the first group receiving device 2
4a, 24b, 24c second group receiving devices 24d, 24e, 24f third group receiving devices 24g, 24h, 24i.

The operation of the group address encoding circuit 2 of the bus control device will be described with reference to Table 1.

[0015]

[Table 1] When the signal indicating the selection of the first group is given to the group address encoder circuit 2, the group address encoder circuit 2 sets only the signal line 13a of the group address signal lines 13a to 13c to "H". When a signal indicating selection of the second group is given, only the signal 13b of the group address signal lines 13a to 13c is set to "H". When a signal indicating selection of the third group is given, the signal line 13 among the group address signal lines 13a to 13c
Only c is set to "H".

The operation of the group address decoding circuits 6 of the first to third groups will be described with reference to Tables 1 to 3.

[0017]

[Table 2]

[0018]

[Table 3]

[0019]

[Table 4] The group address decoding circuit 6 provided in the receiving device of each group decodes the address signal of the group to which it belongs.

The procedure for transferring the group address signal and the device address signal will be described with reference to FIG. First, the bus control device 1 on the transmission side confirms that the ready signal line 11 is "H", and sends the group address signal from the group address encoding circuit 2 to the group address signal lines 13a ...
Output to 13c. Further, the device address signal is output from the device address encoding circuit 3 to the data signal line 14. Almost at the same time, the device address / data identification signal line 9 is set to the “L” level and the strobe signal line 10 is set to the “L” level.
Set to level.

If the device address / data identification signal line 9 and the strobe signal line 10 are both at the "L" level, the bus control device 5 on the receiving side receives the group address decoding circuit 6
To take in the group address signal indicated by the group address signal lines 13a to 13c. The device address decoding circuit 7 takes in the device address transmitted from the data signal line 14 and sets the ready signal to "L" level. The group address decoding circuit 6 determines whether the fetched group address matches the group to which the device belongs, and if they match, outputs the "H" level. Further, the device address decoding circuit 7 determines whether the taken-in device address matches the device address, and if they match, outputs the "H" level. Both outputs of the group address decoding circuit 6 and the device address decoding circuit 7 are ORed and input to the control circuit. If the output of the logical sum is "H" level, data is received. Otherwise, no data is received. That is, no data signal is taken in from the data signal line. When the bus control device 5 of each receiving device completes the reception of the group address signal and the device address signal, it sets the acknowledge signal given to the bus transceiver 25 to the “H” level. When the acknowledge signal of each receiving device is brought to the "H" level by the function of the bus transceiver 25, the acknowledge signal line 12 is set to the "H" level. The control device 1 on the transmitting side learns that all the receiving devices have completed the address discrimination when the level of the acknowledge signal line being monitored becomes "H" level, and sets the strobe signal to "H" level. Then, the transmission of the data signal is started from the transmitting device 21 side to the designated receiving device or receiving device group.

The group address signal can be used not only for designating a single device group but also for designating a plurality of device groups at the same time.

[0023]

As described above, the bus control device of the present invention includes an encoder for transmitting a group address signal indicating a group to be received to the data transfer bus prior to the transmission of the data signal, and a group from the data transfer bus. Since it has a decoding unit that takes in the address signal and confirms whether the group address matches the group to which the receiving device belongs, even when sending and receiving data in broadcast mode, a single handshake can be used to receive the transmitting device and a specific group. It is possible to establish a data transfer path with each of the side devices, and it is possible to suppress an increase in overhead required for device address transfer on the data transfer bus and prevent a decrease in throughput.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a bus control device.

FIG. 2 is a block diagram showing a configuration example of a transmitting device and a receiving device.

FIG. 3 is a block diagram showing a configuration example of a broadcast system.

FIG. 4 is a signal waveform diagram illustrating transmission / reception of a group address and a device address.

FIG. 5 is a block diagram showing a configuration example of a conventional bus control device.

FIG. 6 is a signal waveform diagram for explaining transmission and reception of a conventional device address.

[Explanation of symbols]

 1, 30 Transmission side bus control device 2 Group address encoding circuit 3, 31 Device address encoding circuit 4, 8, 32, 36 Control circuit 5, 33 Reception side bus control device 6 Group address decoding circuit 7, 35 Device address decoding circuit 9 , 37 Device address / data identification signal 20, 42 Parallel data transfer bus 21 Transmitting device 22, 23 Data register 24 Receiving device 25 Bus transceiver

Claims (1)

[Claims] 1. A bus control device for controlling data transfer between a plurality of devices connected to a parallel data transfer bus, wherein the bus control device is provided in a device that transmits a data signal, and the data is sent prior to sending the data signal. A group address decoder that sends out a group address signal indicating a plurality of devices that should receive signals at the same time to the parallel data transfer bus, and a device that receives a data signal, and is provided with the group address signal from the parallel data transfer bus. A bus control device, comprising: a group address decoder that enables a device that receives the data signal to determine a match with a group address held therein and to receive the data signal.