KR19990079974A - Apparatus for controlling delayed request between two buses in multiprocessor system and its control method - Google Patents

Abstract

The present invention relates to an apparatus for processing a delayed request between two buses in a multiprocessor system and a method of controlling the same. In particular, the first P6 bus 100 and the second P2 bus that transmits address and information processing data between processors are provided. A P6 bus 200; A queue unit 300 which temporarily stores address and information processing data; When the address and information processing data are transmitted from the first P6 bus 100 to the second P6 bus 200, when a delay signal occurs to the second P6 bus 200, the address and information data are read and stored. A delay-request queue unit 400; An address stored in the delay-request queue unit 400 in the case of a transferable state after determining the transferable state of the second P6 bus 200 by the transfer processing request signal output from the delay-request queue unit 400; And a delay-request controller 500 for transmitting information processing data to the second P6 bus 200. The present invention connects two P6 buses to which a plurality of Pentium Pro processors are connected. When the information processing data is transferred from one P6 bus to another P6 bus, even if a delay condition occurs, the data transfer process is smoothed by controlling the information processing data to be transmitted after the delay state is finished. A multiprocessing system that combines two P6 buses can be implemented, which not only increases data throughput but also extends the Pentium Pro processor. That there is an effect.

Description

Apparatus for controlling delayed request between two buses in multiprocessor system and its control method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and in particular, connects two P6 buses, each connected with a plurality of Pentium Pro processors, from one P6 bus to another P6 bus. When transmitting information processing data, it is possible to control the information processing data to be transmitted after the delay state is terminated even if a delay occurs, so that it is possible to implement a multiprocessing system combining two P6 buses. The present invention relates to an apparatus for handling a delayed request between two buses and a control method thereof.

The system using the Pentium Pro provided by Intel can only support up to four Pentium Pro processors on one P6 bus due to the electrical characteristics, and two P6 buses to connect eight Pentium Pro processors. If there was a delay in one of the two P6 buses, there was no device to handle it, so it was not able to support eight Pentium Pro processors, which reduced the scalability. There was a slowing problem.

The present invention is to solve the above-mentioned conventional problems, each of which a plurality of Pentium Pro processor is connected to the two P6 bus connected, and the delay state when transmitting information processing data from one P6 bus to another P6 bus, Handles delayed requests between two buses in a multiprocessor system that enables a multiprocessing system that combines two P6 buses to control the transfer of information processing data after a delay is terminated even if To provide an apparatus and a control method for the same.

In order to achieve the above object, an apparatus for processing a delayed request between two buses in a multiprocessor system of the present invention may be connected to a plurality of processors to transfer an address and information processing data between processors. Wow; A second P6 bus connected to a plurality of processors and the first P6 bus to transmit address and information processing data between the processors; A queue connected to the first P6 bus and the second P6 bus to temporarily store address and information processing data transferred from the first P6 bus to the second P6 bus or the second P6 bus to the first P6 bus. (Queue) section; It is connected to the signal output terminal of the second P6 bus and the queue section, and has an entry for storing a plurality of addresses and information processing data, and the address and information processing data on the first P6 bus. Is transmitted to the second P6 bus, when a delay signal occurs on the second P6 bus, reads and stores the address and information data stored in the queue unit, and outputs a transmission process request signal. A Defer-Reply cue portion; Connected to the signal output terminals of the first P6 bus, the second P6 bus, and the delay-request queue portion, and grasping the transferable state of the second P6 bus by the transfer processing request signal output from the delay-request queue portion; And a delay-request control unit for transmitting the address and information processing data stored in the delay-request queue unit to the second P6 bus when the transmission is possible.

In addition, in the multiprocessor system of the present invention, a control method of an apparatus for processing a delay between two buses includes: a first outputting address and information processing data to a first P6 bus from a processor connected to a first P6 bus; Step S1; A second step (S2) of determining whether it is necessary to transfer the address and information processing data generated on the first P6 bus to the second P6 bus after the first step (S1); After the second step S2, if there is no need to transfer the address and information processing data generated on the first P6 bus to the second P6 bus, the information processing data is transmitted to the corresponding processor connected to the first P6 bus. Giving a third step (S3); After the second step S2, if it is necessary to transfer the address and information processing data generated on the first P6 bus to the second P6 bus, the fourth step of transmitting the address and information processing data to the second P6 bus ( S4); A fifth step S5 of determining whether a delay signal has occurred on the second P6 bus after the fourth step S4; A sixth step (S6) of transmitting information processing data to a processor connected to the second P6 bus when a delay signal does not occur on the second P6 bus after the fifth step (S5); After the fifth step S5, when a delay signal is generated on the second P6 bus, a seventh step S7 of reading and storing the address and information processing data temporarily stored in the queue unit in the delay-request queue unit Wow; An eighth step (S8) of outputting a transfer processing request signal to the delay-request control unit after the seventh step (S7); A ninth step (S9) of determining whether a transmission state of the second P6 bus is possible after the eighth step (S8), and performing the eighth step (S8) if the transmission state is not possible; After the ninth step (S9), it is characterized in that it comprises a tenth step (S10) for transmitting the address and information processing data to the second P6 bus when the transmission state of the second P6 bus is possible.

1 is a functional block diagram showing a configuration of an apparatus for processing a delayed request between two buses in a multiprocessor system according to an embodiment of the present invention;

2 is a control flowchart illustrating an operation of an apparatus for processing a delayed request between two buses in the multiprocessor system according to FIG. 1.

<Explanation of symbols for the main parts of the drawings>

100: first P6 bus 200: second P6 bus

300: cue part 400: delay-request cue part

500: delay-request control unit

Hereinafter, the above-described contents will be described in detail through an embodiment according to the present invention.

As shown in FIG. 1, the first P6 bus 100 transmits address and information processing data between processors, and the second P6 bus 200 is connected to the first P6 bus 100. The processor transmits the address and information processing data between the processors, and the queue unit 300 temporarily stores the address and information processing data transmitted from the first P6 bus 100 to the second P6 bus 200.

In addition, the delay-request queue unit 400 having an entry capable of storing a plurality of addresses and information processing data transmits the address and information processing data from the first P6 bus 100 to the second P6 bus 200. When a delay signal occurs on the second P6 bus 200, the address and information data stored in the queue unit 300 are read and stored, and the delay request controller 500 stores the transmission process request signal. Will output

On the other hand, the delay-request control unit 500, after determining the transmission possible state of the second P6 bus 200 by the transmission processing request signal output from the delay-request queue unit 400, and when the transmission possible state The present embodiment is constructed by transmitting the address and information processing data stored in the delay-request queue unit 400 to the second P6 bus 200.

Hereinafter, an operation process of an apparatus for processing a delayed request between two buses in a multiprocessor system configured as described above will be described with reference to FIGS. 1 and 2.

First, when the processor connected to the first P6 bus 100 outputs address and information processing data (S1), the address and information processing data generated on the first P6 bus 100 may be converted into a second P6 bus ( It is determined whether it is necessary to transmit to 200 (S2).

In addition, it is determined whether the address and information processing data generated on the first P6 bus 100 need to be transmitted to the second P6 bus 200 (S2), and thus the address generated on the first P6 bus 100 is determined. When it is not necessary to transmit the information processing data to the second P6 bus 200, the information processing data is transmitted to the processor corresponding to the address (S3).

On the other hand, it is determined whether the address and information processing data generated on the first P6 bus 100 need to be transmitted to the second P6 bus 200 (S2), and thus the address generated on the first P6 bus 100 is determined. If it is necessary to transmit the information processing data to the second P6 bus 200, the address and the information processing data are transmitted to the second P6 bus 200 (S4).

In addition, the queue unit 300 temporarily stores the address and information processing data transmitted from the first P6 bus 100 to the second P6 bus 200.

However, after the address and information processing data are transmitted from the first P6 bus 100 to the second P6 bus 200, it is determined whether a delay signal has occurred on the second P6 bus 200 (S5). .

On the other hand, it is determined whether a delay signal is generated on the second P6 bus 200 (S5), and when the delay signal does not occur on the second P6 bus 200, the second P6 bus 200 Information processing data is transmitted to the connected processor (S6).

In this case, it is determined whether a delay signal is generated on the second P6 bus 200 (S5), and when a delay signal is generated on the second P6 bus 200, the delay-request queue unit 400 is determined. The address and information data stored in the queue unit 300 are read and stored (S7).

In addition, the delay-request queue unit 400 may store a plurality of addresses and information processing data whose processing operation is delayed due to having an entry.

On the other hand, after the delay-request queue unit 400 stores the address and information processing data, the delay-request queue unit 400 continuously outputs the transmission process request signal to the delay-request control unit 500 (S8).

Then, the delay-request controller 500 determines the transmittable state of the second P6 bus 200 based on the transmission process request signal output from the delay-request queue unit 400 (S9).

In addition, the delay-request control unit 500 checks the transmittable state of the second P6 bus 200 and then stores the address and information processing data stored in the delay-request queue unit 400 in the transmittable state. It transmits to the second P6 bus 200 (S10).

On the other hand, the second P6 bus 200 inputs the address and information processing data transmitted through the delay-request control unit 500, and transmits the information processing data to the processor corresponding to the address.

Therefore, when address and information processing data are transmitted from the first P6 bus 100 to the second P6 bus 200, even if a delay condition occurs, the delay condition is controlled by the control operation of the delay-request controller 500. By transmitting the address and information processing data after completion, the data transfer processing is smoothed, so that a multi-processing system in which two P6 buses are combined can be implemented.

As described above, in the multiprocessor system of the present invention, an apparatus for processing a delayed request between two buses and a method of controlling the same are connected to two P6 buses each connected with a plurality of Pentium Pro processors, and one P6 bus. Transfers information processing data from one P6 bus to another P6 bus, even if a delay occurs, controlling the data to be transmitted after the delay is terminated, thereby facilitating the data transfer process. Processing systems can be implemented, which not only increases data throughput, but also extends and supports the Pentium Pro processor.

Claims (2)

A first P6 bus, connected to a plurality of processors, for transmitting address and information processing data between the processors; A second P6 bus connected to a plurality of processors and the first P6 bus to transmit address and information processing data between the processors; A queue unit connected to the first P6 bus and the second P6 bus and temporarily storing address and information processing data transferred from the first P6 bus to the second P6 bus or the second P6 bus to the first P6 bus; Wow; Is connected to the signal output terminal of the second P6 bus and the queue section, and has an entry for storing a plurality of addresses and information processing data, and when transmitting address and information processing data from the first P6 bus to the second P6 bus. A delay-request queue section for reading and storing address and information data stored in the queue section and outputting a transmission processing request signal when a delay signal occurs on the second P6 bus; Connected to the signal output terminals of the first P6 bus, the second P6 bus, and the delay-request queue portion, and grasping the transferable state of the second P6 bus by the transfer processing request signal output from the delay-request queue portion; In the multi-processor system characterized in that it comprises a delay-request control unit for transmitting the address and information processing data stored in the delay-request queue unit to the second P6 bus when the transmission possible state; Device for handling delayed requests. A first step S1 of outputting address and information processing data to a first P6 bus from a processor connected to the first P6 bus; A second step (S2) of determining whether it is necessary to transfer the address and information processing data generated on the first P6 bus to the second P6 bus after the first step (S1); After the second step S2, if there is no need to transfer the address and information processing data generated on the first P6 bus to the second P6 bus, the information processing data is transmitted to the corresponding processor connected to the first P6 bus. Giving a third step (S3); After the second step S2, if it is necessary to transfer the address and information processing data generated on the first P6 bus to the second P6 bus, the fourth step of transmitting the address and information processing data to the second P6 bus ( S4); A fifth step S5 of determining whether a delay signal has occurred on the second P6 bus after the fourth step S4; A sixth step (S6) of transmitting information processing data to a processor connected to the second P6 bus when a delay signal does not occur on the second P6 bus after the fifth step (S5); After the fifth step S5, when a delay signal is generated on the second P6 bus, a seventh step S7 of reading and storing the address and information processing data temporarily stored in the queue unit in the delay-request queue unit Wow; An eighth step (S8) of outputting a transfer processing request signal to the delay-request control unit after the seventh step (S7); A ninth step (S9) of determining whether a transmission state of the second P6 bus is possible after the eighth step (S8), and performing the eighth step (S8) if the transmission state is not possible; And a tenth step (S10) for transmitting address and information processing data to the second P6 bus when the second P6 bus is available for transmission after the ninth step (S9). A method for controlling a device for handling a delayed request between two buses in a network.