JP3270040B2 - Bus control method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control system, and more particularly to a bus control system for an information processing apparatus.

[Conventional technology]

Conventionally, in such an information processing apparatus, only one cycle can be performed at a time due to the structure of a bus, and a data transfer cycle and an interrupt control cycle are separated, and each cycle is performed exclusively. .

Also, when data is exchanged with the peripheral device by DMA, the width of data handled by the peripheral device in one cycle is smaller than the width of data handled by the central processing unit.

[Problems to be solved by the invention]

In the conventional method described above, when data is being exchanged with peripheral devices by DMA, data is not transmitted using the entire data width of the bus. Only effective use of resources was not achieved.

Also, since the central processing unit cannot use the bus during that time, it simply waits for the bus to open without doing anything.

[Means for solving the problem]

The bus control method according to the present invention is an information transmission path (hereinafter, referred to as a bus) used for an information processing apparatus, wherein the bus is divided into two upper and lower data buses having the same data width; The first and second address buses have a function of exchanging information of the upper and lower two data buses.
A central processing unit having a function of performing interrupt control using a higher-order data bus even when a direct memory access (hereinafter referred to as DMA) operation is being performed externally; A first storage device for storing a program or data for operating a processing device, and a second storage device for storing information for interrupt processing of the central processing unit and capable of extracting information independently of the first storage device A peripheral circuit having a function of sending an interrupt request signal to the central processing unit and providing the central processing unit with factor information for interrupt processing of the central processing unit;
A peripheral device control circuit for controlling peripheral devices connected to the information processing apparatus; a DMA control circuit for transmitting and receiving data in a DMA system between the peripheral device control circuit and the first storage device; The output address of the device is
A fourth switching circuit having a function of switching to flow to one of the storage device and the address bus, and a bus control circuit controlling the first, second, third, and fourth switching circuits, The central processing unit is connected to the address bus via the fourth switching circuit, the first storage device is connected to the address bus via the first switching circuit, and the second storage device is The data bus is connected via a third switching circuit, and the peripheral circuit is connected to the data bus via the second switching circuit.

〔Example〕

An embodiment of the present invention will be described with reference to FIG.

Here, this system has a 32-bit data bus. When the central processing unit of this system transfers data, upper and lower 32-bit data is transferred between the first storage device 105 and the peripheral circuit 102 using the lower data bus 202 and the upper data bus 203. Do, DMA
Sometimes, data is exchanged with the first storage device 105 using the lower 16-bit lower data bus 202, and when the interrupt factor information of the central processing unit 101 and the vector are received, the lower data bus 202 is normally used. Data transfer.

When the DMA transfer is performed in the system shown in FIG. 1, the DMA control circuit 103 outputs a hold request signal to the central processing unit 101 to the hold request signal line 206. On the other hand, the central processing unit 101 outputs a hold request permission signal to the hold request permission signal line 207. When this signal is received by the DMA control circuit 103, the operation of DMA is started, an address to the first storage device 105 is output to the address bus 201, and the address is transmitted to the peripheral device control circuit 104 and the storage device 105. Is sent to the DMA control line 208. By receiving this control signal, the peripheral device control circuit 104 and the first storage device 105 transfer data using the lower data bus 202.

When receiving the hold permission signal from the central processing unit 101, the bus control circuit 106 switches the switching circuits 107, 112, 11
A control signal is sent to the DMA control line 208 with respect to 0, 111, and the switching circuit 107 switches the first storage device in accordance with the DMA transfer address.
The data bus connected to 105 is divided into upper and lower
The second switching circuit 112 and the third switching circuit 111 can switch the data bus between the upper and lower data buses, and
The second storage device 109 and the peripheral circuit 102 are connected to 203, and the fourth switching circuit 110 switches the address line of the central processing unit 101 to the second storage device 109.

Here, when an interrupt request is input from the peripheral circuit 102 having the interrupt factor to the central processing unit 101 using the interrupt request signal line 204, the central processing unit 101 outputs a response signal to the interrupt to the interrupt response signal line 205. At the same time, the interrupt factor information is taken. At this time,
The transfer of the factor information is performed using the upper data bus 203.

The central processing unit 101 reads the jump destination address stored in the second storage device 109 based on the received factor information, and performs the next process for the interrupt at the same time as the completion of the DMA transfer. .

〔The invention's effect〕

As described above, by providing the central processing unit with the function of performing interrupt control even during hold, and by making the data bus of the bus connecting the central processing unit switchable, it can be used even during DMA cycles. At the same time as the bus which has not been used can be used effectively, the processing by the interrupt can be started at the same time as the end of the DMA cycle.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. 101 central processing unit, 102 peripheral circuit, 103 DNA control circuit, 104 peripheral device control circuit, 105 first storage device, 106 bus control circuit, 107 first Switching circuit, 109: second storage device, 110: fourth switching circuit, 111: third switching circuit, 112: second switching circuit, 201: address bus, 202: lower data Bus 203, upper data bus 204 interrupt request signal line 205 interrupt response signal line 206 hold request signal line 207 hold response signal line 208 DMA control line.

Continuation of front page (56) References JP-A-1-248264 (JP, A) JP-A-2-181251 (JP, A) JP-A-63-5455 (JP, A) JP-A-1-319850 (JP, A) JP-A-61-175750 (JP, A) JP-A-2-6353 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 13/16, 13/28 G06F 13 / 32,13 / 36

Claims (1)

(57) [Claims] An information transmission path (hereinafter, referred to as a bus) used in an information processing apparatus, wherein said bus is a data bus which can be divided into two upper and lower data buses having the same data width, and an address bus. A first, a second, and a third switching circuit having a function of exchanging information of the upper and lower two data buses, and interrupt control even during an external direct memory access (hereinafter referred to as DMA) operation. A central processing unit having a function that can be performed by using an upper data bus; a first storage device for storing a program and data for operating the central processing unit; and information for interrupt processing of the central processing device. A second storage device capable of extracting information for the interrupt processing independently of the first storage device, and an interrupt request signal to the central processing device. A peripheral circuit having a function of providing factor information for interrupt processing of the central processing unit to the central processing unit, a peripheral device control circuit for controlling peripheral devices connected to the information processing device, and the peripheral device control circuit; A DMA control circuit for transmitting and receiving data to and from the first storage device according to a DMA method, and an address output from the central processing unit flowing to one of the second storage device and the address bus. A fourth switching circuit having a switching function; and a bus control circuit for controlling the first, second, third, and fourth switching circuits, wherein the central processing unit controls an address bus via the fourth switching circuit. , The first storage device is connected to the address bus via the first switching circuit, and the second storage device is connected to the data bus via the third switching circuit. Connected to said peripheral circuit bus control method characterized by comprising connected to the data bus via the second switching circuit.