JPS61105662A - Direct memory access unit and data transfer unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to improvements in direct memory access (DMA) devices.

〔overview〕

The present invention provides a DMA device that performs high-speed data transfer between a storage device and a transmission circuit, in which a buffer means for storing data is provided between the storage device and the transmission circuit, and the data is transferred between the buffer means and the storage device. After transmission is completed, the right to use the system bus (address bus and data bus) is returned to the central processing unit, thereby minimizing the use of the system bus by the DMA device and increasing the processing efficiency of the central processing unit. .

[Conventional technology]

Many data processing environments require a central processing unit, such as a microprocessor, to receive data, process the data, and transmit or further process the resulting data.

Typically, the central processing unit is connected to a storage device that can be accessed via an address bus and a data bus. These buses, combined with control lines, are collectively called a system bus. The amount of processing that can be performed by a central processing unit is limited by the time required for the central processing unit to execute each instruction and the time that processing is stalled due to data transfer.

2. Description of the Related Art Direct memory access (DMA) technology is known as a technique for transferring data at high speed, in which data is transferred directly to and from a storage device without a command from a central processing unit.

A device that performs direct memory access is called a DMA device.

□ [Problem to be solved by the invention] However, in the conventional DMA device, while direct memory access is being executed, the DMA device controls the system bus, so the central processing unit cannot access the storage device. This has the drawback of causing loss of program execution time.

This is particularly noticeable when data is transferred using a relatively low-speed transmission circuit.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved DMA device so that system bus usage is minimized.

[Means for solving problems]

The DMA device of the present invention is connected to a system bus including an address bus and a data bus connecting a storage device and a central processing unit, and has an address port connected to the address bus and a data port connected to the data bus. a direct memory access device comprising: a transmission port connected to a transmission circuit; and means for transferring data between the storage device and the transmission circuit, the means for transferring data comprising a buffer means; means for transferring data between said data port and said buffer means; and means for transferring data between said transmission port and said buffer means; The present invention is characterized by comprising control means for returning control of the system bus to the central processing unit when there is no data to be transferred between the data port and the buffer means.

Preferably, the control means detects an interval during which the processing unit does not request use of the system bus, and requests use of the system bus during this time. This process is a cycle steal (cy
cle steering).

The DMA device can also perform data transfer to or from the storage device, and the buffer means includes an output buffer for transferring data from the storage device to the transmission circuit;
It is desirable to include an input buffer for transferring data from the transmission circuit to the storage device. Each buffer is configured with a first-in, first-out storage device, and each buffer is preferably capable of storing one word of data.

Furthermore, it is preferred that the DMA device includes programmable means for successively transferring words between said buffer and a plurality of storage locations of said storage device.

A data transfer device can be constructed by using the DMA device of the present invention together with a central processing unit, a storage device, and a transmission circuit.

[Effect]

The DMA device of the present invention includes a buffer means between the storage device and the transmission circuit, and when the data transfer between the storage device and the buffer means is completed, the use of the system bus is terminated and its control is centrally controlled. Return to processing unit. therefore,
Even when using a low-speed transmission circuit, system bus usage time can be reduced.

〔Example〕

FIG. 1 is a block diagram of a DMA device according to an embodiment of the present invention.

The DMA device 10 includes a control port 20 for connection to a control bus, an address port 21 for connection to an address bus, and a data port 22 for connection to a data bus 4. Inside the DMA device 10, there are a control port 20, an address port 21, and a data port 2.
2 are a device control bus 23 and a device address bus 2, respectively.
4 and device data bus 25.

Device data bus 25 is connected to a buffer circuit 26 comprised of a 1-byte output buffer 27 and a 1-byte input buffer 28. Output buffer 27 and input buffer 28 are connected to internal bus 29 and transmission port 3.
It is connected to the transmission bus via 0.

If a larger buffer circuit is required, output buffer 27 and input buffer 28 are made larger.

Figure 2 shows the central processing unit 50, transmission circuit 51 and DMA.
1 is a block diagram of a data transfer device including a device 10; FIG.

DMA device 10 is connected between central processing unit 50 and transmission circuit 51. The central processing unit 50 communicates using a system bus composed of a system control bus 52, a system address bus 53, and a system data bus 54. The address bus 53 and the data bus 54 are connected to a storage device 55, and data information is transferred between the central processing unit 50 and the storage device 55 by the data bus 54.
Address information is transferred from the central processing unit 50 to the address bus 53.
The data is supplied to the storage device 55 via. DMA device 10
causes the transmission circuit 51 to perform direct memory access via the transmission bus 56. Status information can also be transferred between transmission circuit 51 and DMA device 10 via transmission control bus 57.

During data transfer from the storage device 55 to the transmission circuit 51, D
MA device 10 transfers data byte by byte from storage device 55 to output buffer 27 using the system bus.

This transfer is performed very quickly at times when central processing unit 50 does not require the system bus. When data information in units of hepatites is transferred from the output buffer 27 to the transmission circuit 51, control of the system bus is returned to the central processing unit.

The DMA device 10 includes a central processing unit 50 or a transmission circuit 5.
Data transfer can be performed in response to a request from either one. Furthermore, multiple bytes of data information can be transferred between the transmission circuit 51 and the storage device 55 under program control of the central processing unit 50. When the transmission circuit requests data transfer, the DMA device 10 generates an interrupt signal, and this signal is supplied to the central processing unit 50 via a control signal. The central processing unit 50 is a DMA
Control is transferred to a subroutine that programmatically controls the device 10, allowing the transmission circuit 51 to transfer data.

Let's return to Figure 1. The device control bus 23 is connected to the control circuit 31
connected to. Control circuit 31 is also connected to device transmission control bus 32 . Device transmission control bus 32 is connected to transmission control bus 57 via transmission control port 33 . The control circuit 31 receives and transmits control signals via the device control bus 23 and device transmission control bus 32, and performs DMA processing.
Operation of the DMA device 10 is monitored by providing enable signals to other circuits within the device 10.

While operating under program control, the central processing unit 5
0 recognizes the circuit within the DMA device 10 using the three signal lines of the address bus used for transfer operations.

Address information associated with the DMA device 10 is latched by a decoder circuit 34 connected to the device address bus. The control circuit 31 then supplies an enable signal to the circuit recognized by the decoder 34.

Address information for transferring data from the storage device 55 is generated by the first programmable circuit 35,
Address information for data transfer to the storage device is generated by the second programmable circuit 36. Each programming circuit 35 . The address pointer 37 receives and receives two consecutive bytes of information from the central processing unit 50 via the system data bus 54 and the device data bus 25 to be read (first programmable circuit 35) or written (first programmable circuit 35). 2. Programmable circuit 36) The first memory location is stored. Before receiving the above 2-byte information, the address pointer 37
Code must be provided to the device address bus 24 to enable the desired address pointer 37 so that the device data bus 25 can receive data information from the device data bus 25.

The device data bus 25 also includes programmable circuits 35.
36 respective address registers 38.

These address registers 38 store values indicating the number of data information to be transferred. Address register 38 also receives an enable signal from control circuit 31. During data transfer between the buffer circuit 26 and the storage device 55, the address register 38 transfers its stored value to the device address bus 24 in response to a second enable signal from the control circuit 31. supply to. The interval between the second enable signals is ideally the minimum value required to continuously perform data transfer between the storage device 55 and the buffer circuit 26. When the transfer is completed, the control circuit 31 sends an increment signal to the address pointer 3.
7 and counter 39. At this time, the address pointer 37 increases the value of the stored address, and the counter 39 is incremented to count the number of transfers. Once the programmable circuits 35,36 are set, the counter 39 is reset in response to a signal from the control circuit 31. Address register 38 and counter 39 continuously provide outputs to digital comparator 40. The digital comparator 40 outputs a signal to the control circuit 31 when the transfer of the desired amount of information is completed.

The DMA device 10 complies with CCITT Recommendation X25 and therefore 8
It is useful for use in packet switching networks that collect a predetermined number of octets made up of bits and transmit them as one packet. The central processing unit 50 (eg, a 280 microprocessor) has an input/output processor (hereinafter referred to as I10) that checks packets for errors and requests retransmission of collided data.
(referred to as a processor). I10
The processor verifies that the packets are transmitted in the correct order before passing the input packets to the active switching circuitry or passing the output packets to the transmission circuitry. The transmission circuit uses Sidanetics 2652 (si
genetics 2652) chip. This chip is a CCITT Recommendation χ25 level 1 interface, ie, a synchronous link where synchronization is maintained by the generating flag when no packets are being transmitted.

The operation of such a device will be explained. Signetics 26
The 52 chip receives the first octet of a packet requesting transmission to the central processing unit 50 from an external signal line. While the central processing unit 50 is processing the previously supplied packet, there is space in its storage to replace it with the next packet. The Signetics 2652 chip provides a data wait signal to the transmission control port 33;
The control circuit 31 requests an interrupt from the central processing unit 50. The central processing unit 50 processes this interrupt and sets the second programmable circuit 36 under program control. This allows new data information to be written into the waiting space of the storage device 55.

The address pointer 37 stores the first location of the available storage area, and the address register 38 stores the first location of the available storage area.
0 stores the expected number of transferred octets. When the address pointer 37 and address buster 38 are set, the central processing unit 50 ends the interrupt processing and returns to the original control, and the DMA device 10 executes data transfer.

Here, the DMA device 10 sends a transmission data signal to the Signetics 2652 chip via the transmission control port 33. This chip sends one octet to input buffer 28 via transmission port 30. Once this transfer is complete, control circuit 31 waits the time necessary to write the octet to storage device 55. The control circuit 31 monitors the system address bus 53 via its decoder circuit 34, and the central processing unit 50 monitors the system address bus 53 via its decoder circuit 34.
Detects that an instruction has been fetched from 5. After fetching, central processing unit 50 does not use the system bus, so this time is ideal for performing accesses to storage device 55. This is a process known as cycle stealing.

After the octet is transferred from input buffer 28 to storage 55, address pointer 37 is incremented and the process of transferring the octet from the Signets 2652 chip is repeated. This process continues until a complete bucket has been transferred and the value stored in counter 39 of programmable circuit 36 is equal to the value stored in address register 38. When these values are equal, the Signetaix 2652 chip outputs a request to send data, requests a second interrupt from the central processing unit 50, and sets the programmable circuit 36.

Data transfer to the Sidanetics 2652 chip can be similarly performed using the first programmable circuit 35 and the converter 27.

During data transfer between the buffer circuit 26 and the storage device 55, the DMA device 10 controls the system address bus 53 and the system data bus 54, while controlling the data ports and The address port is tri-stated. To make this setting, the control circuit 31 supplies a signal to a bus request terminal of the central processing unit 50 connected to the system control bus 52. The central processing unit 50 is connected to the system address bus 5.
3 and system data bus 54, the DM
Returns the bus acknowledge signal to the A device 10 and performs the DMA
Data port 22 and address port 21 of device 10
Make it tristate.

FIG. 3 is a block configuration diagram showing an example of a configuration for multiple transmission devices to access the same storage device.

In this example, three DMA devices 10A, IOB and 10C can access the same storage device 65. The access priority of each DMA device 10A, IOB, and IOC is determined by the physical wiring of the bus request signal and bus acknowledge signal lines. In the example of FIG. 3, three DMA devices 10A, 10B and 10
C is connected to the system bus of the central processing unit 50.

The solid processing device 50 includes a bus request terminal 70 and a bus acknowledge terminal 71. These terminals are connected to signal lines of system control bus 52. However, in FIG. 3, these signal lines are shown separately. When a bus request signal is provided to bus request terminal 70, central processing unit 50 tristates its data port and its address port (connected to system data bus 54 and system address bus 53, respectively). At this time, a pass acknowledge signal is output from the terminal 71, and the DMA device 10A, IOB, or IOC that receives this signal can use the system bus.

DMA device 10A 5IOB and IOc each have a bus request output terminal 72 that outputs a bus request signal when requesting use of the system bus, and a bus request input terminal 73 that receives and receives bus requests from other DMA devices. Be prepared.

When the DMA device 10G generates a bus request signal, this signal is supplied to the bus request input terminal 73 of the DMA device 10B, and is sent to the bus request input terminal 73 of the DMA device 10A via the bus request output terminal 72 of the DMA device 10B. and is supplied to the bus request terminal 70 of the central processing unit 50 via the bus request output terminal 72 of the DMA device 10A.

Similarly, the pass acknowledge signal is transmitted from the pass acknowledge terminal 71 of the central processing unit 50 via the bus acknowledge input terminal 74 and the bus acknowledge output terminal 75 to the DMA device that generated the bus request signal.

The DMA device that has generated the bus request signal latches the pass acknowledge signal and does not transmit this signal to the lower DMA device until it finishes using the system bus.

〔Effect of the invention〕

The DMA device of the present invention can minimize the time that the system bus is used even when the transmission speed of the transmission circuit connected to the device is slow. Therefore, direct memory access can be performed without substantially interrupting the processing of the central processing unit, which has the effect of increasing the processing efficiency of the central processing unit and also increasing the efficiency of data transmission from the transmission circuit.

Furthermore, by using a large number of processors, it is possible to provide a high-performance packet switching device without the need for expensive processing equipment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a DMA device according to an embodiment of the present invention. FIG. 2 is a block diagram of a data transfer device including a central processing unit, a transmission circuit, and a DMA device. FIG. 3 is a block configuration diagram showing an example of a configuration for multiple transmission devices to access the same storage device. 10, 10A, IOB, IOC... DMA device, 20... Control port, 21... Address port,
22...Data port, 23...Device control bus, 2
4... Device address bus, 25... Device data bus, 26... Buffer circuit, 27... Output buffer,
28... Input buffer, 29... Internal bus, 30...
...Transmission port, 31...Control circuit, 32...Device transmission control bus, 33...Transmission control port, 34...
Decoder circuit, 35.36... programmable circuit,
37... Address pointer, 38... Address register, 39... Counter, 40... Digital comparator, 50... Central processing unit, 51... Transmission circuit, 52
... system control bus, 53 ... system address bus, 54 ... system data bus, 55 ... storage device, 56 ... transmission bus, 57 ... transmission control bus,
70... Bus request terminal, 71... Bus acknowledge terminal, 72... Bus request output terminal, 73... Bus request input terminal, 74... Bus acknowledge input terminal, 7
5...Bus acknowledge output terminal.

Claims (7)

[Claims] (1) An address port (21) connected to a system bus including an address bus and a data bus that connects a storage device and a central processing unit, and connected to the address bus.
and a data port (22) connected to the data bus, a transmission port (30) connected to the transmission circuit, and a means for transferring data between the storage device and the transmission circuit. In the memory access device, the means for performing the data transfer includes a buffer means (26), the data port (22), and the buffer means (26).
means (25) for transferring data between said transmission port (30) and said buffer means (26); request to the processing device,
The data port (22) and the buffer means (26)
A direct memory access device comprising control means for returning control of the system bus to the central processing unit when there is no data to be transferred between the system bus and the central processing unit. (2) The control means includes means for detecting an interval in which the central processing unit does not use the address bus and the data bus, and means for requesting use of the address bus and the data bus during this interval. The direct memory access device according to scope item (1). (3) The buffer means (26) includes an output buffer (27) for transferring data from the storage device to the transmission circuit, and an input buffer (28) for transferring data from the transmission circuit to the storage device. A direct memory access device according to claim (1). (4) Output buffer and input buffer (27, 28)
3. The direct memory access device according to claim 3, wherein the direct memory access device is configured to store one word of data each. (5) The control means includes a buffer means (26) and a storage device (
55) program-controlled configurable means for transferring consecutive words to and from a plurality of memory locations (35);
, 36). The direct memory access device according to claim (1). (6) The means that can be set by the program are means (37) for indicating the address of the first storage location, means (38) for storing the number of data to be transferred, and means (39) for calculating the address to be read next. ) A direct memory access device according to claim (5). (7) a central processing unit (50); a storage device (55) connected to the central processing unit by a system bus including a data bus and an address bus; and a direct memory access device (10) connected to the system bus. and a transmission circuit connected to the direct access memory device, the direct memory access device (10) having an address port (21) connected to the address bus, and a data port connected to the data bus. (22); a transmission port (30) connected to a transmission circuit; and means for transferring data between the storage device and the transmission circuit, the direct memory access device comprising: a buffer; means (26); said data port (22) and said buffer means (26).
means (25) for transferring data between said transmission port (30) and said buffer means (26); request,
The data port (22) and the buffer means (26)
and control means for returning control of the system bus to the central processing unit when there is no data to be transferred between the data transfer apparatus and the system bus.