JP2603123B2 - Descriptor chaining method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A method of chaining command descriptors for indexing a reception buffer is intended to eliminate the need for scanning such as returning, acquiring, and reconnecting descriptors. Are connected to a command descriptor having fields indicating the head address of the reception buffer, the byte length of the reception data, and the head address of the next processing command descriptor, are used to chain each command descriptor, and provide the address of the command descriptor. The specified byte length data is transferred to the corresponding reception buffer by the DMA operation when read, and the data in the reception buffer is read out at the end of reception and the address of the next descriptor described is given. In the reception data transfer method for continuously executing the executed commands, each command descriptor is connected in a ring shape, and when the processing of each command descriptor is completed, the content is updated and a new buffer is connected thereto. .

[Industrial applications]

The present invention relates to a system for chaining command descriptors (hereinafter simply referred to as "descriptors") for indexing reception buffers, and more particularly to a descriptor chaining system for connecting descriptors in a ring.

[Conventional technology]

FIG. 6 is a diagram for explaining a conventional descriptor chaining method. _First receive buffer (RX-BF) 31 _{1 to} 31 ₄
There is set, it is assumed that the descriptor corresponding to each (DSC) 32 ₁ ~32 ₄ are chained. Reference numeral 33 denotes a head pointer indicating the address of the descriptor (DSC), and reference numeral 34 denotes a buffer pool.

FIG. 7 is a flowchart showing the processing in the conventional descriptor chaining system of FIG.

When the DMA transfer of data to the receive buffer (RX-BF) 31 ₁ from now communication LSI completed, the series of processing is started by interrupt takes respect communication LSI.

First, the descriptor (DSC) 3 indicated by the head pointer 33
2 _1-32 fetches the _fourth address (step S1) Contents Descriptor (DSC) 32 ₁ that corresponds to the receive buffer (RX-BF) 31 ₁ by is checked. By reference descriptor (DSC) 32 ₁ exit status description section (CSD), look at whether or not there was an error in the received data (step S2) ends the processing when there is an error,
If there is no error, a message having the byte length described in the buffer length description section (BLD) in the reception buffer (RX-BF) is transmitted (step S3). Thereby, for example, data received from the subscriber line is notified to each application program by the OS processing.

Next Descriptor (DSC) 32 ₁ of the head pointer 33 using the contents of the next descriptor describing portion (NDA) is updated (step S4), and with the next descriptor (DSC) 32 ₂ address is specified, spent descriptor (DSC) 32 ₁ is returned to the buffer pool 34 (step S5). And then the receive buffer (RX-BF) 31 ₅ is obtained from the buffer pool 34 together (step S6), and
Corresponding descriptor (DSC) 32 ₅ buffer pool 34
(Step S7). That is, since the data currently received is the receive buffer (RX-BF) 31 ₁ ended continue to be used to communicate the received data for each application program, the newly received Buffa provided to receive the next data (RX-BF ) To get the descriptor (DS
C).

Acquired descriptor (DSC) 32 ₅ is linked to the end at which the disk pre Kuta (DSC) 32 ₄ descriptors (DSC) which is chained (Step S
8). As a result, the completion of the reception preparation is notified to the communication LSI (step S9), and the next reception buffer (RX-BF) 31
DMA transfer of data to ₂ is performed. The data transfer in this case is performed in response to the descriptor (DSC) 32-byte length specified in the buffer-length description portion described in ₂ (BLD), octets number word number description unit received at the receiving ends (CCD ) Is written.

In the conventional descriptor chaining method,
Each time the processing of data output from the reception buffer (RX-BF) ends, the descriptor (DSC) corresponding to the reception buffer (RX-BF) is returned to the buffer pool 34, and a new reception buffer (RX-BF) is returned. A descriptor (DSC) corresponding to is acquired from the buffer pool 34 and linked to the end of the descriptor chain.

Therefore, it takes time to return the processed descriptor (DSC), obtain a new descriptor (DSC), and change the link, thereby causing a problem that the processing speed is reduced.

In such a descriptor chaining method, it is required that the processing speed is not reduced by returning and acquiring the descriptor (DSC) and changing the link.

[Problems to be solved by the invention]

The present invention is intended to solve such a problem of the prior art, and does not require operations such as returning, acquiring, and reconnecting a descriptor (DSC), and thus provides a descriptor chaining method that can improve the processing speed. It is intended to be.

[Means for solving the problem]

In the present invention, as shown in the embodiment of FIGS. 1 and 2, each of a plurality of reception buffers (RX-BF) 31 _{1 to} 31 _m for storing data received from the outside is a descriptor (DSC) 32 _1. It is connected to to 32 _n are used. m represents the total number of reception buffers (RX-BF), and n represents the total number of descriptors (DSC). The relationship is m ≧ n, and any receiving buffer (RX-BF) may be connected to each descriptor (DSC). Each descriptor (DSC) is provided with a field indicating a head address of a reception buffer (RX-BF), a byte length of received data, and a head address of a descriptor (DSC) to be processed next.

When the address of each descriptor (DSC) is given, the byte-length data described in that descriptor (DSC) is transferred to the corresponding receive buffer (RX
-BF), and this buffer (RX-
BF) and read the descriptor (DS
The chained commands are continuously executed by giving the address of the next descriptor (DSC) described in C).

In this case, each descriptor (DSC) 32 _{1 to} 32 _n is connected in a ring shape, and when the processing of each descriptor (DSC) is completed, its contents are updated and a new reception buffer (RX-BF) is connected to this. It was done.

Accordingly, the configuration of the present invention is as described below. That is, each of the plurality of reception buffers 31 _{1 to} 31 _m for storing data received from the outside has a field indicating a head address of the reception buffer, a byte length of the reception data, and a head address of a command descriptor to be processed next. Each of the command descriptors 32 _{1 to} 32 _n is connected and used, and each command descriptor is chained. When the address of the command descriptor is given, the byte-length data described in the command descriptor is transferred to the DMA.
In the receiving data transfer method of transferring to the corresponding receiving buffer by operation, reading out the data of the receiving buffer at the end of the receiving, and continuously executing the chained command by giving the address of the next descriptor described, Each of the command descriptors 32 _{1 to} 32 _n is connected in a ring shape, and when the processing of each command descriptor is completed, its contents are updated, and a new reception buffer is connected thereto. .

(Operation)

In the descriptor chaining method of the present invention, a required number of descriptors (DSCs) are connected in a ring shape in advance.

Then, the head pointer 33 is made to always point to the descriptor (DSC) being processed (to be processed), and the received data is transferred to the reception buffer (RX-BF) by DMA transfer according to the description of the descriptor (DSC). The processing of the next descriptor (DSC) is sequentially performed according to the address described in the (DSC). Thus, the chained commands are continuously executed.

At this time, each of the descriptors (DS
When the processing of C) is completed, the contents are updated and a new receive buffer (RX-BF) is connected to this, so the descriptor (DSC) is used for each receive data transfer processing
There is no need to perform the processing of return, acquisition, and chain connection, so that the processing time can be shortened and the data transfer speed can be improved.

〔Example〕

FIG. 1 is a diagram for explaining a descriptor chaining method as one embodiment of the present invention, and the same parts as those in FIG. 6 are indicated by the same numbers. In FIG. 1, the numbers m and n match in the correspondence relationship between the reception buffer (RX-BF) 31 _{1 to} 31 _m and the command descriptor (DSC) 32 _{1 to} 32 _n. 1
A method in which a reception buffer is connected and performs reception processing.
The numbers m and n do not necessarily have to match.

FIG. 2 is a flowchart showing processing in the descriptor chaining method of the present invention shown in FIG. 1, and the same steps as those in FIG. 7 are indicated by the same numbers.

In the descriptor chaining method of the present invention, a required number of descriptors (DSCs) 32 _{1 to} 32 _n are connected in a ring shape.

After receiving buffer (RX-BF) 31 ₁ DMA transfer of data to have been completed from the communication LSI, the processing of step S1~S4 leading to update the head pointer 33, and the conventional case shown in FIG. 7 The same is done.

Even if the next descriptor (DSC) 32 ₂ address by updating the Het pointer 33 is specified, not returned to the used descriptors (DSC) 32 ₁ buffer pool 34. The newly received buffer (RX-BF) 31 ₅ is acquired from the buffer pool 34 (step S6), and is connected to the descriptor (DSC) 32 _1. Here, receive buffer (RX
-BF) 31 ₅ are for convenience, be any as long as it is in the buffer pool. That is, now receive buffer (RX-BF) 31 ₁ to the data reception has been completed is still used in the notification of the received data for each application program, a new receive buffer (RX-BF) 31 ₅ won by descriptor instead ( DSC) ready for the next data reception by connecting the 32 _1.

As a result, the reception preparation completion is notified to the notification LSI (step S9), and the next reception buffer (RX-BF) 31 ₂
DMA transfer of data is performed.

FIG. 3 is a diagram exemplifying a configuration of a system to which the present invention is applied, and shows a connection form between the ISDN exchange and the subscriber line 2. In FIG. 3, reference numeral 1 denotes a concentrator, which connects a subscriber line 2 to a switching network 3 by concentrating. The concentrator 1 has a digital subscriber circuit (DLC) 4 corresponding to each subscriber line 2, and each digital subscriber circuit (DLC) 4 is further connected to the switching network 3 via a demultiplexer 5. Is done. Each of the line concentrators 1 has a control unit (DLCC) 6, and controls connection in each digital subscriber circuit (DLC) 4 and multiplexing / demultiplexing unit 5. Further, a line control processor (LPR) 7 controls a controller (DLCC) 6 to control connection between each concentrator 1 and the switching network 3. Line control processor (LPR)
Reference numeral 7 has a central processing unit (CPU) 9 and a main memory (MM) 10 and controls signaling via a signaling control unit (SGC) 8. Reference numeral 11 denotes a central control unit (CC) for controlling a communication path in the switching network 3, and a main memory (MM) 12 holds or stores various information required at this time.

FIG. 4 is a diagram showing a configuration example of the control device (DLCC) 6 shown in FIG. Reference numeral 21 denotes a communication LSI which constitutes a data link control device. Under the control of a central processing unit (CPU) 22, a digital subscriber circuit (DLC) 4 or a control device (DLCC) 6 and a reception buffer (RX- BF) for transmitting and receiving data to and from a multi-channel communication processing device (MACH-1) 23 for processing the HDLC procedure and a multi-channel communication processing device (MACH-2) 24 having a DMAC function. Has become. Central control unit (CPU) 22, multi-channel communication processing unit (MACH-1) 23, multi-channel communication processing unit (MACH-
2) 24 is connected by a bus 25, and further via an address latch 26 and a data input / output unit (data D / R) 27, a read-on memory (ROM) 28, a random access memory (RA
M) Connected to 298.

Address latch 26 is connected to bus 25 and read-on memory (RO
M) 28, and latches addresses transferred to a random access memory (RAM) 29. A data input / output unit (data D / R) 27 is connected to a bus 25 and a read only memory (RO).
M) 28, and inputs and outputs data transferred to and from a random access memory (RAM) 29. Lead-on memory (RO
M) 28 includes a central control unit (CPU) 22, a multi-channel communication processing unit (MACH-1) 23, and a multi-channel communication processing unit (MA
CH-2) Stores basic programs necessary for the operation of 24, and is read into each unit from now on at initial setting. The random access memory (RAM) 29 is provided with a reception buffer (RX-BF) area and a descriptor (DSC) area for data to be DMA-transferred from the multi-channel communication processing device (MACH-2) 24, and a central control device (RAM). The programs necessary for the reception processing in the CPU 22, the multi-channel communication processing device (MACH-1) 23, and the multi-channel communication processing device (MACH-2) 24 also exist here.

When receiving data, the multi-channel communication processor (MACH-
1) 23 receives the data by performing the process of the HCLC procedure, and the multi-channel communication processing device (MACH-2) 24 converts the received data by the DMA operation to the multi-channel communication processing device (MACH-1).
Transfer from 23 to memory (receive buffer). At the time of data transmission processing, a multi-channel communication processing device (MACH-2)
24 transfers the transmission data from the memory to the multi-channel communication processing device (MACH-1) 23 by the DMA operation.

At this time, during the DMA operation, the control right of the bus 25 is transferred from the central control unit (CPU) 22 to the multi-channel communication processing unit (MACH-2) 2.
4 and multi-channel communication processor (MACH-2) 24
When the one-word DMA transfer is completed, the control of the bus 25 is returned to the central control unit (CPU 22).

DM in the multi-channel communication processor (MACH-2) 24
In the data transmission / reception processing by the A operation, a descriptor (DSC) describing control information is provided for each data of one frame in a memory (reception buffer), and the processing is performed by chaining and deploying the descriptor (DSC). This enables continuous processing of data of a plurality of frames to improve the processing speed.

FIG. 5 is a diagram illustrating a configuration example of a descriptor (DSC), which includes a memory address description section (MAD), a buffer length description section (BLD), a word count description section (CCD), an end state description section (CSD), The next descriptor description (NDA) is shown.

The head address of the receive buffer (RX-BF) for performing the DMA transfer is written in the memory address description part (MAD). The byte length of the received data is written in the buffer length description section (BLD). The number of octets received in the received command is written in the word number description section (CCD). The termination buffer (RX-B
The state of F) is written. Next descriptor description section (NDA)
Indicates the start address of the next descriptor (DSC). It should be noted that data other than the above is written in the blank portion in FIG.

In the descriptor chaining method according to the present invention, the processing speed does not decrease due to the return of the descriptor (DSC), the acquisition, or the reconnection of the link.

〔The invention's effect〕

As described above, according to the present invention, the descriptors (DSCs) corresponding to the plurality of reception buffers (RX-BF) are chained, and the reception data is DMA-operated according to the description of the descriptors (DSCs). RX-B
F), and receive data corresponding to the chained descriptors (DSC) are sequentially and continuously output by DMA transfer in accordance with the description of each descriptor (DSC).
C) is connected in a ring, so the descriptor (DSC)
The time for returning, acquiring, and chain connection is shortened, and the processing speed of transfer of received data can be improved.

[Brief description of the drawings]

FIG. 1 is a view for explaining a descriptor chaining method as one embodiment of the present invention, FIG. 2 is a flowchart showing processing in the descriptor chaining method of the present invention, and FIG. 3 is a system configuration to which the present invention is applied. FIG. 4 is a diagram illustrating a configuration example of a control device (DLCC). FIG. 5 is a diagram illustrating a configuration of a descriptor (DSC). FIG. 6 is a diagram illustrating a conventional descriptor chaining method. FIG. 7 is a flowchart showing a process in the conventional descriptor chaining method. DESCRIPTION OF SYMBOLS 1 ... Concentrator 2 ... Subscriber line 3 ... Switching network 4 ... Digital subscriber circuit (DLC) 5 ... Demultiplexer 6 ... Controller (DLCC) 7 ... Line control processor (LPR) 8 ... Signaling control unit (SGC) 9 Central processing unit (CPU) 10, 12 Main memory (MM) 11 Central control unit (CC) 21 Communication LSI 22 Central processing unit (CPU) 23 Multi-channel communication processing device (MACH-1) 24 Multi-channel communication processing device (MACH-2) 26 Address latch 27 Data input / output unit (data D / R) 28 Read-only Memory (ROM) 29 Random access memory (RAM) 31 _{1 to} 31 _m ...... Reception buffer (RX-BF) 32 _{1 to} 32 _n ...... Command descriptor (DSC) 33 ...... Head pointer 34 ...... Buffer pool

Continuing on the front page (72) Inventor Sumie Morita 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Noriko Yamada 3-9-1, Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Fujitsu Daiichi Tsushin Software Ware Co., Ltd. (72) Inventor Takashi Koga 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa Prefecture Fujitsu Daiichi Tsushin Software Co., Ltd. (72) Inventor Tsutomu Shioman 3-chome, Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa No. 9 No. 18 Fujitsu Daiichi Communication Software Co., Ltd.

Claims (1)

(57) [Claims] 1. Each of a plurality of reception buffers 31 _{1 to} 31 _m for storing data to be received from the outside indicates a head address of the reception buffer, a byte length of the reception data, and a head address of a command descriptor to be processed next. Each of the command descriptors 32 _{1 to} 32 _n having each field is connected and used, and each command descriptor is chained. When an address of the command descriptor is given, byte-length data described in the command descriptor is received by a DMA operation. In the reception data transfer method, when the reception is completed, the data in the reception buffer is read out, and the chained command is continuously executed by giving the address of the next descriptor described. _1-3 2. A descriptor chaining method characterized by connecting 2 _n in a ring shape, updating the contents of each command descriptor at the end of processing, and connecting a new reception buffer to this.