JPS59218531A - Information processor - Google Patents

Abstract

PURPOSE:To improve the information processing capacity by providing a time band when the using right of a data bus is disused for a communication controller which performs the asynchronous control for transfer of data between a CPU and a memory device via a communication circuit. CONSTITUTION:A CPU1, an RAM2 and a floppy disk FDP3 are connected to a common BUS, and a communication controller CIP4 performs the asynchronous control to transfer data among said parts. Both the FDP3 and the CIP4 are constituted with a small microprocessor type logic respectvely and transfer data between the RAM2 and the FDP3 via the BUS with no use of the CPU. The CIP4 inhibits temporarily the bus using right before the next data transfer is started when a piece of data is received from a host computer. Then the bus is used again after a prescribed period of time, and the data is transferred among the CPU1, the RAM2 and the FDP3 while the bus using right is disused. Thus the information processing capacity is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an information processing device, and for example, to a technique effective for a microcomputer having a data communication function, such as a microcomputer system development device.

[Background technology]

For example, when developing a program for a microcomputer, it is conceivable to develop the program by connecting a host computer, such as a large-sized computer, and the microcomputer through a communication line. A microcomputer serving as such a terminal device is provided with a communication control device whose sole task is to send and receive data through a communication line using a small microprocessor type logic.

The above microcomputer includes a microprocessor, RAM (random access memory),
A floppy disk control device and the communication control device are connected via a common signal bus, and the communication control device asynchronously transfers data between the RAM or floppy disk memory and the host computer through a communication line. In other words, each data transfer is performed upon receiving the data transfer end signal. At this time, the inventor's research has revealed that the following problem occurs.

In other words, since the various memory devices and the communication control device are connected via a bus to transfer the data, the signal bus is occupied by the communication control device during a series of data transfers. . therefore,
During this time, the microprocessor simply waits for the signal bus to become available and is unable to perform any information processing operations.

[Purpose of the invention]

An object of the present invention is to improve the efficiency of information processing operations in an information processing apparatus having a data communication function.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, by providing a function to set a time period during which the communication control device relinquishes the right to use the signal bus while a series of data is being exchanged through the communication line, microcontroller control can be performed even during data transfer operations. It enables other devices, such as processors, to perform information processing operations.

〔Example〕

The drawing shows a block diagram of an embodiment of a microcomputer system to which the present invention is applied. Although not particularly limited, the microcomputer system of this embodiment is used as a program development device for a microcomputer.

Memory board RA consisting of a microprocessor CPU and a semiconductor memory device such as dynamic RAM
M, the floppy disk control device FDP, and the communication control device CIP are interconnected by a common bus BUS to form one information processing system. Above bus B
US includes an address bus and a data bus.

In addition, a CRT as a program debug module, etc.
Input/output devices such as a console and a printer are also provided, but they are omitted because they are not directly related to this invention.

The above-mentioned floppy disk control device FDP and communication control device CIP are both configured with small microprocessor-type logic, and are capable of exchanging data between the RAM and floppy disk memory and through communication lines without using the microprocessor CPU. These are control devices whose sole and exclusive job is to send and receive data.

That is, the communication control device CIP transfers data held in the RAM or floppy disk memory to the host computer through a communication line, or conversely receives data in the memory device of the host computer and transfers the data to the RAM or floppy disk memory.
Alternatively, it performs tasks such as writing to a disk memory. In this embodiment, the following functions are added to the communication control device CIP in order to improve the efficiency of the processing function of the microprocessor CPU, in other words, to realize so-called multi-jobs.

Although not particularly limited, in data transfer with the host computer, when one data is transferred and a zero reception signal is received, the acquired bus usage right is temporarily relinquished before transferring the next data, and the programmable After the time set by the timer has elapsed, the right to use the bus is acquired again and the data transfer according to the method described above is performed.

The time set in the programmable timer is set by the microprocessor CPU or the like according to the priority of the data transfer operation currently being performed.

In this embodiment, as described above, the communication control device CIP is used to set an idle time period of the bus BUS set by the above-mentioned timer while exchanging data with another information processing device such as a post computer. Therefore, the microprocessor CPU and the like can perform information processing operations using this time. Therefore, in the microcomputer system of this embodiment, the data transfer operation using the communication line and the information processing operation by the microprocessor CPU etc. are performed in a time-sharing manner.

〔effect〕

+11 A process that takes a relatively long time (by providing a time period in which the bus BUS is idle during a data transfer operation using a line line, the microprocessor CPU, etc. can perform the desired information processing operation using this time. Since it can be executed, it is possible to achieve the effect of achieving high efficiency in the information processing operation that accompanies the data transfer operation.

(2) By using a programmable timer to set the time during which the bus is idle, the above two types of information can be transmitted in a time-sharing manner according to the priority of data transfer using the communication line. The effect is that substantial time allocation for processing can be made.

(3) By being equipped with a communication control device and operating it essentially in a time-sharing manner, it is possible to use a large-sized computer and also process information with a microprocessor CPU. The effect is that program development becomes relatively easy.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without getting the gist of the invention. Nor. For example, the bus may be provided with an idle time every time a plurality of data are transferred via a communication line. Further, the above-mentioned free time setting may be performed using a delay circuit, various counter circuits, etc. that perform a predetermined time setting operation.

Claims (1)

[Claims] l. A central processing unit, a memory device, a communication control device whose job is to send and receive asynchronous data through a communication line, and a signal bus that connects these devices. Information characterized by having a function of setting a time period during which the communication control device relinquishes the right to use the signal bus while the communication control device is transmitting and receiving a series of data through the communication line. Processing equipment. 2. The information processing apparatus according to claim 1, wherein the time period during which the right to use the signal bus is relinquished is set during each data exchange. 3. The time setting of the time period in which the right to use the signal bus is to be waived is set by a programmable timer, claim 1 or ff12.
The information processing device described in the section. 4. The information processing device according to claim 1, 2, or 3, wherein the information processing device constitutes a program development device for a microcomputer.