JPS6339042A - Intertask synchronizing system for multi-task - Google Patents

Abstract

PURPOSE:To ensure the working of a multi-tasking system without destructing a synchronizing mechanism and to process the tasks in the order of higher priorities, by processing the tasks of higher priorities with preference only with management of the priority of each task even in case the I/O processing is involved. CONSTITUTION:When the task of processing algorithm delivers a system call P(S) to an operating system OS, a CPU 1 gives a command to a semaphore managing part 6 and the semaphore designated by a semaphore part 3 is decided. Then this semaphore if decided off is turned on and the flag of a flag part is turned on to complete the processing. While if said semaphore is kept on, the part 6 gives a command to an address generating part 4 to produce an address so that the corresponding task information is selected within a semaphore-only task control part 2. A comparator 7 compares the priority information given from the part 2 with the task priority given from the CPU 1. Then a signal is sent to an interruption control part to perform the interruption processing when the priority of the task produced the call P(S) is higher than the priority information of the part 2.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to multitasking, a processing method in which a program is divided into tasks in small processing units and a CPU (central processing unit) is allocated in a time-sharing manner. The present invention relates to an inter-task synchronization method in a processing device that supports.

[Conventional technology]

Generally, in multitasking, a plurality of tasks operate by monopolizing a CPU in a time-sharing manner according to their respective priorities. Normally, in order to achieve this kind of multitasking, basic software called an operating system or a monitor is involved, and this operating system (hereinafter referred to as O8) responds to processing requests (hereinafter referred to as system calls) from each task. It manages interrupts and performs overall control so that multiple tasks operate without contradiction. This control is usually realized by software or firmware such as a microprogram. In this multitasking, tasks have several task states so that multiple tasks can operate without contradiction.

If you take a moment in time, there is only one task that is running exclusively using the CPU, and this is called the run state. Although it is possible to transition to this run state, it is not possible to run due to priority. A state in which it is waiting without being able to move to the O8 state is called a ready state, and a state in which a system call has been issued to O8 but the request is not satisfied is called a wait state. These state transitions are managed by the O8, which changes the state of each task as appropriate to control the entire system to operate normally.

In multitasking, which is different from traditional single-programming, there are a number of phenomena that require attention. for example,
Multiple tasks use the same memory or input/output device (hereinafter referred to as I10)
), if control is transferred to another task while one task is using the shared memory or Ilo, and that task uses the shared memory or Ilo, the previously running task will There is a possibility that the data in the memory that was being manipulated and the state of Ilo will be destroyed.

In this case, when control is transferred to the original task again, it will not be able to operate normally. As a means to avoid such a phenomenon, O8 generally has an inter-task synchronization mechanism.

There are many methods for this inter-task synchronization mechanism, but here we will explain the task jump synchronization flag (hereinafter referred to as semaphore).

FIG. 4 is a block diagram showing an example of a synchronization method between tasks using a general semaphore. In this example, two tasks 21.22, task A including read Ilo, and task B including write Ilo, share I, 1020, and task B has a higher priority. In the figure, P (S) is one of the system calls that requests the semaphore to take exclusive use of the semaphore, and V (S) requests the semaphore to release the semaphore.

FIG. 5 is a flowchart illustrating the processing of this system call P (S). In step 31, O8 turns on the semaphore.
This semaphore is not ON but OFF.
If it is, the semaphore is turned on in step 32.

In this case, the task that issued this system call has satisfied the request. Furthermore, if the semaphore is already ON, the task that issued the system call in step 33 temporarily saves the state at this point, and in step 34 transitions from the run state to the wait state. In this way, the task is
It often holds the state at a certain point and suspends execution.

The space for saving this state is called a task control block (hereinafter referred to as TCB), and the configuration of this TCB is shown in a part of FIG. 3. Normally, TCBIo, 11 is secured in memory, and one TCB exists for each task. This T (, BIO is connected to the control unit 12 and the evacuation area 13
The control unit 12 is a space reserved for the O8 to manage tasks, and the save area 13 is a space for saving the state of the running program and the state of Ilo when the task is interrupted.

The O8 suspends the system call issuing task, transitions to a wait state in step 34, and then transitions to step 35.
The process of P(S) is ended by selecting a task to be placed in a run state and passing control to that task.

FIG. 6 is a flowchart showing the processing of the other system call (S). First, in step 36, O8 determines whether there is any task waiting for the semaphore. If there is no task waiting for the semaphore, in step 37, O8 turns off the semaphore and ends the process. If there are waiting tasks, one task among the waiting tasks is selected in step 38, the task state is transitioned from the wait state to the ready state, and then the task to be put in the run state is selected in step 39. to end the process.

Task A in FIG. 4 performs read processing 21 from I 1020, and task B performs write processing 2 to Ilo.
Do step 2. First, task A runs, issues a semaphore exclusive request system call P(S>, and enters read processing 21 from I 1020. Assuming that an interrupt occurs during this read processing 21 and task B is activated, Task B
attempts to execute write processing 22 and issues P (S).

In this case, since the semaphore is already occupied by task A, task B transitions to a wait state, O8 selects task A again, and task A continues the read process 21. After this reading process 21 is completed, system call V(S
), the semaphore is released, task B, which is waiting for the semaphore, monopolizes the semaphore and transitions from the wait state to the ready state. O8 then selects task B and puts it in a run state, thereby transferring control to task B, and task B can move on to the write process 22. This task B executes system call V (
S) to release the semaphore and allow another task to newly occupy the semaphore.

FIG. 7(a) is a time chart explaining the above process, where the horizontal axis is time and the vertical axis is task A.

Each process of tasks B and I10 is shown. The dotted line on the horizontal axis represents the state of not being activated or the wait state, the dotted line on the vertical axis represents the correspondence of the processing flow, and the solid line represents the CP
It represents the processing of U or Ilo.

As explained above, by using the synchronization mechanism, the write process 22 can be executed during the read process 21,
Also, malfunctions caused by performing the opposite operation can be prevented. Typically, O8s that support this type of multitasking are equipped with a synchronization mechanism. Manual riRMX86 NUCLEUS R
See EFERENCE MANUA'L.

[Problem that the invention seeks to solve]

As mentioned above, semaphores are used to synchronize tasks, but once a semaphore is occupied,
Until the semaphore is released, any task will be placed in a wait state by using the system call P (S>) and will not be able to operate. In multitasking, tasks have priorities, and tasks with higher priority However, in a multitasking system, it is difficult to control the execution order of each task in detail, and the processing of tasks with high priority is difficult. It has the disadvantage that it is put on hold by issuing the system call P(S) and is dependent on the processing of tasks with lower priority, resulting in a delay in the processing order.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-task inter-task synchronization method that eliminates such drawbacks, prioritizes processing of tasks with high priority, and eliminates delays in processing order.

[Means for solving problems]

The configuration of the present invention is such that multitasking processing, in which a program is divided into tasks for each processing unit and the central processing unit is time-divided for processing, synchronizes each task using a flag management means that manages an inter-task synchronization flag. In the inter-task synchronization method that is performed while a comparison means for comparing the priority of the task that monopolizes the flag management means included in the exclusive task management means; The invention is characterized in that it includes an interrupt control means for outputting an interrupt signal to the central processing unit when the level is high.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, l is a central processing unit (CPU), 2 is a semaphore exclusive task management section, 3 is a semaphore section, 4 is an address generation section,
5 is a flag section, 6 is a semaphore management section, 7 is a comparator, and 8 is an interrupt management section. The semaphore unit 3 includes eight semaphores, and the semaphore exclusive task management unit 2 corresponds to each semaphore in the semaphore unit 3, and includes a pointer to the TCB and the priority of the task that exclusively uses each semaphore. . The address generation unit 4 generates an address for selecting one of the semaphore exclusive task management units 2. Semaphore management section 6
has the function of managing the semaphore unit 3 based on commands from the CPUI, controlling the address generating unit 4 to generate addresses, and setting a flag in the flag unit 5. Comparator 7 is CP
The task priority information given from U1 is compared with the priority information of the semaphore exclusive task management section 2, and a signal representing the comparison result is generated. The interrupt management unit 8 receives the signal and
Generates an interrupt signal to the CPUI.

FIG. 2 shows a flowchart when a task of a processing algorithm for operating this embodiment issues a system call P(S) to O8. Upon entering P(S) processing, the CPUI issues a command to the semaphore management unit 6. The semaphore management unit 6 determines the designated semaphore in the semaphore unit 3 in step 41, and if it is in the OFF state, turns on the designated semaphore in step 42, and turns the flag in the flag unit 5 to OFF.
If the answer is N, the process ends. The CPU determines whether the exclusive request for the semaphore is satisfied by determining the flag state of the flag unit 5, and if the flag unit 5 is ON, the CPU
Set to FF state.

If the designated semaphore of the semaphore section 3 is ON, the semaphore management section 6 sends a command to the address generation section 4 to generate an address. The address generation section 4 generates an address for selecting corresponding task information in the semaphore exclusive task management section 2 based on the information of the semaphore section 3 in response to a command. In step 44, the comparator 7 compares the priority information output from the semaphore exclusive task management unit 2 with the priority of the task that issued the system call P(S) generated from the CPUI, and determines whether the system call P(S) has been issued. If the issued task has a higher priority, a signal is generated to notify the interrupt management unit 8 of this fact, and the interrupt management unit 8
Generates an interrupt signal to the PUI. If the CPUI generates an interrupt, system call P is executed in step 45.
The task that issued (S) is transitioned from the run state to the wait state, and then, in step 46, the task to be placed in the run state is selected.

When interrupt processing is entered, the CPUI transfers the TCB from the TCB pointer in the semaphore exclusive task management section 2 in step 47.
, the I10 processing is interrupted, and the program state at that time and information for remembering that the I10 processing has been interrupted are saved in the save area of the TCB.

Figure 3 shows the semaphore exclusive task management section 2 and TCB in Figure 1.
It is a diagram showing the relationship between Io and 11. The TCB pointer of the semaphore exclusive task management unit 2 points to the corresponding TCB on the memory. The CPU 1 can know the location of the TCBIO existing on the memory using the TCB pointer. The CPU interrupts the task occupying the semaphore, saves the state at the time of interruption to the save area of the TCB, moves the task to the wait state if it is in the ready state in step 48, and then Step 4
Select the task to be placed in the run state in step 9.

Although this embodiment has been described with reference to eight semaphores, the number can be increased depending on the scale of the system, and the information of the semaphore exclusive task management section 2 is not the TCB pointer but identifies the task. You may also use an identifier for

FIG. 7(b) is a time chart showing the processing of each task and Ilo in this embodiment as a time flow, and FIG.
) are compared under the same conditions. First, task A monopolizes Ilo by issuing system call P (S), control is transferred to task B which is processing I10, and when task B issues system call P (S), task B has priority. Since the priority is high, the I10 processing of task A is interrupted, and task B monopolizes the semaphore and performs the I10 processing. After completing this I10 processing, task B makes system call V (S
), task A monopolizes the semaphore again,
I/'○ The process can now be re-executed.

These Figure 7(a).

As can be understood by comparing (b), by prioritizing the processing of high-priority task B and operating without breaking the synchronization mechanism, it is possible for the high-priority task to perform its intended processing quickly. becomes. Note that Δ in the figure represents the end of a task.

Assuming that the read processing of task A, which has a low priority, precedes the write processing of task B, which has a high priority, in the conventional method, task B, which is originally a high priority,
The information that should have been written is put on hold, and the previous read process causes the old I10 information to be read once, resulting in one useless read process.
In some cases, it is necessary to add an operation for determining whether the read information is new or old in the task Aljl that performs the read process. In contrast, in the method according to the present invention, the read process of task A is temporarily suspended, and after the write process of task B is executed, the read process of task A is re-executed. Therefore, when processes overlap, the process with a higher priority is always given priority, and the write process has already been written. : The latest information can be read.

〔Effect of the invention〕

As explained above, according to the inter-task synchronization method of the present invention, when building a multitasking system, there is no need to understand the processing order of each task in detail, and the I10 processing can be performed simply by managing the task priorities. Even when tasks are involved, priority can be given to tasks with higher priority, which greatly improves the ease of programming. In addition, by providing a semaphore exclusive task management unit, comparison means, etc., the structure of the O8 that executes the synchronization mechanism between tasks is simplified, and the O8
8 design also has a very large effect.

As explained above, in the present invention, when a proprietary system call for a semaphore is issued to O8, the priority of the task issuing the system call is determined by comparing the priority of the issued task with the priority of the semaphore exclusive task. If the semaphore is higher, the semaphore exclusive task is interrupted, the state at the time of interruption is saved, and the task issuing the system call is allowed to exclusively own the semaphore, so that the task with higher priority can monopolize the semaphore more quickly. I10 processing can be performed. In other words, it is possible to operate without breaking the synchronization mechanism, and tasks with higher priority can quickly perform their intended processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a flowchart explaining the processing of system call P(S> in this embodiment, and FIG. 3 is a block diagram of the semaphore exclusive task management unit 2 of FIG. A memory layout diagram showing the relationship with the task control block (TCB), Figure 4 is a configuration diagram showing an example of conventional synchronization between tasks, and Figures 5 and 6 are system call p in Figure 4.
(s) and V(S) processing, FIG. 7(a)
) and (b) are time charts showing inter-task synchronization in the conventional example and the present embodiment. 1...CPU, 2...Semaphore exclusive task management unit,
3... Semaphore section, 4... Address generation section, 5...
・Flag section, 6... Semaphore management section, 7... Comparator, 8... Interrupt management section, 10.11... Task control block (TCB), 12... Control section, 13.
・Evacuation area, 20...l101, 21.22...
・Task A. B, 31-38.41-49...step. . 2o δ

Claims (1)

[Claims] Inter-task synchronization, in which multi-task processing in which a program is divided into tasks for each processing unit and processed by time-sharing allocation of the central processing unit, is performed while each task is synchronized by a flag management means that manages inter-task synchronization flags. In the method, a dedicated task management means holds information regarding a task that exclusively uses the flag management means, and when a task issues an exclusive request to the flag management means, the priority of the task and the exclusive task management are provided. a comparing means for comparing the priority of a task that monopolizes the flag management means included in the means; and a comparison means that makes the monopolization request and, if the priority of the task is higher than the priority of the monopolization task, the central processing unit; 1. An inter-task synchronization method for multitasking, comprising: interrupt control means for outputting an interrupt signal.