JPS60557A - Dma control system - Google Patents

Abstract

PURPOSE:To remove the limitation in the mounting position of a channel by making a local burst possible with a system which is not an interlacing mode and, furthermore, without the highest priority. CONSTITUTION:Since a flip flop 15 is actuated and a bus request is outputted, and then, a bus occupancy permit is returned from a CPU when the internal request of a channel is generated, a counter 17 counts the bus occupancy permit. When the counter 17 counts the permit for more than predetermined times, the counter 17 generates an end signal END. When the end signal END is generated, a bus request is processed at the timing when the next bus occupancy permit arrives, but, until the next bus occupancy permit comes, a flip flop 16 outputs a DMA data sequence actuating signal at every occupancy permit passing through a gate 11. By means of the actuating signal, a DMA data transferring sequence is executed by one time to reset the flip flop 16 by means of the DMA sequence end signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a control method for DMA (direct memory access) performed between a channel and a memory.

Prior Art and Problems There is often a large amount of data fetched/stored in memory, and for this reason there is a tendency to adopt a local burst method in which data is transferred multiple times with one bus request.

Conventional methods for realizing local bursts include (1) a method using interlace mode, and (2) a method of giving the highest priority to a channel without using interlace mode. FIG. 1 is a time chart for explaining the method using the interlace mode mentioned above (11). In this method, the bus line has a Busy signal line, and the channel device that performs local burst raises the bus request and is granted bus occupancy. When it receives this, it issues a Busy signal and prohibits other channel devices from occupying the bus.

Therefore, multiple channel devices do not collide on the bus line, and DMA can be performed until the busy signal is stopped, i.e., local burst can be realized. On the other hand, on high-speed buses, the time required for DMA is relatively short (,
The waiting time is longer than the data transfer time, reducing data transfer efficiency. Furthermore, since a Busy signal line is required, there is a drawback that the number of bus pins increases.

FIG. 2 is a time chart according to method (2) above. This method does not require bus lines to have a Busy signal line, but instead gives highest priority to the farthest channel device on the control signal line (DC chain) so that such channel is A method is used in which a signal is raised to inhibit a bus request from a channel device, and a bus occupancy permission signal that comes in between is used to perform the required number of DMA operations.

In this method, the number of channels capable of local bursting is limited to one channel per system, and the mounting position is also limited, so there is a risk that versatility in system design may be impaired.

OBJECTS OF THE INVENTION The present invention attempts to eliminate the above-mentioned limitations of the conventional system by allowing local bursting in non-interlaced systems and even without the highest priority.

Structure of the Invention The present invention provides a DMA control method in which a channel device directly accesses memory through a bus, and when one of a plurality of channel devices connected to a common bus issues a bus request, the bus request is The channel device that issued the bus request is configured to serve as a bus request prohibition signal to other channel devices that have a lower priority than the channel device that issued the bus request, and the channel device that issued the bus request receives bus occupancy permission for each preset number of times. A unit of data is transferred for each bus occupancy grant, and when another channel device with a higher priority issues a bus request during the bus occupancy period, the acquisition of its own bus occupancy grant is interrupted. This will be explained in detail below with reference to the illustrated embodiments.

Embodiment of the Invention FIGS. 3 to 5 are explanatory diagrams showing an embodiment of the present invention, and FIG. 3 is a flowchart showing a control procedure. ``Judgment A'' in the figure is a step of determining whether a bus request is coming from a channel with a higher priority, and ``Judgment B'' is a step of determining whether a bus occupancy permission has been received a specified number of times. , "Judgment Cl is DM for the specified number of times.
This is a step of determining whether or not A has been executed. Judgment B
The "prescribed number of times" of and C are the same, and can be specified by program or setting before starting DMA.

FIG. 4 is a block diagram of a DMA control unit that executes operations according to the flow shown in FIG. 3, and FIG. 5 is a time chart thereof. In Fig. 4, 11 to 14 are AND gates, 15.1
6 is a flip-flop at J-, 17 is a counter, and 18 is an inverter.

Explain the operation. First, when an internal request for the channel is issued, the flip-flop 15 is activated and a bus request is output (at L level). This bus request (output) is passed to another channel or DM with a lower priority.
It is also sent to the A management department, and the Busy message in Figure 1 is sent to the former.
Acts equivalent to a signal (bus request prohibited). When this bus request is output, a bus occupancy permission is returned from the CPU, and this is counted by the counter 17. The bus request (input) input to the AND gate 11 is from a channel with a higher priority (it also enters at L level), and when this bus request (input) is received, the AND gate 1
1 is closed and does not allow the bus occupancy permission signal to pass. This corresponds to the broken line portion of the bus request in FIG. Therefore, judgment A in FIG. 3 is executed by this AND gate 11.

When there is no bus request (input) for the higher channel, AND gate 11 opens and passes the bus occupancy grant signal, which is applied to AND gates 12 and 13 and flip-flop 16. When there is an internal request, the flip-flop 15 is set and its Q output becomes the ■] level, and the counter 17 becomes 1.
When the number of DMA operations to be performed in response to a bus request is set and the count is not yet completed, the output is at L level, so the output of inverter 18 is at H level. Input to counter 17. The counter 17 counts this lotus occupancy permission signal. The counter 17 generates an end signal END after counting a predetermined number of times. This signal END is inverted by the inverter 18 and becomes L level, closing the gate 13, so that even if bus occupancy permission is input any further, it will not be counted. Therefore, judgment B in FIG. 3 is executed by the inverter 18, gate 13, etc. When the end signal END occurs, the flip-flop 15 is reset and the bus request (output) drops at the next timing when the lotus occupancy permission comes, but until then, the flip-flop 16 is reset every time the lotus occupancy permission passes through the gate 11. is activated and a DMA sequence activation signal is output. When one DMA data transfer sequence is executed by this activation signal, the flip-flop 16 is reset by a DMA sequence end signal, and becomes ready to be sent when the next bus occupancy permission arrives.

The time chart in FIG. 5 shows an example in which data transfer is performed three times with one bus request. In this case, "2" is set as an initial value in the counter 17, and the counter 17 is counted down by 1 each time a bus occupancy permission is received. In this way, the counter value becomes "0" when two bus occupancy permissions that have passed through Goo 1-13 are counted. This is taken as the prescribed number of times end signal END. In the example of FIG. 5, the second bus occupancy permission is due to a bus request from a higher-order channel, and since the gate 11 is closed, this does not become an input to the counter 17, etc. The counter 17 operates at the falling edge (trailing edge) of the bus occupancy permission signal, and does not change after the counter value reaches "0". Therefore, when the flip-flop 15 is reset by the last (4th - 3rd) bus occupancy permission and the lotus request (output) disappears, the counter 17 remains at "0". Therefore, the end signal END is generated one time before the number of bus occupancy permissions reaches the specified number.

Effects of the Invention As described above, according to the present invention, (1) there is no need for a Busy signal line since the mode is not interlace mode.

Therefore, the number of bus pins can be reduced and there is no need to change other channel devices. (2) Furthermore, since it is not necessary to give the highest priority to the channel that performs local bursting, there are advantages such as there are no restrictions on the mounting position of the channel.

[Brief Description of the Drawings] Figures 1 and 2 are explanatory diagrams showing different examples of conventional DMA control methods, and Figures 3 to 5 are flowcharts, block diagrams, and timing diagrams showing one embodiment of the present invention. It is a chart. In the figure, 11 is a bus occupancy permission acquisition inhibiting gate, 14 is a bus request transmission inhibiting gate, 15 is an internal request storage flip-flop, 16 is a DMA sequence activation flip-flop, and 17 is a specified number of times counter. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi 1:, Q7 Figure 1 Figure 3 Figure 4

Claims (1)

[Claims] In a DMA control method in which a channel device directly accesses memory through a bus, when one of multiple channel devices connected to a common bus issues a bus request, the bus request is lower than the channel device that issued the bus request. The channel device that issued the bus request receives bus occupancy permission for each bus occupancy permission while receiving bus occupancy permission for a preset number of times. A DM that performs unit data transfer, and suspends acquisition of its own bus occupancy permission when another channel device with a higher priority issues a bus request during the bus occupancy period.
A control method.