JPH10111857A - Multi-processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evade the performance reduction of a multi-processor owing to the synchronous processing of a parallel processing program by improving the reply speed of CR(communication register) access performance in appearance. SOLUTION: A CR mainbody 6 holds synchronous control information corresponding to respective CSs(critical section) in respective CR areas. A lock information holding part (lock bit register 8) is constituted by an element whose access speed is higher than the CR mainbody 6 and only lock information within synchronous control information inside the respective CR areas is held. A CR obtaining information hoolding part (CR obtaining information register 9) holds information indicating whether or not respective kinds of lock information inside the lock information holding part is obtained. A CR control part 10 receives a CR access request from respective CPUs 100 and executes control so as to return only lock information within synchronous control informationan inside the CR areas being the request object of the CR access request to respective CPUs 100 by a timing faster than that of reply data of whole synchronous control information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a multiprocessor (multiprocessor type information processing apparatus), and more particularly to a multiprocessor.
The present invention relates to a multiprocessor employing an R synchronization control method.

[0002]

2. Description of the Related Art In a multiprocessor, one of the important points to improve parallel processing performance is synchronous processing performance between processors. One way to speed up this synchronization between processors is as follows:
Many methods for realizing the barrier synchronization mechanism by hardware have been proposed.

In FIG. 7A, tasks 701 and 7
The operation for realizing barrier synchronization between the processes of the tasks 02 and 703 is described. First, the task 703 performs a necessary process up to the barrier synchronization point,
At this point, the task 703 enters a wait state because another task has not completed execution of necessary processing until the barrier synchronization point. Similarly, the task 701 enters a wait state. Finally, the necessary processing up to the barrier synchronization point is completed in the task 702, all the tasks recognize that the tasks 701 to 703 have reached the barrier synchronization point, and the subsequent processing is restarted. Such a synchronization method is called a barrier synchronization method.

The above-described barrier synchronization method is a general method as an information processing apparatus having a special hardware mechanism for realizing the barrier synchronization has been commercialized.

FIG. 7B is a diagram for simply explaining the operation of the hardware mechanism of the barrier synchronization method. That is, in FIG. 7B, the CPU (Central Pr)
2 shows an example of realizing barrier synchronization between three processors, namely, the processing unit 71, the CPU 72, and the CPU 73.

Each CPU has a synchronous F / F (Flip / F).
lop. 3) are included.
In other words, each of the three CPUs has an F / F set when the task of its own CPU has completed execution up to the barrier synchronization point.
F (own CPU task synchronization point arrival F / F) has one bit, and is set when another CPU task reaches the barrier synchronization point (other CPU task synchronization point arrival F / F).
F) has two bits. Own CPU task synchronization point reached F
/ F is F / F 710, 721, 732 in the CPU 71, the CPU 72, and the CPU 73, respectively. The F / F 711 and the F / F 712 are other CPU task synchronization point arrival F / Fs in the CPU 71 indicating that the tasks of the CPU 72 and the CPU 73 have reached the barrier synchronization point.
It is. F / F 720 and F / F in CPU 72
The same applies to the F / F 730 and the F / F 731 in the CPU 722 and the CPU 73.

The above-mentioned hardware mechanism can only cope with barrier synchronization between tasks on different CPUs. FIG.
(A) Task 701, task 702, and task 7
03 to CPU71, CPU72, and CPU73, respectively.
, The following processes are performed.

First, the task 703 reaches the barrier synchronization point, and the F / F 732 is set.

The information is transmitted via signal line 706 to the CP
It is also reported to U71 and CPU72, and F / F712 and F / F722 are set.

Next, the task 701 reaches the barrier synchronization point, the F / F 710 is set, the information is reported to the CPU 72 and the CPU 73 via the signal line 704, and the F / F 720 and the F / F 730 are set. .

Finally, the task 702 reaches the barrier synchronization point, the F / F 721 is set, the information is reported to the CPU 71 and the CPU 73 via the signal line 705, and the F / F 711 and the F / F 731 are set. .

As described above, the nine synchronous F / Fs
Is set, and the CPU confirms that barrier synchronization has been established.
The next processing is started by the recognition by the CPU 71, the CPU 72, and the CPU 73.

A good point of this method is that the report from the CPU executing the task that reaches the barrier synchronization point lastly coincides with the end of the task (exactly, from the timing when the task reaches the barrier synchronization point. Since all the CPUs are notified after the signal transfer time has elapsed), the next process after the barrier synchronization is established can be executed quickly.

On the other hand, the problem with this method is that it is usually only possible to read (READ) only one synchronization bit per processor (CPU), so that it cannot cope with multitask processing in which a plurality of tasks are processed by one CPU. That is. Further, when a plurality of sets of synchronous F / Fs are provided, the number of connecting cables between CPUs is increased, the number of logic circuits is increased, and the management of synchronous bits is complicated even in software.

Now, apart from the above barrier synchronization method, CR (Communication Resist)
er), which holds a “shared data area between CPUs whose access time is faster than that of the main memory (memory)”.
There is a method for realizing synchronization between processors based on synchronization control information stored in a processor (software can be realized, but generally, software) based on software.

In this method (CR synchronization control method), exclusive control of an exclusive resource called CS (Critical Section) shared by a plurality of tasks (CPUs on which the tasks are started) is realized by synchronization control information in the CR. Is done.

Each CR area exists in the CR corresponding to each CS, and a specific bit string (generally, the first bit) in the synchronization control information in the CR area makes it possible to use the CS. Information indicating whether or not it is set is set. Information on the exclusive control of the CS indicated by such a specific bit string is called lock information.
If it is bit information, the bit is called a lock bit.

An indispensable instruction in this CR synchronization control method is a test & set CR instruction (hereinafter abbreviated as a TSCR instruction).

FIG. 5 is a diagram showing an example of the specification of the TSCR instruction. This TSCR instruction includes an OPC field,
An Sx # field and a CR # field are included.

The TSCR instruction issued from a certain CPU (processor) is executed as shown in the following (1) to (5).

First, the value in the CR area specified by the CR address in the CR # field (the CS synchronization control information corresponding to the CR area) is stored in the work area W.

Further, when the first bit (lock bit) of the synchronization control information read from the CR area is “0”, the lock bit is set to “1”, and the synchronization control information is set to “1”. The value of the general-purpose register Sx (general-purpose register specified by the register number in the Sx # field) is stored in the remaining 63 bits in the information. Here, when the lock bit is set to “1”,
"The state where the CS is used" is shown. Also,
When “0” is set to the lock bit, “a state in which no task using the CS exists” is indicated.

On the other hand, if the lock bit is “1”
Is not written to the CR area. The general-purpose register Sx stores the value of the work area W, that is, read data of the work area W.

If a basic instruction such as the TSCR instruction for performing inseparable processing on a CR is prepared, the C
Exclusive control of S, and thus synchronous control among a plurality of CPUs, can be realized. Here, "indivisible" means that no other processing that manipulates the value must be performed during the read / write processing.

The advantage of this CR synchronization control system is that
It is possible to hold other data (in the above example, 63-bit data other than the lock bit) other than the lock information (lock bit information in the above example) as the synchronization control information. That is, a plurality of synchronization control information exists. Thereby, flexible synchronization control can be realized.

Further, even in the case where the CR synchronization control method is realized by hardware, the fact that the number of CR areas (the number of synchronization control information) in the CR increases, the feasibility of hardware is not considered. It does not significantly affect the number of inter-CPU connection cables that causes difficulty and high cost. In the barrier synchronization method described above, the superiority of the CR synchronization control method is apparent, considering that the number of connection cables between CPUs per control bit is “the number of CPUs * (the number of CPUs−1)”.

However, such a CR synchronization control system also has a problem. That is, the recognition of the establishment of the synchronization is delayed because another task waiting for the establishment of the synchronization (the state in which the CS can be used) spin-locks the CR.

In order to explain this problem, the above-mentioned CR
An example in which a synchronous control method is employed and an actual multitask process is executed will be described with reference to FIG. In this example, CS, which is a program that can be executed only by a single task, is exclusively controlled by the lock bit in the synchronization control information in the CR area of CR address CR # 3. As a simple example of a program corresponding to CS, there is a program for realizing a process for which operation cannot be guaranteed if a plurality of tasks are executed simultaneously, such as a process for accessing one input / output channel.

Task 601 is to execute CR of CR # 3 in CR.
To see the lock bit in the synchronization control information of the area, L
In OOP1, a TSCR instruction is executed. That is, the value of CR # 3 (synchronization control information) is stored in the general-purpose register S7.
Write.

Next, a branch instruction based on the value in the general-purpose register S7 is executed. This branch instruction determines the upper one bit (lock bit) of the value in the general-purpose register S7,
If “0”, the execution of the CS is started, and “1”
If so, jump to LOOP1 and retry TSC
This instruction repeats the execution of the R instruction. The state in which the execution of the TSCR instruction is repeated in this manner is referred to as “spin lock”.
Call.

In this case, since the task 601 is a task that has attempted to execute the CS first, the right to use the CS is acquired, and the execution of the CS is started.

On the other hand, the task 602 also checks the lock bit in the synchronization control information in the CR area of CR # 3,
At OP2, a TSCR instruction is executed. At this time,
The lock bit in the synchronization control information is set to "1" by the TSCR instruction by the task 601.
CS execution of task 602 is prevented. That is, in the execution of the branch instruction, the task 602 enters a spin lock state.

After completing the execution of the CS, the task 601 executes a CR write instruction (an instruction for writing to the CR) and sets the lock bit of CR # 3 to "0".

On the other hand, the task 602 executes a loop called TSCR-branch because the task 601 has executed CS first, and waits in a spin lock state until the CS is released.

When the task 601 sets the lock bit of CR # 3 to “0” by executing the CR write instruction, the task 602 acquires the right to use CS, and
Start running.

By the way, when the scale of the parallel processing program targeted by the present invention is small, the granularity of a task (the size of the processing amount of a single task) often decreases. Then, the frequency of the start / end of the task becomes high, and the CS shared between the tasks is frequently acquired / released. That C
Since S is actually shared by not so many CPUs, it is unlikely that a collision of shared resource acquisition requests will occur. Therefore, in the first TSCR instruction, C
There is a high possibility that acquisition of S will be performed.

Therefore, the activation time of the task activated after the acquisition of the CS is the time when the reply of the TSCR instruction returns, which affects the overall program performance. Therefore, it has been reported that the performance evaluation result that the shortening of the reply time of the TSCR instruction greatly contributes to the improvement of the performance of the parallel program, particularly to the improvement of the performance of the program having a small task granularity.

The tendency that the granularity of a task becomes smaller is as follows.
It largely depends on the nature of the program (algorithm), the parallel programming technology, and the capabilities of the parallelizing compiler. One of the important themes of the conventional parallel processing research is the establishment of a technique for increasing the granularity of a task, reducing the overhead of synchronous processing, and improving the parallel processing performance. Unfortunately, however, there are very few programmers with the technical skills to at least take advantage of this research. Therefore, it can be generally said that most of the parallel processing programs existing in the world have small task granularity, and the bottleneck of the program performance is the CR access time as described above.

[0039]

As described above, in the prior art "multiprocessor employing the CR synchronization control method", a CR access request (the above-described TSC
Since the access time of the R instruction, the CR write instruction, and the request by the CR read instruction becomes longer, a parallel processing program with a small task granularity (as described above, an actual parallel processing program is a program with a small task granularity) ), There is a problem that the overhead of the synchronization process increases.

Further, in order to increase the granularity of the tasks of the parallel processing program so as to hide the synchronous processing in order to reduce the above-mentioned problems, it is necessary to use advanced compile optimization techniques, advanced programming techniques, and parallel algorithms. Development is required. However, users (programmers) who master these techniques are very limited.

In view of the above, it is an object of the present invention to avoid performance degradation caused by synchronous processing of a parallel processing program without using a special technique for increasing the granularity of a task (performance of a parallel processing program). It is an object of the present invention to provide a multiprocessor (a multiprocessor adopting a CR synchronous control method) that is capable of apparently improving a reply speed of CR access performance, which is a main cause of the decrease.

In order to achieve the above object, the present invention employs the following basic concept. That is,
Information regarding CS exclusive control is indicated by lock information in the synchronization control information. Therefore, if the synchronization waiting task can recognize even the lock information at high speed, the restart of the synchronization waiting task is quick, which greatly contributes to the improvement of the performance of the parallel processing program. Therefore, only the lock information is stored in an element having an access speed higher than that of a normal CR, and only the lock information is returned to the CPU that issued the CR access request earlier than the reply data of the entire synchronization control information.

[0043]

According to the present invention, there is provided a multiprocessor employing a CR synchronous control system, comprising: a CR main unit in a CR unit for holding synchronous control information corresponding to each CS in each CR area; , A lock information holding unit in a CR unit that holds only lock information in synchronization control information in each CR area in the CR body (FIG. 1). 2 and a CR acquisition information holding unit (FIGS. 1 and 2) in a CR unit that holds information indicating whether or not each lock information in the lock information holding unit has been acquired. 2) and a CR unit for the CR unit.
An R access request is issued, and only the lock information for the CR access request is received before the entire synchronization control information for the CR access request.
If the information indicates permission to use S, each CPU that starts execution of the process using the CS, and a CR access request from each CPU, receives a CR access request from the CR area, and And a CR control unit in a CR unit that controls to return only the lock information in the synchronization control information to each CPU at a timing earlier than the reply data of the entire synchronization control information.

[0044]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

[0045]

FIG. 1 is a block diagram showing a configuration of a multiprocessor according to an embodiment of the present invention.

The multiprocessor of this embodiment has a plurality (here, n + 1) of CPUs 100-0 to 100-n (hereinafter, an arbitrary CPU is denoted by reference numeral "100").
The same applies to other codes), and n + 1 signal lines 200
, N + 1 data lines 300 and n + 1 signal lines 4
00, n + 1 data lines 500, and a plurality of CPUs 1
CR unit 600 shared by n + 1
It is configured to include three signal lines 700, a memory 800, and n + 1 signal lines 900.

Each CPU 100 issues a CR access request to CR unit 600, and upon receiving a CR reply lock bit from CR unit 600 in response to the CR access request, simultaneously receives a CR reply lock bit V bit After confirming the validity of the CR reply lock bit, it is determined based on the CR reply lock bit whether or not the CS associated with the CR access request is usable, and is determined to be “usable”. In this case, the CS is acquired and the execution of the process related to the CR access request is started.

Each CPU 100 sends a CR access request (TS
(A request by a CR command, a CR write command, and a CR read command). If the instruction related to the CR access request is a TSCR instruction or a CR write instruction,
CR write data is sent from each CPU 100 to the CR unit 600 via each data line 300. here,
It is assumed that CR write data for the CR unit 600 is folded in half and issued twice.

When each CPU 100 reads the synchronization control information from the CR unit 600 by the TSCR instruction or the CR read instruction, the lock bit is advanced through each signal line 400, and all the CR bits are subsequently transmitted through each data line 500. Read data is sent. The reply (lock bit or all CR read data) is transferred to CR60.
0 to each CPU 100, each signal line 7
At 00, a timing signal (reply control signal) is transmitted.

Each CPU 100 shares the memory 800, and can access the memory 800 by each signal line 900. However, the access speed to the memory 800 is lower than the access speed to the CR unit 600.

From the plurality of CPUs 100, other CPUs 1
A CR access request can be issued regardless of the state of 00. Note that here, for simplicity of explanation,
From a certain CPU 100, 1 request-1 reply C
Assume that an R access request is issued. However, each CP is not limited to one request and one reply.
This can be dealt with by providing a buffer in the U100 or the CR unit 600.

FIG. 2 is a diagram showing an example of the configuration of a CR unit 600 having a characteristic structure in the multiprocessor of this embodiment.

The CR unit 600 includes: a CR access request register 1 corresponding to each CPU 100;
Each CR write data reception register 2 corresponding to the PU 100, each CR write data holding register 3, corresponding to each CPU 100, a CR address register 4, a CR write data register 5, a CR body 6, and a CR read data register 7 And a lock bit register 8 corresponding to a lock information holding unit, and a C bit corresponding to a CR acquisition information holding unit.
R acquisition information register 9, CR control unit 10, each CPU
100, each CR reply lock bit F / F12 corresponding to each CPU 100, each CR reply data V bit register 13 corresponding to each CPU 100, and each C reply lock bit F / F12 corresponding to each CPU 100.
Each CR reply data register 1 corresponding to PU100
4 and selectors 15 to 17.

The CR access request register 1 is a register for storing request control information relating to a CR access request from the corresponding CPU 100 via a signal line. The contents of the request control information include a valid bit (a bit indicating whether or not valid request control information exists), a request command (information indicating the type of the command of the CR access request), and a CR address (CR access request). (Information for specifying the CR area in the CR to be requested). The request control information in the CR access request register 1 is held until the CR unit 600 processes the CR access request related to the request control information. The holding instruction is issued from the CR control unit 10 via a signal line.

The CR write data receiving register 2 stores C
This register accepts CR write data related to the R access request. According to the present invention, since the access time of a part of the CR reply data is improved, one word is divided into the U (Upper) side and the L (Lower) side for the CR write data in consideration of hardware cost reduction. There is no effect even if control is performed in two cycles. Therefore, CR write data receiving register 2 receives and stores 1/2 word data.

The CR write data holding register 3 stores the CR
This buffer stores the contents of the write data reception register 2 for one word, aligned with the U side / L side, and holds the contents until the processing of the CR access request related to the CR write data is completed. The holding instruction is issued by the CR control unit 1.
This is performed from 0 through a signal line.

The CR address register 4 includes a selector 15
, The CR address in the request control information in the predetermined CR access request register 1 is fetched and stored.

The CR write data register 5 is provided with a predetermined CR write data holding register 3 via a selector 16.
Fetch and store the contents of

Here, the control of the selector 15 or the selector 16 for designating the “predetermined” CR access request register 1 or the CR write data holding register 3 is performed by an instruction from the CR control unit 10 via a signal line. .

The CR body 6 has a RAM (Rand) storing data of 64 bits × 256 words (not to mention limited to such numerical values).
omAccess Memory). Each CR area (an area for one word) holds synchronization control information having all bits.

The CR read data register 7 is a register for storing a value (synchronization control information) of a CR area in the CR body 6 specified by the CR address specified by the CR address register 4.

The lock bit register 8 is 1 bit × 2
It is an F / F group of 56 words, and is constituted by each F / F corresponding to each word of the CR body 6. C which is RAM
Unlike the R main body 6, the access speed is high, and data can be sent to the reply exit to each CPU 100 in one cycle.

The CR acquisition information register 9 is 1 bit × 2
It is an F / F group of 56 words, and is constituted by each F / F corresponding to each word of the CR body 6. Multiple CPUs 1
It has control information (CR acquisition information) for arbitrating the timing so that the control of reading the lock bit by the CR access request from 00 is not processed at the same time.

The CR control unit 10 performs overall control of the inside of the CR unit 600.

CR reply lock bit V bit F / F
F / 11 holds a flag (CR reply lock bit V bit) indicating whether or not a CR lock bit as a valid reply to the corresponding CPU 100 exists.
F. When this flag is lit (when information indicating that a valid CR reply lock bit is present is set), the CR reply lock bit V bit F /
CR reply lock bit F / F12 corresponding to F11
Indicates that valid data exists.

The CR reply lock bit F / F12 is
This is an F / F for storing a lock bit (lock information) previously sent to the corresponding CPU 100, and holds a value read from the lock bit register 8 via a signal line. This transfer (lock bit register 8 to CR
The transfer of the lock bit to the reply lock bit F / F12) can be performed simultaneously unless the lock bits are related to the same CR address.

CR reply data V bit F / F13
Is a flag (C indicating whether or not CR reply data as a valid reply to the corresponding CPU 100 exists.
F / F holding R reply data (V bits).
When this flag is lit (when information indicating that valid CR reply data exists) is set,
This indicates that valid data exists in the CR reply data register 14 corresponding to the reply data V bit F / F13.

The CR reply data register 14 is a register for holding CR read data (synchronous control information having all bits) as CR reply data for the corresponding CPU 100. The difference from the lock bit register 8 is that the access speed is low and that only one piece of reply data can be read in one cycle even if the CR address is different. The CR reply data register 14 controls to divide the CR read data read into the CR read data register 7 into two parts, U side / L side, and send it to the CPU 100 as CR reply data. The selection of the U side / L side is controlled by the selector 17.
Done by

The selector 15, as mentioned above,
This is a selector for selecting one CR address from n + 1 CR addresses based on an instruction from the CR control unit 10.

The selector 16 is, as mentioned above,
A selector for selecting one CR write data from n + 1 CR write data (U side or L side) based on an instruction from the CR control unit 10.

The selector 17 is, as mentioned above,
This is a selector for selecting one of the U side and the L side of the CR read data.

FIGS. 3 and 4 are time charts for explaining a specific operation of the multiprocessor of this embodiment.

Next, the operation of the multiprocessor of this embodiment thus configured will be described with reference to FIGS. It should be noted that the overall control of the following operation in the CR unit 600 is performed even if the CR unit 600 is not specified.
This is performed by the control unit 10.

First, referring to FIG. 3, a plurality of CPUs 1
CR for CR area of same CR address from 00
The operation when access requests conflict will be described.

As shown in FIG. 3, C by the TSCR instruction
An R access request (a CR access request for a CR area having the same CR address) is transmitted between the CPU 100-0 and the CPU 10.
From 0-1 to the CR unit 600, where C
It is assumed that a CR access request from PU 100-0 arrives one cycle earlier in a cycle.

The CPU 100-0 issues a CR access request based on the TSCR instruction. CR of this TSCR instruction
The designation of the address is “# 3”.

On the other hand, the CPU 100-1 also issues a CR access request by a TSCR instruction having a CR address designation of "# 3" one cycle later.

In the cycle, the CR in the CR unit 600
The request control information of the CR access request from the CPU 100-0 that has reached the access register 1-0 is held in the CR access register 1-0 until the cycle for the subsequent access processing to the CR body 6.

Further, the CR write data relating to the CR access request is divided into two times on the U side / L side and
From 00-0, the data is transferred to the CR write data receiving register 2-0, and stored in the CR write data receiving register 2-0 at the timing of the cycle.

Further, the CR write data is stored in the CR write data holding register 3-0, and is held until the cycle for the same reason as holding the request control information of the CR access request.

Similarly, in the cycle, the CR unit 600
CPU 10 that has reached CR access register 1-1
The request control information of the CR access request from 0-1 is held in the CR access register 1-1 until the cycle for the subsequent access processing to the CR body 6.

Further, the CR write data relating to the CR access request is divided into two times on the U side / L side and
00-1 is transferred to the CR write data reception register 2-1 and stored in the CR write data reception register 2-1 at the cycle and timing.

Further, the CR write data is stored in the CR write data holding register 3-1 and is held until the cycle for the same reason as the holding of the request control information of the CR access request.

In this embodiment, as described above, a CR access request from a certain CPU 100 is one request-
Since the control is performed by the one-reply method, there is no fear that the retained request control information and the CR write data are destroyed by the subsequent CR access request (when a control method other than the one-request-one-reply method is employed). A buffer can be provided to prevent the "destruction" described above.)

As described above, C from the CPU 100-1
Since the R access request was one cycle later than the CR access request from the CPU 100-0, the CPU 100-0
While the process related to the CR access request is being performed, only the request control information is held, and the process waits for the start of the process related to the own CR access request.

Further, since the processing related to the CR access request from the CPU 100-0 has priority over the processing related to the CR access request from the CPU 100-1, the CR control unit 10 determines whether the CR access request from the CPU 100-0 has arrived. As an opportunity, F / # 3 of CR acquisition information register 9
F (F / F corresponding to # 3 CR address in CR body 6)
The setting of F) is performed in a cycle. By this operation,
C that accesses the CR area of the same CR address (# 3)
It arbitrates contention with the processing related to the CR access request from the PU 100-1. That is, in the cycle, which is the processing period of the CR access request of the TSCR instruction from the CPU 100-0, the F / F
F (indicated by “CR acquisition F / FCR # 3” in FIG. 3) is set and reset in a cycle. Upon seeing this reset state, the processing relating to the CR access request from the CPU 100-1 is started, and the CR acquisition F
/ FCR # 3 is set.

On the other hand, in the cycle, the CR address is #
The lock bit in the synchronization control information of the CR area 3
Ready to send to PU100-0. That is, the F / F of # 3 in the lock bit register 8
The value of F (indicated by "CR lock bit F / FCR # 3" in FIG. 3) is transferred to CR reply lock bit F / F12-0, and the validity of the lock bit is determined by CPU1.
CR reply lock bit V bit F / F1 of CR reply lock bit V bit for recognizing 00-0
The setting to 1-0 has also been completed. In this manner, the control for "returning the reply regarding the lock information to the CPU earlier", which is the object of the present embodiment and the present invention, is realized.

The CPU 100-0 has a CR unit 600.
The validity of the CR reply lock bit received from is checked by the CR reply lock bit V bit received at the same time, and it is determined whether the lock bit is 0 or 1. Then, when the lock bit is 0, the C related to the CR access request is
Recognizing that S is usable, it acquires the CS and starts executing the process related to the CR access request.
If the lock bit is 1, the CR
It recognizes that the CS relating to the access request is unusable, and enters a spin lock state.

In the subsequent cycles, the CPU 10
Control regarding CR reply data including all of the synchronization control information other than the lock bit for 0-0 is performed.

First, a process for reading the value (synchronization control information) of the CR area having the CR address # 3 from the CR body 6 is performed. CR access request register 1-
The CR address (# 3) in the request control information held at 0 is stored in the CR address register 4 in a cycle, and the C address specified by the CR address of the CR body 6 is
The CR data (synchronization control information) in the R area is held in the CR read data register 7 for a period of up to. The reason why the data is held for two cycles is that, similarly to the case where a CR access request is received from each CPU 100, when the CR reply data is returned to each CPU 100, the control is performed by dividing the data into two U / L sides.

The U-side / L-side data of the CR read data read from the CR body 6 to the CR read data register 7 are stored in the CR reply data register 14-0 in cycles and in the CPU 100-0, respectively. On the other hand, the CR reply data is transmitted twice. In this cycle and at the same time, the CR reply data V bit, which is a signal indicating the existence (validity) of the CR reply data, is set to the CR reply data V bit F / F13-0. At this stage, the processing related to the CR access request from the CPU 100-0 ends.

Next, processing related to the held CR access request from the CPU 100-1 is started from the cycle.

CR acquisition F / reset in cycle
Based on FCR # 3, in the cycle, the lock bit of CR lock bit F / FCR # 3 is set to CR reply lock bit F / F12-1, and the lock bit is earlier than all the synchronization control information (CR reply data). Is sent to the CPU 100-1. At this transmission timing, the CR reply lock bit V bit F / F1
CR reply lock bit V indicating "valid" to 1-1
The bit is set.

Thereafter, similarly to the control for the CPU 100-0, CR reply data other than the lock bit is also sent to the CPU 100-1.

Second, referring to FIG. 4, a plurality of CPUs 1
CR for CR area of different CR address from 00
The operation when access requests conflict will be described.

As shown in FIG. 4, C by the TSCR instruction
An R access request (a CR access request for a CR area having a different CR address) is transmitted between the CPU 100-0 and the CPU 10
From 0-1 to the CR unit 600, where C
It is assumed that a CR access request from PU 100-0 arrives one cycle earlier in a cycle.

As shown in FIG.
At this time, a CR access request (CR access request by a TSCR instruction) from the CPU 100-0 to the CR area having the CR address “# 4” arrives in a cycle, and
It is assumed that a CR access request (CR access request by a TSCR instruction) from 0-1 to a CR area having a CR address “# 5” arrives in a cycle.

At this time, in the cycle and
The R reply lock bit is set between CPU100-0 and CPU1.
00-1. The reason is that C
CR arrived from PU100-0 and CPU100-1
This is because the CR area to be accessed in the access request is different.

However, since the CR reply data other than the lock bit must be read out from the CR main unit 6 which is a RAM, the CR reply data from the preceding CPU 100-0 is output.
Until the processing related to the access request ends, the subsequent CP
It is necessary to wait for the process related to the CR access request from U100-1. As a result, the CPU 100-1
The transmission timing of the CR reply data is delayed until the cycle.

However, in the present embodiment, and eventually in the present invention,
As described above, since only the lock bit is advanced in the cycle for the CPU 100-1, a decrease in access performance can be avoided.

[0101]

As described above, according to the present invention,
In a multiprocessor in which synchronous control is performed by the CR access control method, even when a parallel processing program with a small task granularity is executed, there is an effect that a performance reduction due to the synchronous control can be avoided.

That is, by using an element with a short access time, such as F / F, for holding only lock information in the CR unit, it is advantageous in terms of circuit mounting, and a reply with only lock information is returned to the CPU quickly. be able to. When examining the behavior of a real program, it is easy to know what the value of the lock information is.
In many cases, the task waiting for the establishment of the synchronization in the U can be restarted earlier. Therefore, the advancement of only the lock information has the effect of avoiding the performance degradation associated with the synchronization control as described above. Will occur.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a multiprocessor according to the present invention.

FIG. 2 is a diagram illustrating an example of a configuration of a CR unit in FIG. 1;

FIG. 3 shows a CR having the same CR address from a plurality of CPUs.
FIG. 10 is a diagram showing a time chart for explaining control timing when a CR access request for an area competes.

FIG. 4 shows CRs having different CR addresses from a plurality of CPUs.
FIG. 10 is a diagram showing a time chart for explaining control timing when a CR access request for an area competes.

FIG. 5 is a diagram showing an example of the specification of a TSCR instruction.

FIG. 6 is a diagram for describing an outline of an operation of a conventional multiprocessor (a multiprocessor employing a CR synchronization control method).

FIG. 7 is a diagram for describing an outline of an operation of the barrier synchronization control method.

[Explanation of symbols]

 1 CR access request register 2 CR write data reception register 3 CR write data holding register 4 CR address register 5 CR write data register 6 CR body 7 CR read data register 8 Lock bit register 9 CR acquisition information register 10 CR control unit 11 CR reply Lock bit V bit F / F 12 CR reply Lock bit F / F 13 CR reply data V bit F / F 14 CR reply data register 15-17 Selector 100 CPU 200, 400, 700, 900 Signal line 300, 500 Data line 600 CR unit 800 memory

Claims (3)

[Claims] 1. A multiprocessor adopting a CR synchronization control method, wherein: a CR body in a CR unit for holding synchronization control information corresponding to each CS in each CR area; and an element having an access speed higher than that of the CR body. A lock information holding unit in the CR unit that holds only lock information in the synchronization control information in each CR area in the CR body; and each lock information in the lock information holding unit is acquired. A CR acquisition information holding unit in the CR unit that holds information indicating whether or not there is a lock request, issues a CR access request to the CR unit, and stores only lock information for the CR access request as a whole synchronization control information for the CR access request Earlier, and if the lock information is information indicating permission to use the CS, execution of the process using the CS is performed. Each C to start
PU, and upon receiving a CR access request from each of the CPUs,
A CR control unit in a CR unit for controlling to return only the lock information in the synchronization control information in the CR area requested by the R access request to each CPU at a timing earlier than the reply data of the entire synchronization control information. A multiprocessor comprising: 2. The multiprocessor according to claim 1, wherein the lock information is a lock bit of one bit information. 3. A CR access register, a CR write data receiving register, a CR write data holding register, a CR address register, a CR write data register, a CR body, a CR read data register, and a lock information holding unit. The corresponding lock bit register and CR
A CR acquisition information register corresponding to an acquisition information holding unit;
A CR unit including an R reply lock bit V bit F / F, a CR reply lock bit F / F, a CR reply data V bit F / F, a CR reply data register, and a CR control unit; Issuing a CR access request to the CR unit;
In response to the CR access request, the CR unit
Upon receiving the R reply lock bit, the validity of the CR reply lock bit is checked by the simultaneously received CR reply lock bit V bit, and then the CS related to the CR access request is used based on the CR reply lock bit. It is determined whether it is possible or not, and if it is determined that it is “usable”, each CS that acquires the CS and starts execution of the process related to the CR access request
The multiprocessor according to claim 1, further comprising a PU.