JPS60252977A - Information processor - Google Patents

Abstract

PURPOSE:To facilitate the expansion and alteration of system configuration by addressing each processor of a multiprocessor system and giving functions of a processor and functions of an input/output processor. CONSTITUTION:In the information processor of a multiprocessor system including processors of different architecture, plural processors MPU/IOP-112-MPU/ IOP-N15 of different architecture are made to function as input/output processors in the idle state, and at the same time, processor switching functions are given to a bus arbiter 11. Thus, addition of any processor card to the system becomes easy, and a system laways compatible from the high order can be constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device for a multiprocessor system including processors of different architectures, and in particular, the present invention relates to an information processing device for a multiprocessor system including processors of different architectures, and in particular, to an information processing device for a multiprocessor system including processors of different architectures. The present invention relates to an information processing device equipped with intelligent bus dominance control means.

(Prior Art) Conventional small-sized information processing devices are usually configured as a single Bromo/7S system.

In that case, the software that could be used was limited to one type for that processor. However, recently, processors with various architectures have become popular, and various types of software have been created for these processors.

Therefore, there is an increasing need to expand the range of software that can be used in information processing devices, and information processing devices with multiprocessor systems in which processors with two or more different architectures coexist are now common.

FIG. 2 shows an example of the configuration of such an information processing device. In the figure, 1 is a bus arbiter, 2 and 3 are processors MPU-A and MPU-B of different architectures, and 4 and 5 are different architectures. architecture input/output processors l0P-A and l0P-B;
6 is main memory.

7 and 8 are input/output devices 1110.9 is a bus direct connection type D
MA controller DMAC, 10 indicates a system bus.

Except for the DMA transfer operation of the DMA controller DMAC9, data transfer via the system bus 10 is performed as follows.
The processor MPU-A or MPU-B functions as a bus mask and controls the bus. Bus arbiter 1 is processor MP
It adjusts conflicts between requests for bus usage rights by U-A and MPU-B, that is, controls the setting of bus dominance.

When processor MPU-A or MPU-B performs input/output processing, a specific input/output Bromo Nosa l0P-A
Alternatively, l0P-B is designated from the register and a request for processing is made.

[Problem that the invention seeks to solve]

The information processing device of the Multibromo 7S system, in which multiple processors with different architectures coexist, is
Due to differences in the bus structure, memory space, file structure due to differences in O8, multitasking methods, etc. of each processor, there are many restrictions on the interface between input and output devices, etc. There was a problem in that the IPL processing and interrupt reception processing for each processor were complicated and difficult to use.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention enables processing of multiple processors with different architectures in their idle (vacant) state.
In the state, the bus control means (bus arbiter) can function as an input/output bromo/7 bus and has a processor switching function.
In an information processing device of a multiprocessor system including main memory means, bus mastership control means, and input/output means, each processor means is assigned an address and has an original processor function and an input/output processor function. The lotus control means is configured to function as an input/output processor in an idle state according to an instruction from the lotus control means, and the lotus control means further includes a processor address register for specifying an address for one processor.

a processor command/status register that notifies a command that instructs the specified processor to perform the original processor function or the input/output processor function, and a status that displays the processing status of IPL or interrupt, etc.; It is equipped with a switching register that starts execution of processor switching and an interrupt register that instructs switching of the processor for interrupt processing, and each processor can equally access each of the above registers in the lotus control means, Specify to switch between the other processors accordingly.

In addition, the input/output processor is specified according to the contents of the job and automatic switching by interrupt is specified, and the bus control unit @control unit controls the switching of the processor according to the specified contents. It is something.

[Effect]

By means of the present invention, it is possible to control the lotus control and at the same time easily select a processor that matches the currently operating processor and operate it including interrupt processing and DMA functions.

〔Example〕

The details of the present invention will be explained below based on two examples.

FIG. 1 is an overall configuration diagram of one embodiment of the present invention.

In the figure, 11 is a lotus arbiter, 12 to 15 are a processor MPtJ19 and a processor 10PPa, respectively.
BLI seso tMPU/10P-1 to MPU with
/10P-N, and 16 is the main memory.

17 and 18 are input/output devices 110, 19 is a direct connection type DMA controller DMAC, 20 is a system hash, 1
3a and 15a represent MPU-directly connected DMA controllers DMAC.

Processors MPU/10P-1 to MPtJ/! 0P-
N is under the control of the bus arbiter 11.

It operates as an MPU when specified as an MPU Hasmask, and when it is in an idle state, the MPU
on instructions from or in response to an interrupt request.
It operates as an OP and becomes a 2-lot master.

The DMA controller is of MPU direct connection type 133.
15a and the bus-direct type 19 are allowed, but higher priority is given to the latter.

The lotus arbiter 11 performs bus mastership control.

In particular, the present invention allows idle processors to
It also has a function to switch the processor that handles interrupt processing to operate as an MPU or IOP when a 9-interrupt request is made.

The lotus arbiter 11 controls lotus control.

There are four types of sequences: In other words, there is a system startup sequence in which each processor is sequentially cleared or IPLed when the power is turned on, a bus mastership arbitration sequence in which bus mastership is determined in the event of a conflict between multiple bus masks, and an interrupt processing processor is activated when necessary when a single interrupt request is made. These are an interrupt sequence for switching, and an IOP switching sequence for switching an idle processor to an input/output processor in response to a request from an operating processor.

FIG. 3 is a detailed configuration diagram of the lotus arbiter 11 in the embodiment system shown in FIG. In the figure.

21 is a priority encoder, 22 is a demultiplexer, 23 is a register file that selects a processor corresponding to an interrupt, 24 is a timer, 25 is an interrupt register that determines whether or not interrupt processing involves processor switching, and 26 is a processor Processor command/status register PC that specifies the state when switched
3R, 27 is a processor switching register PEXR for instructing processor switching, and 28 is a processor address register PADR for specifying a processor.

29 represents a D latch, 30 represents a ROM storing control firmware, and 31 represents a D latch. The contents of the symbols representing the signals are as follows.

BRO~3 Bus control request BG Lotus permission BGADO~2 Lotus permission address BGEP Processor lot grant BRLS Lotus release request BBSY Bus busy BCLK Constant clock I RQ7~0 Interrupt request IPLO~2 Encode interrupt request Priority encoder 21 is input from the outside. The interrupt request signal (IRQO to IRQO7) is converted to an interrupt level, and the level with the highest priority is selected and supplied to the demultiplexer 22.

The demultiplexer 22 encodes the selected interrupt level according to the value stored in the interrupt register 25.
) to the operating processor MPU/I○P, or to the register file 23 in order to select another processor for interrupt processing.

The register file 23 stores in advance a table indicating the addresses of processors that perform interrupt processing corresponding to one interrupt level, and is supplied to the processor address register 28 as processor selection information.

The timer 24 is provided to prevent one processor from occupying the lotus for more than a certain period of time and remaining in a halt state. An interrupt request with a priority level is generated to reduce the probability of system failure.

Interrupt register 25 is populated to specify whether it is necessary to switch processors for one interrupt handling.

Processor command/status register PC3R26
If the processor to be switched has an MPU or IOP
This is a register for notifying commands for instructing whether to function in any of the following, and statuses such as cold start IPL and interrupt 2 interrupt completion.

The switching register PEXR27 is used as a processor command/status register PC3R26 and a processor address register PAD when switching processors.
It is used to instruct the start of execution of switching when a set of necessary information such as R28 is ready.

Processor address register PADR28.

Used to specify the address of the processor to be switched. IOP from the MPU bus mask currently in use
Either the processor address specified as (via the system bus) or the interrupt processing processor address read from the register file 23 is set. If the processor address is set in the register file 23 at the same time as the MPtJ hasmask designates the IOP, the IOP can immediately respond to an interrupt request from an input/output device.

The ROM 30 stores a control logic table for lotus control. The D latch 29 receives the bus mastership request signal (BRO~3) and the processor address register PAD.
The processor address from R28 is set and the RO
Used to access M30. D latch 31
is the control signal (BG, BGE) output from ROM30.
P, BGADO~2. BRLS) is used to temporarily hold the BRLS.

Next, the four lotus control sequences described above by the Nihas arbiter 11 will be sequentially explained with reference to the configuration shown in FIG.

(1) System startup sequence After turning on the power, it immediately enters the startup sequence.

Outputs BG, BGEP, and BGAD of the D latch 31.

All BRLSs are in a negated state or inactive level. When the reset is released, BGEP becomes active, and the processor addressed to "000" initializes the system. If a processor equipped with a cache memory is installed in the system, the cache memory is also cleared.

The lotus arbiter 11 sets the processor command/status register PC3R26 to "IPL", sequentially switches the processors, and hands over the lotus control. The processor that has received control of Hasmask, that is, Hasmask,
After initializing himself, he returns control of the lotus.

After the processor has handed over control of the bus, it is in an idle state with respect to the system bus.

When all the installed processors have been initialized, the processor at address "000" takes control of the bus and reads the bootstrap.

After that, the bootstrap data is analyzed to find out, for example, the type of language used, one corresponding processor is identified using a preset correspondence table, and its address is stored in the processor address register. A
DR28 is set, the status is set to "cold start" indicating that the power is turned on, and the processor command/status register PC3R26 is set to switch the processor. This switched processor becomes the Hasmask.

In this way, based on the bootstrap read by the "000" processor, a suitable processor can be automatically selected and IPLed to operate as the first MPU bus mask.

The entire power supply startup sequence is shown in (1) to (2) below.

(2) When the system is reset, BGADO~2 points to the hash permission address "000" and all processors enter the reset state.

■ When the reset is canceled, the Hass consent address “000”
” and initializes the entire system.

Block command/status register PC3R2
G is also initialized.

■ Processor command/status register PC3R
The "IPL status" is written to 2 and the installed processor actually initializes itself.

■ When the hasmask returns to "000" for the processor, other processors are in idle mode.

■ When the bootstrap driver is read by IPL, it is determined which processor should be supported based on the bootstrap data.

■ Set the address of the corresponding processor in the processor address register PADR28.

Write “Coult Starbi” as the status and switch between Brose and Su.

(2) Bus mastership determination sequence This sequence is an existing method, in which the processor becomes the master only while there is no external request for the bus.

The entire procedure of the bus mastership determination sequence is shown in (1) to (3) below.

■ Either BRO~3 becomes active.

■ BGEP is negated and the processor relinquishes control.

■ Compare priorities and set the level with the highest priority.

■ Low-priority items use the bus and 0G'B
Output RLS.

■ After receiving BRLS, the hs master temporarily changes to BBS.
Negate Y and output BRn again.

(2) BBSY is negated, waits for the cycle to complete G, and then outputs BG and level to BCAD.

■ After confirming that the level matches his own, the bass master activates BBSY and lowers BR.

(2) If none of BRO~3 is output, the bus arbiter outputs BGEP and the contents of the processor address register to BGADO~2.

If there is a BR, the ruling will be made again.

(3) Interrupt Sequence In the interrupt sequence, there are two modes: (1) a mode in which an interrupt signal is output to the bus as usual after taking priority, and (2) a mode in which when an interrupt request is received, a specific processor processes it. In the former mode, the processor 1 that is operating normally performs the processing, but in the latter mode, the processor address corresponding to the interrupt level is set in the register file 23 in advance, and the 1 interrupt register 25 is "enabled". If one interrupt request occurs, the command is set to "interrupt" and switching to the specified processor is automatically performed. Note that the status contains the processor address before the interrupt, so it is set based on this at the end of the interrupt processing. Also, the processor sends "interrupt ended" to the return status.

The entire interrupt sequence is shown in (1) to (2) below.

■ IRQO~7 is set to active.

■ Compare the priorities and output the level with the highest priority to IPLO~2.

■ Should the interrupt register specification be changed? ■ If switching is not necessary, the processor currently operating as MPL+ handles the interrupt.

■ If switching is required in ■, set the address corresponding to the level from the register file to PADR,
Set PO3H to "interrupt" and perform PEXR operation to switch processors.

■ The specified processor handles the interrupt.

If necessary, set IOCB to cent, set PC3R to "interrupt end", switch processors, and release bus control.

(4) IOP switching sequence procedure 7 In MPtJ/IOP, there is no need to determine bus control by yourself. There are two types of states for the system bus: a mode in which the bus becomes a bus mask, and a mode in which it becomes idle. In the latter case, all elements connected to the bus are not actively driven. In the former, MPU
There are cases where it operates as an IOP and cases where it operates as an IOP, and this is determined based on the contents of the PC5R26.

In bus master/idle mode, the processor is BGE
This is determined by P and BGADO~2. That is, when BGEP is active, it compares the number assigned to itself as an address and BGADO~2.

When it matches, it becomes the bus master, and otherwise it becomes idle.

Note that if a DMA controller is mounted directly connected to MPtJ, the lotus exchange between MPLJ and DMA is performed internally, so that they appear as the same bus mask to the system bus.

Further, the processor MPU/IOP may be an intelligent controller having firmware dedicated to processing a specific input/output device. That is, as long as it is idle relative to the system bus.

This is because the local bus can be moved during the idle state.

FIG. 4 shows a flowchart of the entire IOP switching sequence.

〔Effect of the invention〕

As described above, according to the present invention, as long as the basic specifications are satisfied when designing the processor card, it is easy to add any processor card to the system, and a system that is compatible from the upper level can be constructed without fail.

Also, if you expand your previous system by adding a new Brosse Nosa card or input/output device,
There is no need to port the previous input/output processing to the expanded system; for example, when using a previous input/output processing device, it is sufficient to functionalize the previous system part, making system expansion easy.

Furthermore, when performing IPL, there is no need to change the hardware settings for each different O8, and a processor compatible with the O8 can be automatically selected by bootstrap analysis.

Note that a memory management unit is used to prevent physical address collisions, so that different processors can use different O8
It is possible to realize a bus-sharing system that runs the two in parallel. It is also possible to connect a high-speed DMA channel using the firmware processor or DMA controller in the intelligent I10 controller as a bus mask.

As described above, according to the two aspects of the present invention, the system configuration can be expanded and changed easily, and high processing efficiency can be maintained.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of an information processing device according to the present invention. FIG. 2 is a configuration diagram of an example of a conventional information processing device.
FIG. 3 is a detailed configuration diagram of the bus arbiter in the embodiment shown in FIG. 1, and FIG. 4 is a flow diagram of the IOP switching sequence. In the figure, 11 is a bus arbiter, 12 to 15 are processors MPU/IOP, 16 is a main memory, 17 and 18 are input/output devices 110, 19 is a DMA controller DMAC,
20 represents a system bus. Patent applicant Banafacom Co., Ltd.

Claims (1)

[Scope of Claim] A plurality of processor means of different architectures, main memory means, and lotus dominance control means. In an information processing device of a multiprocessor system including an input/output means, each of the processor means is assigned an address and has an original processor function and an input/output processor function, and in an idle state, the bus mastership control means The bus mastership control means is configured to perform an input/output processor function according to instructions from the input/output processor, and further includes a processor address register for specifying an address for one processor, and a processor address register for specifying an address for one processor, and for controlling the input/output processor function to cause the specified processor to perform its original processor function. a processor command/status register that notifies a command instructing whether to perform a processor function and a status displaying the processing status of IPL or interrupts, a switching register that starts execution of processor switching, and a processor for interrupt processing. The processor is provided with an interrupt register for instructing switching of the lotus control means, and each processor can equally access each of the registers in the lotus control means. The bus mastership control unit specifies switching between other processors as necessary, and also specifies input/output processors according to the content of the job and automatic switching due to interrupts. An information processing device characterized by controlling switching of processors according to content.