JPH03137756A - Information processor - Google Patents

Abstract

PURPOSE:To efficiently an AV system by controlling the use right of a system bus for respective information transmission lines and simultaneously executing data transfer which plural operation means request in the allowable range. CONSTITUTION:A CPU 1 designates the address of a memory 4, reads an instruc tion, repeats execution and proceeds a program. When there is a sound output processing in the procedure, the CPU 1 writes the address of sound data into a register to which AP 2 is concerned and gives a command to AP 2 to output sound. An AP 2 obtains the number of necessary transmission lines from a necessary data transfer quantity and gives the request of the use right of four system buses 14 to a second bus width arbitration means 10, for example. The means 10 executes arbitration by using the other bus arbitration means 9, 11 and 12 and a bus width arbitration control line 13 and obtains the use right of four buses 14. Then, means informs a second data width conversion means 6 of the obtained bus width by using a data width control line 16. The AP 2 reads sound data from the memory 4, executes decoding and outputs sound.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an information processing device that processes data. More specifically, the present invention relates to the configuration of an information processing apparatus suitable for processing audio data and video data (hereinafter referred to as AV data).

2. Description of the Related Art In recent years, as computers have become multimedia, computers have been required to have a configuration suitable for processing AV data.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A compact disc interactive system (hereinafter referred to as CD-I system, !-at.) as an example of the conventional information processing apparatus described above will be described below with reference to the drawings. The configuration of the CD-I system is basically the same as that of conventional computers, and one of the purposes of the system is to process AV data.

Figure 5 shows the literature (COMPUTER DESIGN Ja
FIG. 1 is a block diagram showing the basic parts of the CD-I system published in 1988). Please refer to the above-mentioned literature article for an explanation of the figure.

FIG. 6 is a block diagram showing a portion of FIG. 5 that is related to the present invention.

In FIG. 6, 601 to 804 are calculation means;
CM Te:l-da(AP), 80:HlDMA:yn)o
This is a memory composed of -RA (DMAC), GOJitDRAII, etc. Ei05 to G08 are each calculation means 6
01 to 604 correspond to bus arbitration means for controlling the right to use the system bus; 6o3 is each bus arbitration means 805 to 60;
8 is a bus arbitration control line through which information is mutually exchanged in order to proceed with bus arbitration, and 810 is a system bus. In this figure, the address bus is omitted and only the 8-bit width data bus is shown. In actual CD-I systems, the width of the data bus is 18 bits. The memory is also connected to the system bus via an image memory access controller (509 in FIG. 5), and bus arbitration means is included therein. 811 is APGO2 data buffer 1
Al in the data buffer used for the ring.

The operation of the information processing apparatus configured as described above will be described below.

First, the system control program executed by the CPU 5ot is stored in the memory 804. CPUGOI is memory 8
The program advances by specifying address 04, reading and executing instructions, and repeating the process.

In the process, if there is a process to decode the data on the memory 604 and output it as audio, the CPUGOI writes the address of the data to be output into the corresponding register of the AP 602, and then instructs the APGO2 to start the process. AP GO2 requests the right to use the system bus 610 from the second bus arbitration means 80B. The second bus arbitration means 80G is connected to the other bus arbitration means 805. After making adjustments according to the procedure determined by fi07, the system bus 8
10 and informs APC02 that it has obtained the usage right. After the AP 802 transfers the data to be decoded from the memory 804 to the buffer IEII, the AP 802 instructs the second bus arbitration means B08 to release the right to use the system bus 61G, and ends the series of operations. Memo!
When data transfer within the 7804 is required, the DMAC 803 obtains the right to use the system bus using the same procedure and reads and writes data in the memory (f04).

Problems to be Solved by the Invention However, in the above configuration, the right to use all system buses is switched at the same time.
It had the following issues, such as when transferring data in synchronization.

(1) A data buffer is required to transfer audio data and video data separately and play them back at the same time.

(2) Alternatively, in order to realize simultaneous transfer, it is necessary to separately provide a dedicated bus for each data.

In view of the above problems, it is an object of the present invention to provide an information processing device suitable for processing AV data without requiring a data buffer or providing a dedicated bus for each data.

Means for Solving the Problems In order to achieve the above object, the information processing device of the present invention includes a system bus consisting of a plurality of calculation means, a plurality of information transmission lines, and a data transfer system required by each of the calculation means. bus width arbitration means for allocating a number of information transmission lines commensurate with the rate to each arithmetic means; and a plurality of data width conversion means for converting input and output data of each arithmetic means into respectively assigned data. It is something that

Effect of the present invention With the above-described configuration, the right to use the system bus is controlled for each information transmission line, and within the permissible range,
Data transfers requested by multiple calculation means are executed simultaneously.

Embodiment Hereinafter, an information processing apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an information processing apparatus in an embodiment of the present invention. 1 to 4 are calculation means, in which 1 is a CPU and 2 is an ADPCM decoder (A
P), 3 is a DMA controller (DIAC), and 4 is a memory. 5 to 8 are data width conversion means allocated to calculation means 1 to 4, respectively, and 9 to 12 are calculation means 1 to 4, respectively.
4, 13 is each bus width arbitration means 9 to 1.
2 is a path width arbitration control line for mutually exchanging information in order to proceed with bus width arbitration, and I4 is a system bus. Here, the address bus is omitted and only the data bus of 8 bits is shown. ! 5 to 1B are each path width arbitration means θ to I2
This is a data width control line for informing each data width converting means 5 to 8 of the width of the bus that has been acquired.

FIG. 2 is a block diagram showing an example in which each data width conversion means 5 to 8 and each bus width arbitration means 9 to 12 shown in FIG. 1 are constructed using a microprocessor. 20! 202 is a microprocessor, 202 is a program ROM 1203 is a first I
10 latch circuit, 204 is the second I10 latch circuit, 2
05 is Memo 1c 206 is bus arbitration system i-line I/F 12
07 is an internal system bus. In FIG. 2, the data width conversion means and the bus width arbitration means are implemented in one system, so the data control lines 15 to 18 shown in FIG. 1 do not exist.

Figure 3 shows step 1 of realizing the function of the data width conversion means.
Figure 4 is a pad diagram showing an example of the procedure by which each bus width arbitration means controls the allocation of the system bus. It can also be realized as a single system using a microprocessor, as shown above. In that case, the microprocessor proceeds with the two procedures in parallel in a time-sharing manner.

Regarding the information processing device configured as described above, the following describes
The operation will be explained using figures.

First, a system control program executed by the CPU is stored in the memory 4. The CPU 1 specifies the address of the memo I74, reads and executes instructions, and advances the program.

In the process, if there is audio output processing, the CPU 1 outputs data as audio (hereinafter referred to as audio data).
After writing the address in the corresponding register of AP2, it issues an instruction to AP2 to perform audio output. AP
2 determines the required number of transmission lines from the required data transfer amount, and requests the second bus width arbitration means 10 for the right to use, for example, four lines of the system bus 14. The second bus arbitration means 10 is connected to the other bus arbitration means 9. 11. 12 and the bus width arbitration control line 13, the system bus is adjusted according to a predetermined procedure, and the right to use the four system buses is obtained. 1B
The obtained bus width (
In this example, 4) will be notified. AP2 reads audio data from memory 4 and performs processing such as decoding,
Output as audio. At this time, the audio data recorded in the memory 4 in 8-bit width is converted into 4-bit width by the fourth data width converting means 8 and is placed on the system bus 14. AP
2 receives the data reconverted into 8 bits by the second data width conversion means 6, performs processing such as decoding, and outputs it as audio. After the audio output is completed, the AP 2 issues an instruction to the second bus arbitration means 10 to release the right to use the system bus 14, and the series of operations ends. In parallel with the above series of processing, when the CPU 1 needs to transfer (copy) a certain part of the memory 4 to another part using the DMAC 5, the CPU 1 sends the DMAC 5 the start address of the transfer source and the transfer destination. After setting the start address, transfer amount, etc., instruct the start of transfer. The DAMC 3 requests the third bus width arbitration means 11 for the right to use the system bus.

The third bus width arbitration means II is connected to other bus width arbitration means 9゜10.
, 12 and bus width arbitration control line 13 according to a predetermined procedure, obtains the right to use the remaining four system buses, and notifies the DMAC 5 that the right to use them has been obtained. 3rd using the data width control line 17.
The bus width (in this example, 4) acquired in the data conversion means 7
book). The DMAC 5 reads data from the memory 4 and sequentially transfers the data to the memory 4 until the specified transfer amount is reached.
Proceed to write to another address. At this time, the data read from the memory 4 is transferred to the fourth data width conversion means 8.
The data is once converted to a 4-bit width, transferred using four system buses, reconverted to an 8-bit width by a third data width conversion means, and read into the DMAC 5. When writing to other addresses in the memory 4, the reverse procedure is followed.

Next, each data width conversion means 5 to 8 and bus width arbitration means 9 to
An example of the internal operation of 12 will be explained with reference to the drawings. For convenience of explanation, the entire block shown in FIG. 2 will be referred to as a subsystem hereinafter. Microprocessor 201 controls the operation of the entire subsystem. The operating procedure of the microprocessor 201 is recorded in the program ROM 202. 1st I1
The 0 latch circuit 203 loads 8-bit width data from each calculation means onto the internal system bus 207, and transfers 8-bit width data on the internal system bus 207 to each calculation means. The second I10 latch circuit 204 loads data with a width of 8 bits or less from each bus width arbitration means onto the internal system bus 207, and transfers data on the internal system bus 207 to each calculation means with a width of 8 bits or less. do. If the width of the data is 8 bits or less, the remaining lines of the internal system bus have no meaning and are fixed to, for example, "l, II. The microprocessor 201 converts the width of the data (
For example, 8-bit width data is converted into two 4-bit width data. ), the data is temporarily held in the memory 205. Further, the microprocessor 201 exchanges information with other subsystems via the bus width arbitration control line I/F 20G in order to mutually arbitrate on the bus.

Next, referring to FIG. 3, a procedure in which the above subsystem functions as a data width arbitration means will be explained.

The program shown in FIG. 3 (hereinafter referred to as program A).

) continues to run as long as there is a data transfer request, as shown in child chip 302. Step 303 is to determine whether there is a specification on the bus, and if there is no specification, step 304. An 8-bit width bidirectional data transfer indicated by 305 is executed. If there is a specification on the bus, the specified data is read in step 306. Here, in the designated data, each bus width arbitration means 9
~! In this example, the functions of the bus width arbitration means 9 to 12 are specified by another program (hereinafter referred to as program B) that is executed on the same microprocessor shown in FIG. ), actual reading is performed via a predetermined area on the memory 205 in FIG. Step 307 shows a loop that is executed while data is being received, and if it is determined in step 308 that the data is destined for each calculation means 1 to 4 from the system bus, step 311. As shown at 312, the data is converted into 8-bit width and transferred to each calculation means 1-4. If the data is in the opposite direction, step 309;
As shown at 310, the 8-bit width data is converted into specified data and transferred to the system bus.

Next, a procedure in which the above subsystem functions as the bus width arbitration means 9 to 12 will be explained using FIG. Step 402 indicates that program B continues to run while the system is running. Step 403 determines whether there is a bus request. If there is no bus, it is determined in step 404 whether the bus is currently being used.

If it is being used, the process returns to step 402 and continues execution. If the bus is not in use, it is determined in step 405 whether the bus is secured, and if it is, it is released in step 40G, and if it is not, the process returns to step 402. If there is a bus request in step 403, first, in step 407, the process waits in step 408 while the destination to be connected is busy.

Once the connection is possible, it is determined in step 403 whether the required number of buses can be secured, and if it is possible,
After securing a bus in step 410 and notifying each calculation means of this in step 411, steps 404 and 40
5. 401i. If the bus cannot be secured in step 409, step 412. As shown in step 413, it continues to wait until it becomes possible, and if it becomes possible, performs the mediation operation in step 414, and then proceeds to step 41.
0. 411. 404. 405. Run 40G.

As described above, according to this embodiment, the plurality of calculation means 1 to 4
and a data bus 14 composed of a plurality of information transmission lines,
Bus width arbitration means 9 to 12 allocate a number of information transmission lines corresponding to the data transfer rate required by each calculation means 1 to 4 to each calculation means 1 to 4, and each calculation means 1 to 4.
a plurality of data width conversion means 5 to 8 for converting the input/output data of the input/output data into respectively allocated data; and an intermediate bus arbitration line 13 for each bus width arbitration means 9 to 12 to exchange information necessary for arbitration work; A data width control line for informing each data width conversion means 5 to 8 of the bus width acquired by each bus width arbitration means 9 to 12! 5 to 18, a plurality of calculation means 1 can be operated within the allowable range of the system bus 14
The data transfers requested by 4 can be executed in parallel. As a result, the data buffer can be omitted or its capacity can be reduced, compared to the case where all the system paths 14 are switched in a time-sharing manner to execute data transfer.

Effects of the Invention As described above, according to the present invention, since the right to use the system bus is controlled for each information transmission line, it is necessary to transfer audio data and video data simultaneously and synchronously.
V system etc. can be realized efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example in which each data width conversion means and each bus width arbitration means shown in FIG. 1 are configured using a microprocessor. 3 is a pad diagram showing an example of a procedure for realizing the function of the data width conversion means, and FIG. 4 is a pad diagram showing an example of a procedure for each bus width arbitration means to control system bus allocation. , FIG. 5 is a block diagram showing the basic parts of a conventional CD-1 system, and FIG. 6 is a block diagram of an information processing apparatus showing the parts related to the present invention extracted from FIG.

Claims (1)

[Claims] A system bus comprising a plurality of calculation means and a plurality of information transmission lines; and a bus width arbitration means for allocating to each calculation means a number of information transmission lines commensurate with the data transfer rate required by each of the calculation means. , a plurality of data width conversion means for converting input/output data of each of the calculation means into respective assigned data widths.