JPS61136159A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To prevent an overhead due to the bus conflict by incorporating plural CPUs and providing the internal and external address data buses to each CPU independently. CONSTITUTION:A CPU 100 gives accesses to an internal memory 103 and an internal I/O interface 104 via an internal address data bus 114. At the same time, the CPU 100 also gives the accesses to an external memory 105 and an external I/O interface 106 via the bus 114 and an internal address data bus 121 connected to each other by a bus controller 102 and an external address data bus 113 connected via a buffer 111. the controller 102 connects the bus 114 and an internal address data bus 120 to the bus 121 or an internal address data bus 122. Then the controller 102 sets the holding signal lines 115 and 119 at high levels respectively and holds the CPU 100 and CPU 101 respectively.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a high-performance single-chip microcomputer with a plurality of built-in central processing units. Each central processing unit has a built-in internal address/data bus, memory, input/output interface, etc., and a bus control device that allows each central processing unit to access the external address/data buses of other central processing units. Concerning a built-in high-performance single-chip microcomputer.

(Prior art) With the increase in the integration density of integrated circuits, the functions and performance of microcomputers are rapidly improving, and various peripheral circuits (human/digital
Along with the integration of circuits (converters, timers, DMA control circuits, etc.), various types of microcomputer systems have come to be constructed and used.

However, with the increasing sophistication of real-time processing and the increase in the amount of data processing required to control peripheral integrated circuits (I10 processing), the processing power required of the central processing unit (hereinafter abbreviated as CPU) has also increased dramatically. Growing and single CP
Processing in the U is reaching its physical limits.

For example, processing requests from peripheral integrated circuits are normally notified to the CPU in the form of interrupts, and the CPU performs corresponding I10 processing and data processing, but as the number of peripheral integrated circuits increases,
The number of interrupts has also increased, and the amount of corresponding Z10 processing and data processing executed by the CPU has also increased. The CPU needs to execute these processes in real time, but a single CPU
When processing with U, the burden is too great, so there is no choice but to sacrifice real-time performance to some extent.

In order to avoid sacrificing real-time performance, it is necessary to reduce the load on the CPU in some way, and a distributed processing system using multiple CPUs is a conventionally used method.

This means that the processing performed by the CPU can be performed by 100% depending on its functions.
By configuring a system that is divided into processing, data processing, etc. and allocating one dedicated CPU to each processing, the processing capacity of the system is improved by a large number of vLK.

The system configuration of the microcomputer system is shown in FIG. 7, and will be explained below based on the same figure.

In FIG. 7, the memory 1 is assumed to be readable, capable of both reading and writing, or a mixture of both. (Hereinafter, when the word "memory" is written, it has the same meaning as the above-mentioned memory 1) CPtJz that performs data processing,
It is coupled to the address and data bus 10 by the bus controller 4 via its own address and data bus 8t.
.

The CPU 3, which performs I10 processing, is coupled to the seat address and data bus 10 by the bus controller 4 via its own address and data bus 9.

A memory l and an I10 interface 7 are connected to the address/data bus 10.

The CPU 3 writes data to and reads data from the X10 interface 7, thereby exchanging data with external equipment.

In the microcomputer system shown in FIG. 7, programs and data for CPU2 and CPU3 are stored in memory 1 on address-data bus 10, and
Since the CPU 2 is connected to the memory IK address/data bus 10 when fetching instruction codes, reading/writing various calculation data to/from the memory 1, or writing/reading data from/to the interface 7 of the processor 10, the CPU 2 The CPU 3 accesses the memory l.

Address/data bus 10 to X10 interface 7
Access via t-.

However, only one CPU can access the address/data bus 10 at the same time, and the bus control device 4
．． An address/data node 10 is assigned to the CPU 3.

Assume that the CPU 2 is currently executing data processing. At this time, the hold signal line 13 is at a low level, the hold signal line 14 is at a low level, and the CPU 3 is in a hold state.

The CPLJ 2 outputs a signal to the processing request signal line 5 and the bus switching request signal line 11 to terminate the data processing.

The bus control device 4 sends a hold signal #! ! 13 is set to high level, execution of CPU2 is interrupted, and address/data bus lQt? After coupling to the address/data bus 9 of the cPU 3, the hold signal line 14 is set to low level, causing the CPU 3' to release from the hold state and execute CPUa.

The CPU 3 outputs a signal to the step 10 processing completion notification signal line 6 and the bus switching request signal line 12 at the same time as the step 10 processing is completed.

The bus control device 4 sets the hold signal line 14e to the hold state to put the CPU 3e in a hold state, and then connects the address-data bus lQf to the address-data bus 8 of the cPU2, sets the hold signal line 13 to a low level, and puts the CPU 2 into the hold state.
to resume data processing.

(Problems to be solved by the invention) In the conventional microcomputer system,
Address/data bus8. Address/data bus 9 is 1
rounding coupled to one address and data bus 1o;
A competition for the address/data bus 1° occurs, and CPU2
．． CPU3 cannot execute programs at the same time,
While the CPU 3 is executing the process 10, the data processing of the CPLI 2 is stopped, resulting in a problem in that the processing capacity of the computer system is significantly reduced.

Therefore, the present invention provides multiple CPUfcs on the same semiconductor substrate.
Internal memory that can be accessed at high speed at all times by each CPU via its own internal address data bus;
By integrating 0 interfaces, processing power and economical efficiency have been greatly improved, and since each CPU can always access external memory and external engineering 10 interfaces, it is possible to By integrating multiple address and data buses so that each CPU has an external address and data bus, bus contention does not occur when the CPU accesses external hardware resources, and processing performance is greatly improved. Synchronous processing between CPUs 1 When performing communication processing, a built-in bus control device that enables high-speed access to external hardware resources of other CPUs (this minimizes the processing performance loss due to bus contention) , a single PU owned by a conventional microcomputer system
The present invention provides a single-chip microcomputer that drastically reduces problems such as a decrease in real-time performance due to an increased load in a microcomputer system and a decrease in processing performance due to bus contention in a microcomputer system using multiple CPUs.

(Means for Solving All Problems) The device of the present invention is a single-chip microcomputer in which a plurality of central processing units are integrated on one semiconductor substrate. an internal memory, an internal input/output interface device corresponding to each of the plurality of central processing units, and internal address data dedicated to each of the plurality of central processing units that access the internal memory and the internal input/output interface device. an address/data bus corresponding to said plurality of central processing units accessing external memory and external input/output interface devices; It is integrated on the one semiconductor substrate and includes bus control means for designating a predetermined address area to access the address/data bus of another central processing unit.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The CPU 100 uses internal memory IJ103. Internal work 10 interface 1
Access 04. Moreover, the CPU 100.

The internal address coupled by the bus controller 102
Data bus 114. Internal address e-data bus 121
via an external address/data bus 113t coupled with a buffer 111 to an external memory 105°
0 interface 106.

Similarly, the CPU 101 uses the internal address/data bus 12
0 via internal memory 109. Access the internal I10 interface 110. CPU10I is also connected to internal address and data bus 120 . Via the internal address data bus 122,
External memory 107° is accessed via external address and data bus 117 coupled with buffer 112 to external I10 interface 108.

The bus controller 102 has an internal address/data bus 114.
, internal address urn data bus 120t-internal address
Data bus 121 or internal address data bus 12
Combine to 2. The bus control device 102 has a hold signal line 1
15. The hold signal mxx9t is set to high level, and each C
It has a function of controlling the PU100 and CPU10I to a hold state.

Register write signal lines 116 and 118 are connected to CPU1, respectively.
00, set to high level when CPUl0I writes data to the address register in the bus control device 102.

Internal hardware resource access signal, 11123.12
4, CPU100 and CPU10I are internal hardware resources (internal memory 17103.
Internal I10 interface 104; CPU10I
Internal memo IJ109. Set to high level when accessing internal 110 interface 110).

Next, the configuration of the bus control device 102 will be explained based on FIG. 2.

The bus control device 102 includes path switch signal generators 200 and 201 and an arbiter 202 with a path switch.

The path switch signal generators 200 and 201 each generate internal address data bus 114, tl-internal address database 12, based on the values of their built-in address registers.
2, the internal address/data bus 12Q t- determines whether to switch to the internal address/data bus 121, and if the bus is to be switched, the internal address/data bus 114
, the bus switching request signal line 201 is set to high level. Furthermore, for the internal address/data bus 120, the bus switching request signal line 206t is set to high level.

The address registers in the path switch signal generators 200 and 201 are respectively stored in the CPU 100. The register write signal lines 116 and 118t are rewritten by a command from the CPU 101, and the register write signal lines 116 and 118t are set to high level at this time.

The arbiter 202 with a path switch has a function of placing the CPU 100 and CPU 101t in a hold state according to the levels of the internal hardware resource access signal lines 123 and 124 simultaneously with the bus switching according to the bus switching request signal lines 205 and 206K. The bus control device 102 is a CPU 10
0 internal address/data bus 114, CPUl0I
internal address/data bus 120t-internal address/data bus 120t
Data bus 121 or internal address data bus 12
2, the path contention at that time is summarized in Figure 3.

Area 3 where CPU100 and CPU10I are surrounded by dotted lines
When performing bus access indicated by 00, the CPU
At least one of CPU100 and CPU10I is accessing its own internal address/data bus, so no path conflict occurs.

Area 3 where CPU100 and CPU10I are surrounded by dotted lines
When performing bus access indicated by 01, each CPU
is accessing its own external address/data bus. Therefore, bus contention does not occur.

Area 3 where CPU100 and CPU10I are surrounded by dotted lines
When bus accesses indicated by 02 are performed, bus accesses are concentrated on one external address/data bus, resulting in bus contention. At this time, the bus control device 102 places one CPU in a t-hold state, which causes overhead.

Area 3 where CPU100 and CPU10I are surrounded by dotted lines
When performing bus access indicated by 03, each CPU
Each accesses the external address/data bus of the other CPU, so no path conflict occurs.

As mentioned in the above description, in the single-chip microcomputer of this embodiment, bus contention occurs only at 9 o'clock when each CPU accesses the same external address/data bus, and does not occur in other cases. do not have.

Moreover, each CPU accessing the same external address/data bus is usually a synchronous process between each CPU.

This is when communication processing is performed, but in a multi-CPU system, each CPU usually spends most of its execution time on other processing.

Therefore, in the single-chip microcomputer of this embodiment, the processing power of the computer system is greatly improved.

Next, based on FIG. 4, the arbiter 202 with a path switch
We will describe the more detailed configuration and operation of.

The arbiter with path switch 202 is the path switch 400
and 401, and an arbiter control unit 402.

When the bus switching signal lines 403 and 404 and the bus switching request signal lines 205 and 206 are at low level, the internal address/data bus 203 is connected to the internal address/data bus 121.
Also, the data bus 204 is the internal address.
Assume that it is coupled to data bus 122.

When the bus switching request signal 205 becomes high level.

The arbiter control unit 402 controls the hold signal line 119 when the internal hardware resource access signal line 124 is at low level.
At the same time, the bus switching signal line 403 is set to a high level, and the internal address/data bus 203t is set to a high level.
Coupling to data bus 405. Internal address and data bus 405 is coupled to internal address and data bus 122, and thus internal address and data bus 203 is coupled to internal address and data bus 122. Therefore, CPU 100 accesses hardware resources on external address/data bus 117 through internal address/data bus 122 .

After that, when the bus switching request signal line 205 becomes low level, the arbiter control unit 402 sets the hold signal line 119 to low level, and at the same time sets the CPU 101t to the execution state, the bus switching signal line 403t becomes low level, and internal address/data bus 203'i Coupled to address/data bus 121.

In the initial state, if the internal hardware resource access signal line 124 is at high level, the arbiter control unit 40
2 does not operate the hold signal line 119, but only performs bus switching.

The same applies when the bus switching request signal line 206 becomes high level.

When the bus switching request signal lines 205 and 206 go high at the same time, the arbiter control unit 402 sets the bus switching signal lines 403 and 404t to high level at the same time, and internal address/data bus 203t' (g address/data bus 405 , internal address and data bus 204 to internal address and data bus 406. Internal address and data buses 405 and 406 are coupled to internal address register buses 122 and 121, respectively, to internal address and data bus 203. 204 are coupled to internal address conflict data buses 122 and 121, respectively.

Next, bus switch signal generation sections 200 and 201 are assumed to be the same, and the detailed configuration and operation of bus switch signal generation section 200 will be described.

The bus switch signal generating unit 200 uses a bus switching request signal line 205t"' so that when the address area t-cPU 100 specified by the internal address register accesses, the CPU 100 automatically accesses the address area of the corresponding CPU10I. It shall be Ilepel.

For example, in FIG. 5, the address space 5 of the CPU 100
02 address area 503t - When the CPU 100 accesses, if data is set in the address register in the path switch signal generation unit 200 so that the bus switching request signal line 205 is at In this case, the CPU 100 uses the address area 50.
3, the corresponding C
To access the entire address area 505 of PUl0I,
Perform bus switching.

The following description will be made with reference to the block diagram of the bus switch signal generator shown in FIG.

In FIG. 6, the address comparator 601 compares the value of the address register 603 and the address value of the internal address/data bus 114, and if this address value is smaller than the value of the address register 603, the signal line 605tl is set to high level. do. The signal line 605 is the address comparator 602
It is also the input signal line. Address comparator 602 similarly compares the value of address register 604 with the address value of internal address/data bus 114, and if the address value is not greater than the value of address register 604, signal line 602
Bus switching request signal +1li1 only when 5 is high level
205 'i High level. In other cases, the bus switching request signal line 205 is at a low level.

Therefore, the address value on the internal address/data bus 114 is
Only when the value is within the range of values given by 04, the bus switching request signal line 205 becomes high level, and as a result, bus switching by the arbiter 202 with a bus switch occurs.

At this time, the arbiter 202 with a bus switch sets the hold signal line 119 to high level to put the CPUIOI in the hold state, and at the same time, the internal address/data bus 203
tl - coupled to internal address and data bus 122
100 is an external address: accesses hardware resources on the data bus 117;

The above state is shown in FIG. 5 by an address space diagram of the CPU 100 and CPU 101.

FIG. 5 is an address space diagram 501 of the CPU 101 and the CPU
100 address space diagram 502, the address area 503 indicated by diagonal lines in the address space diagram 502 is the address register 603 and the address register 6.
This is the address area specified by 04. Here, the value of the address register 603 is the lower limit address of the address area 503, and the value of the address register 604 is the upper limit address of the address area 503.

When the CPU 100 accesses the address area 503, the address register 5Q5 of the corresponding CPU 101 is automatically accessed as indicated by an arrow 504.

Address register 603. Data can be written to the address register 604 by a command from the CPU 100, and at this time, the register write signal +i 116 t-no.
level.

The CPU 100 has an address register 603. For the address area 503 specified by the address register 604, C
The address area 505 corresponding to PUl0I can be accessed.

In the above embodiment, considering only a single address area, the circuit shown in FIG.
By installing a plurality of them for each address area 14, the above-mentioned automatic bus switching can be easily realized in a plurality of arbitrary address areas. In addition, the bus switch signal generator 200.2
Although 01 was considered to have the same system configuration, it may be different.

Next, the operation of this embodiment will be specifically explained based on FIGS. 1 and 3.

When CPtJloo and CPUl0I are each accessing their own external address and data bus 113.117,
The internal address/data bus 114 is coupled to the internal address data bus 121, and the internal address/data bus 120 is coupled to the internal address/data bus 122 by the bus control device 102. Write signal lines 116 and 118 to address registers in device 102 are at low level. Internal hardware resource access signal lines 123 and 124 are both at low level. At this time, the CPU 100 uses the external memory 1J10 via the external address/data bus 113.
5. The CPU 10I accesses the external memory 107 through the external data bus 117. Therefore, no bus contention occurs.

At this time, the computer system is performing bus access as shown by an area 301 surrounded by dotted lines in FIG.

In the above state, the CPU 100 controls the bus control device 102.
When accessing the address area specified by the address register in the bus controller 102, the bus controller 102 issues a hold signal
31119 to high level and CPU10I to the hold state, at the same time, the internal address/data bus 114
t-coupled to internal address and data bus 122, CPU
100, the CPU 10I performs bus accesses indicated by an area 302 surrounded by dotted lines in FIG.

In this state, the CPU 100 accesses the hardware resources on the external address/data bus 117.

At this time, a competition for the internal address-data bus 122 occurs between the CPU 100 and the CPU 101, and the CPU 1
01 is in the hold state, but since the bus control device 102 switches the bus money at high speed, there is no overhead due to the bus switching.

Next, when the CPU 100 finishes accessing the address area specified by the address register in the bus control device 102, the bus control device 102
is set to low level, and at the same time, the internal address/data bus 114 is set to the internal address/data bus 114.
Connected to data bus 121, CPU 100, CPU
10I performs bus access indicated by a region 301 surrounded by dotted lines in FIG. Therefore, no bus contention occurs at this time.

In the initial state, when the CPU 100 accesses its own external address/data bus 113 L and CP[J101 accesses its own internal address/data bus 120, the CPU 10I sets the internal hardware resource access signal i 124 t to high level, Since internal hardware resources are being accessed and bus contention does not occur, the bus control device 102 only performs bus switching and does not operate the hold signal line.

The above description also holds true when the CPU 101 accesses the address area specified by the address register in the bus control device 102.

In the above embodiment, when bus contention occurs, the internal address data bus 122 is accessed by the CPU 100, and the internal address data bus 121 is accessed by the CP (JI).
Although it is assumed that OI access is given priority, the priority order is reversed and access to the internal address/data bus 122 is accessed by the CPU 10.
It is also conceivable that the access of the CPU 100 to the internal address/data bus 121 is given priority. In that case, if bus contention occurs in the description, only the CPU in the hold state is replaced, and other parts of the description remain unchanged.

CPU100 and CPU10I simultaneously operate the bus control device 1.
When accessing the address area specified by the address register in α2, CPU100, CPU101u
A bus access is performed as indicated by an area 303 surrounded by a dotted line in FIG. The bus control device 102 has an internal address f
- Taha 7.114 to internal address data bus 122
internal address and data bus 120.
t-coupled to the internal address and data bus 121 of the cPU
Since LOO and CPU10I access the external 7L/S data buses 117 and 113, respectively, no bus contention occurs. After that, when the CPU 100 performs its own internal address/data bus 114 haircut, cPU1
00, CPUl0I hg3 Figure o, all bus accesses indicated by the area 300 surrounded by tius are performed, so no bus contention occurs.

As described above, in this embodiment, it is possible to significantly prevent a decrease in processing performance due to bus contention.

(Effects of the Invention) As described above, the present invention has a plurality of built-in CPUs, each of which independently owns the entire internal address/data bus and external address/data bus, thereby eliminating the overhead caused by competition for the bus. This has the effect that processing capacity can be significantly improved.

In addition, since each CPU has a built-in bus control device that performs high-speed bus switching so that each CPU can access the external hardware resources of other CPUs, only when multiple CPUs access the same external address/data bus at the same time. Bus contention occurs and some CPUs enter a hold state, but in other cases bus contention does not occur and the processing power can be greatly improved.

Furthermore, when a CPU accesses an arbitrary address area determined by a register that can be set by a command, the bus control device automatically connects the CPU's address/data bus to the external address/data bus of another CPU, so there is no need to switch buses. Since there is no need to execute instructions, software overhead can be significantly reduced, and since the address area for bus switching can be specified flexibly, system configuration is easy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a path control device, FIG. 3 is a diagram showing bus access states, FIG. 4 is a block diagram of an arbiter with a bus switch, and FIG. FIG. 5 is an address space diagram of the CPU, FIG. 6 is a block diagram of a bus switch signal generating section, and FIG. 1IX7 is a block diagram of a conventional microcomputer system. 1... Memory, 2... CPU, 3... Old CPU, 4... Bus control device, 5...
...110 Processing request signal line, 6...110
Processing end notification signal line, 7...1/. Interface, 8, 9.10...Address/data bus, 11.12...Bus switching request signal line, 12.14...Hold signal line, io
o,ioi/old...CPU1102...Path control device, 103,109...Internal memory, 10
4,110...Internal I10 interface,
105,107----External memory, 106,10
8...External engineering 10 interface, 111,
112...Buffer, 113,117...
・External address/data bus, 114, 120, 12
1.122...Internal address data bus, 1
15,119...Hold signal line, 116,1
18...Register write signal line, 123, 12
4... Internal hardware resource access signal line,
200゜201... Bus switch signal generation section,
202... Arbiter with bus switch, 203
,204...Internal address/data bus, 20
5,206...Bus switching destination request signal line, 300
, 301, 302. 303...Area indicating bus access status %400, 401... Bus switch, 402... Arbiter control unit, 403, 40
4... Bus switching signal d, 405, 406...
...Internal address data bus, 501.502.
...Address space diagram, 503゜505...
-Address area, 601, 602... Address comparator, 603, 604... Address register, 605... Signal line. Agent: Susumu Uchihara, Patent Attorney - 0 Minej times Hayabusa 2 Kuni (: pUit) / 3 times

Claims (1)

[Scope of Claims] A single-chip microcomputer in which a plurality of central processing units are integrated on one semiconductor substrate, comprising: an internal memory corresponding to each of the plurality of central processing units; and each of the plurality of central processing units. an internal input/output interface device corresponding to the internal input/output interface device; an internal address/data bus dedicated to each of the plurality of central processing units that accesses the internal memory and the internal input/output interface device; an address/data bus corresponding to the plurality of central processing units to be accessed; and an arbitrary one central processing unit among the plurality of central processing units to the address/data bus of the remaining other central processing units. 1. A single-chip microcomputer, comprising bus control means for specifying and accessing a predetermined address area, and integrated on the one semiconductor substrate.