JPS62152064A - Single-chip microcomputer - Google Patents

Abstract

PURPOSE:To improve the processing capacity of a single-chip microcomputer by providing internal address data buses independently of plural CPU respectively and incorporating bus controllers. CONSTITUTION:A CPU 100 gives access to its own address data bus 102 and a CPU 101 gives access to external hardware resources. Under such conditions, an address data bus 103 of the CPU 101 is connected to an address bus 108 via a bus controller 113. Here the CPU 100 gives access to an internal memory 104 and an internal I/O interface 105 via the bus 102. while the CPU 101 gives access to an external memory 111 and an external I/O interface 112 via an external address data bus. As a result, no competition is caused between buses. Under such conditions, the CPU 100 tries to give access to the external hardware resources on a bus 110. There the competition occurs in the bus 108 and the CPU 101 is held. As a result, an overhead is produced. However a bus switching action causes no overhead since the controller 113 switches buses at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-performance single-chip microcomputer incorporating a plurality of central processing units.

In particular, it has multiple central processing units on the same semiconductor substrate, each central processing unit has a built-in internal address/data path, memory/input/output interface, and access to an external address/data path shared by the multiple central processing units. The present invention relates to a high-performance single-chip microcomputer with a built-in path control device that enables each central processing unit to perform the following steps.

[Conventional technology]

As the integration density of integrated circuits increases, the functions and performance of microcomputers rapidly improve, and a wide variety of peripheral circuits (A/
Along with the integration of circuits (DFFI converters, timers, DMA control circuits, etc.), various types of microcomputer systems have been constructed and used.

However, as the real-time processing required to control peripheral integrated circuits (10 processes) increases and the amount of data processed increases, the processing capacity required of the central processing unit (hereinafter abbreviated as CPU) also increases dramatically. Processing by a single CPU is reaching its physical limits.

For example, a processing request from a peripheral integrated circuit is normally notified to the CPU in the form of an interrupt, and the CPU performs the corresponding I10 processing and data processing, but as the number of peripheral integrated circuits increases, the number of interrupts also increases, and the CPU Corresponding I10 processing to be executed
The amount of data processed is also increasing.

It is necessary for the CPU to execute these processes in real time, but since the burden of processing on a single CPU is too heavy, there is no choice but to sacrifice real-time performance to some extent.

In order not to sacrifice real-time performance, it is necessary to reduce the load on the CPUK by some method, and conventionally, a distributed processing system using multiple CPUs has been used.

A distributed processing system divides the processing performed by the CPU into I10 processing, data processing, etc. according to its function, and configures a system in which a dedicated CPU is assigned to each processing.
This improves the processing power of the system. 8. The configuration of the above-mentioned microcomputer system is shown in FIG.

This will be explained below based on the same figure.

In FIG. 6, the memory 1 is assumed to be readable only, readable and writable, or a mixture of both. (The term "memory" hereafter has the same meaning as the memory 1) The CPU 2 that performs data processing is coupled to its own address/data path 8 and address/data path 7.

The CPU 3, which performs I10 processing, is coupled to the address and data path 7 via its own address and data path 9.

Address/data path 7 has memory 1, I10* (transfer)
upxas family user's manual P593
(Intel Japan @J) K-Example is given.

Interface 6 is connected.

The CPU 3 writes and reads data to and from the I10 interface 7 and the 8th 6, and exchanges data with external equipment.

In the microcomputer system shown in FIG. 6, CPU2. Programs and data for CPU 3 are stored in memory 1 on address/data path 7, and also in memory 1 on address/data path 7.
The 0 interface 6 is connected to the address/data path 7, and the CP is
U2 accesses memory 1 via address and data path 7, and CPU 3 accesses memory 1 and I10 interface 6 via address and data path 7.

However, only one CP can be connected to address/data path 7 at the same time.
Unable to access UL, CPU2. The CPU 3 connects the address/data path 70 to the hold release signal lines 4 and 5.
Make the assignment.

Assume that the CPU 2 is currently executing data processing. C
PU3 is in a hold state.

After completing the data processing, the CPU 2 puts itself into a hold state, releases the address/data path 7, and outputs a signal to the hold release signal line 4 at the same time.

The CPU 3 is released from the hold state, acquires the address/data path 7, and executes the I10 process.

After completing the I10 process, the CPU 3 puts itself into a hold state, releases the address/data path 7, and outputs a signal to the hold release signal line 5 at the same time.

The CPU 3 is released from the hold state, acquires the address/data path 7, and begins data processing.

In the above operation, the CPU puts itself in a hold state and operates the hold signal layer by a CPU command (such as a hold command).

[Problem that the invention seeks to solve]

In the conventional microcomputer system described above, an address/data path 8, an address/data path 9
are combined into one address data path 10,
CPU2. Since the address/data path 10 is always accessed when the CPU 3 operates, the address/data path 10 is always busy, and the CPU 2. It is impossible for CPU3 to execute programs at the same time, and CPU3
During execution of processing 3 and step 10, data processing by the CPU 2 is stopped, resulting in a disadvantage that the processing capacity of the microcomputer system is significantly reduced.

[Means for solving problems]

The single-chip microcombination device according to the present invention is
- In a single-chip microcomputer in which a plurality of CPUs are integrated on a semiconductor substrate, a built-in memory/input/output interface device corresponding to each of the CPUs, which the plurality of CPUs access through dedicated address/data paths; An address/data path shared by the plurality of CPUs to enable each CPU to access an external memory/external input/output interface device, and an arbitrary address area in which each CPU is designated to access the address/data path. A major feature is that it integrates a path control device that enables the

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a single-chip microcomputer according to the present invention.

The CPU 100 connects to an internal memory 104 and an internal I10 interface 105 via an address/data path 102.
access.

The CPU 100 accesses an external memory 111 and an external I10 interface 112 via address/data paths 102 and 108 coupled by a path controller #113 and an external address/data path 110 coupled by a buffer 109.

Similarly, CPU10I connects internal memory 107 and internal I10 interface 1 via address/data path 103.
Access 06.

CPU10I is connected to the external memory ! 7111, access the external engineering 10 interface 112.

Path controller 113 couples address datapath 108 to address datapath 102 or address datapath 103.

The path control device 113 sets the hold signal lines 114, 115 to high level, and the CPU 100. It has a function of placing the CPU 101 in a hold state.

Register write signals IJI 116 and 117 are each C
When the PU100 and CPU10I write data to the register in the path control device 113, the signal is set to high level.

Internal hardware resource access signal lines 118 and 119 are connected to the CPU 100. CPUl0I is an internal node hardware resource (internal memory 104° for CPU100, internal I1
0 interface 105 corresponds to the internal memo IJ107. Internal I10 interface 1
06 is compatible. ) is set to high level when accessing.

Next, the configuration of the path control device 113 will be explained based on FIG. 2.

The path control device 113 includes a path switch signal generation section 200.
201 and an arbiter section 202 with a path switch.

The path switch signal generators 200 and 201 switch the address/data path 10 based on the values of their respective built-in registers.
2 to the address/data path 108 and the address/data path 103 to the address/data path 10B. If path coupling is to be performed, the path coupling request signal line 203 is connected to the address/data path 102. of·
Level up. Furthermore, for the address/data path 103, the path coupling request signal line 204 is set to high level.

The registers in the path switch signal generators 200 and 201 are respectively connected to the CPU 100. It is rewritten by the instruction of CPU10I, and at this time CPU100. CPU10I sets register write signal lines 116 and 117 to a no-y level.

The arbiter unit 202 with a path switch connects the paths according to the path joining request signal lines 203 and 204, and simultaneously connects the CPU 100. It has a function to put CPUl0I in a hold state.

The path control device 113 controls the address/data path 102 . CPU10I address/data path 10
3 is coupled to the address/data path 108, and table 1 summarizes the path contention at that time.

CPU100. Area 30 where CPUl0I is surrounded by a dotted line
When accessing the path indicated by 0, the CPU 10
0. At least one of the CPU10Is is accessing its own internal address data path and no path conflict occurs.

CPU100. Area 30 where CPUl0I is surrounded by a dotted line
When performing path accesses indicated by 1, path conflicts occur because the path accesses are concentrated on the external address/data path. At this time, the path control device 113
is placed in a hold state, causing overreading.

As stated above, in the single-chip microcomputer according to the present invention, path conflict occurs only when each CPU accesses the external address/data path at the same time, and does not occur in other cases. .

Moreover, as manufacturing process technology advances, the amount of built-in memory continues to increase, and each CPU can now cover most of the required amount of memory with built-in memory, making access to the external address/data path less frequent. It is thought that it will be Ayumu.

Therefore, access to external addresses and data is mainly performed when synchronization and communication processing is performed between CPUs, but in a multi-CPU system, the time spent on the synchronization and communication processing is a small portion of the execution time. That's just part of it.

Therefore, in the single-chip microcomputer according to the present invention, the processing power of the computer system is greatly improved.

, then 1 Based on FIG.
The configuration and operation of 02 will be described in more detail.

The arbiter section 202 with a path switch is the path switch 40
0,401, and an arbiter control section 402.

Path switching signal 1fM403, 404. The path connection request signal lines 203 and 204 are at low level, and the CPU is at 100°C.
PUl0I are each internal address data path 102゜1
Assume that you are accessing 03.

When the path joining request signal line 203 becomes high level, the arbiter control unit 402 does not operate the hold signal line 115 because the internal node hardware resource access signal line 119 is high level, and sets the path switching signal line 403 to high level.
address/data path 102 to address/data path 1
Join to 08. Address datapath 108 is coupled to external address datapath 110 via buffer 109 so that CPU 100 accesses external hardware resources.

After that, when the path coupling request signal 1I1203 becomes low level, the arbiter control unit 402 controls the path coupling signal line 403.
is set to a low level, and the coupling between the address/data path 102 and the address/data path 108 is released.

In the initial state, when the internal node hardware resource access signal line 119 is at a low level, the arbiter control unit 40
2 sets the hold signal line 115 to a high level when coupling the address/data path 102 to the address/data path 108, and puts the CPU10I in a hold state. Then, when the address/data path 102 and the address/data path 108 are uncoupled, the address/data path 1
03 is coupled to the address/data path 108, and the hold signal 1115t is set to low level, causing the CPU 10I to resume instruction execution.

Conversely, if the internal hardware access signal line 118 is at low level in the initial state, one CPU
is placed on hold. However, in this case, the CI'UFiCPU 101, which is placed in a hold state, can be put in a batch.

If the internal hardware access signal lines 1ts and 119 go low at the same time, the arbiter control unit 402
Priority is given to access of the PU 100 to external hardware resources.

Next, the path switch signal generation sections 200 and 201 have the same configuration, and a more detailed configuration and operation of the path switch signal generation section 200 will be described.

When the CPU 100 accesses the address area specified by the internal register, the path switch signal generating unit 200 sets the path connection request signal line 203 to a high level so as to automatically access the external address area.

For example, in FIG. 4, the address space 5 of the CPU 100
When the CPU 100 accesses the address area 503 of 01, data is set in the register in the path switch signal generation unit 200 so that the path connection request signal line 203 becomes high level.
2 couples the address data path 102 to the address data path 108 when the CPU 100 accesses the address area 503.

This will be explained below with reference to FIG.

In FIG. 5, comparator 601 compares the value of register 603 with the address value of address/data path 102, and if the address value is smaller than the value of register 603, sets signal line 605 to the NO level.

The signal line 605 is used as an input signal line of the comparator 602.

Comparator 602 similarly compares the value of register 604 with the value of register 604.
- Compare the address value of the address data path 102 and if the address value is not larger than the value of the register 604, the path connection request signal line 203 will be used only when the signal line 605 is at high level.
to a high level. In other cases, path joining request signal line 2
Make 03 No Ireperu.

In other cases, the path coupling request signal line 203 is always at a low level.

Therefore, only when the address value on the address/data path 102 is within the range of values given by the registers 603 and 604, the path joining request signal line 203 becomes high level, and as a result, the arbiter unit with path switch 202 - Combine data paths 108.

The state is expressed by the CPU 100. It is shown in FIG. 5 by the address space diagram of CPUl0I.

The wJ4 diagram is composed of a CPU10(1)7 address space diagram 501 and an address space diagram 502 of CPU10I, and the address area 503 indicated by diagonal lines in the address space diagram 501 is the address specified by the register 603.604. It is an area. Here, the value of the register 603 is the lower limit address of the address area, and the value of the register 604 is the upper limit address of the address area. Furthermore, the area indicated by the arrow 504 in the address space diagrams 501 and 502 is an address area that can be accessed by both the CPUs 100 and 101.

Arbitrary data can be written to the registers 603 and 604 according to instructions from the CPU 100.
0 makes the register write signal line 116 high level.

When the CPU 100 accesses the address area 503, the path control device 113 operates and automatically accesses external hardware resources.

At that time, if CPTJIOI is accessing an external hardware resource, the path control device 113 sets the hold signal line 115 to a high level, puts the CPUIOI in a hold state, and gives priority to the access of the CPU 100.

Next, the operation of the single-chip microcomputer according to the present invention will be specifically explained based on FIGS. 1 and 7.

When CPU 100 is accessing its own address datapath 102 and CPU10I is accessing external hardware resources, CPU10I's address and datapath 103 is coupled to address and datapath 108 by path controller 113. Also, at this time, the hold signal lines 114 and 115 are at low level, and the path control devices 1 and 1
The write signal lines 116 and 117 for the internal register 3 are at low level. Further, the internal hardware resource access signal line 118 is at high level, and the internal hardware f2 source access signal line 119 is at low level.

At this time, the CPU 100 accesses the internal memory IJ104 and the internal I10 interface 105 via the internal address/data path 102, and the CPU 10I accesses the external memory 111 via the external address/data path 110.
, accesses the external I10 interface 112, so no path conflict occurs.

At this time, the computer system is accessing the path indicated by the area 300 surrounded by dotted lines in the table of FIG.

In the above state, when cpaloo accesses the address area specified by the register in the path control device 113, the path control device 113 sets the hold signal line 115 to high level, puts the CPU10I in the hold state, and at the same time turns the address/data path 102 on. Address/data path 108
The CPU 100°CPUl0I performs the path access shown in the area 301 surrounded by the dotted line in Table 1.

In this state, the CPU 100 accesses external hardware resources on the external address/data path 110.

At this time, the competition for the address/data path 108 is C
PU100. This occurs between the CPUs 10I and 101, which causes the CPU 101 to go into a hold state, which causes overhead, but since the path control device 113 switches paths at high speed, there is no overhead due to path switching.

Next, when the CPU 100 finishes accessing the address area specified by the register in the path control device 113, the path control device 113 sets the hold signal line 115 to low level, puts the CPU10I into the l execution state, and at the same time 103 to address/data path 10
8 and connects to CPU100. The CPU 101 performs path access indicated by an area 300 surrounded by a dotted line. Therefore, no path contention occurs at this time.

In the initial state, the CPU 100. When the CPU10I is accessing its own internal address/data path 102, 103, the CPU10I sets the internal hardware resource access signal line 119 to high level, accesses the internal hardware resource, and path conflict occurs. Therefore, the path control device 113 only performs path switching and does not operate the hold signal line 115.

The above description also applies when CPUl0I accesses the address area specified by the register in the path control device 113.
Access to external hardware resources is established except for the fact that CPU 100 has priority.

CPU100. At the same time, CPU101 and path control device 11
When accessing the address area specified by the register in CPU 100. CPU10I performs path access shown in area 301 surrounded by dotted lines in Table 1.

The path control device 113 couples the address/data path 102 to the address/data path 108 and at the same time sets the hold signal line 115 to a high level, thereby placing the CPU10I in a hold state.

When the CPU 100 finishes accessing the external hardware resources, the path control device 113 issues a hold signal 1115.
is set to low level, the address/data path 103 is coupled to the address/data path 108, and the CPU 10I is allowed to access external hardware resources.

In the example above, if path contention occurs, the CP
It is assumed that the access of U100 is given priority, but the access of CPU100 is
It is also possible to make the access 1 km ahead.

In that case, C will be in a hold state when a path conflict occurs.
Only the PU is replaced, other description parts remain unchanged.

Furthermore, in the above embodiment, the path is automatically switched by the main address in accordance with the address value on the internal address/data path, so the CPUfr? Faster path switching is achieved compared to execution using the r instruction.

〔Effect of the invention〕

As explained above, the single-chip microcomputer according to the invention has a plurality of built-in CPUs, and each
Since each PU independently owns an internal address/data path, the overhead caused by competing for the path is eliminated, and the processing power of the computer system is greatly improved.

In addition, in order to enable each CPU to share external hardware resources with other CPLIs, a path control device connects each CPU's built-in address/data path to one external address/data path and performs high-speed path switching. Because of this, path conflict occurs only when multiple CPUs access the external address/data path at the same time, causing some CPUs to enter the hold state, but in other cases, path conflict does not occur.

This has the effect of greatly improving processing capacity.

It is determined by register values that can be set by the CPU using instructions. When an arbitrary address area is accessed, the path control device automatically connects the CPU's internal address and data path to the external address and data path, so there is no need to execute instructions for path switching, and software overhead is large. It is possible to reduce the width.

Furthermore, since path switching is automatically performed by hardware, faster switching can be achieved than when switching is performed by CPU instructions.

Furthermore, design of a computer system is facilitated because address space areas for path switching can be specified flexibly. ,

[Brief explanation of drawings]

Fig. 1 is a block diagram of an IJa example of the present invention, Fig. 2 is a block diagram of a microcomputer system of Hosame, Fig. 3 is a block diagram of a path control device, and Fig. 4 is an armhole with a path switch. FIG. 5 is a block diagram of the CPU address space, FIG. 6 is a block diagram of a path switch signal generator, and FIG. 7 is a diagram showing a path access state. 1... Memo 1c 2... Data processing CPU, 3... I10 processing CPU 14, 5.
...Hold release signal i, 6...I10
Interface, 7,8゜9・・・・・・Address・
Data path, 100, 101-...CPU110
2,103,108...Internal address/data path, 104,107...Internal memo 1c 10
5, 106... Internal engineering 10 interface, 109... Buffer, 110... External address/data path, 111... External memory, 112... ...external I10 interface,
113...Path control device, 114°115.
...Hold signal line, 116, 117...
・Register write signal line, 118, 119...
Internal node-ware resource access signal line, ZOo, 20
1...Pass switch signal generation section, 2o2...
...Arbiter section with path switch, 203, 204.
...Path connection request signal line, 300, 301...
...Area indicating path access status, 400, 401.
...Path switch, 402...Arbiter control unit, 403, 404...Path switching signal line, 501, 502...Address space diagram, 50
3... Part of the address space, 504...
...Arrow, 601.602...Address comparator, 603,604...Fast 1 time cputot cow 7 depression

Claims (1)

[Claims] In a single-chip microcomputer in which multiple central processing units (hereinafter referred to as CPUs) are integrated on the same semiconductor substrate, each of the multiple CPUs has a dedicated address.
A built-in memory/input/output interface device corresponding to each of the CPUs accessed via a data path, and a built-in memory/input/output interface device that allows each of the CPUs to access an external memory/external input/output interface device,
It is characterized by integrating an address/data path shared by the U and a path control device that allows each CPU to access the address/data path in a designated arbitrary address area, thereby improving path usage efficiency. A single-chip microcomputer.