JPH07200490A - Mpu - Google Patents

Abstract

PURPOSE:To enable one MPU to perform plural different arithmetic processes at a time by providing plural CPUs and caches corresponding to them in one MPU. CONSTITUTION:When the MPU 1 reads and executes a program A (instruction code A) stored in a main storage part 6, a 1st CPU 2a fetches the instruction code A through a 1st cache 3a and starts a process. While the instruction code A is fetched and this process is performed, an internal bus 6 is in an open state and 2nd CPU 2b... (n)th CPU 2c perform nothing. A bus arbitration part 4 when recognizing the state allows the 2nd CPU 2b to fetch another instruction code B on condition that there is the instruction code B to be executed. Consequently, the 2nd CPU 2b fetches the instruction code B through a 2nd cache 3b and performs a process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MPU having an arithmetic processing unit.

[0002]

2. Description of the Related Art An MPU is composed of an arithmetic processing unit, a register, a buffer, and a control unit for controlling the operations of these units.
The program stored in the external main memory is executed. The program stored in the main storage unit is first taken into the buffer under the control of the control unit and then carried to the register, and the program stored in the register is executed and processed by the arithmetic processing unit.

[0003]

Since the conventional configuration is as described above, there is a problem that one MPU can perform only one process at a time and the processing capacity is low.

The present invention has been made to solve the above problems, and an object thereof is to increase the processing speed of the MPU.

[0005]

An MPU of the present invention comprises a plurality of CPUs each comprising an arithmetic processing unit, a register, a buffer, a control unit for controlling the operation of these units, and a plurality of CPUs respectively corresponding to the CPUs. Cache memory,
An internal bus arbitration unit that arbitrates the access right of the CPU, and an internal bus that connects the CPU to the bus arbitration unit via the cache memory are featured. In addition, a plurality of CPs including an arithmetic processing unit, a register, a buffer, a control unit that controls these operations, and the like.
U, a plurality of cache memories respectively corresponding to these CPUs, an internal bus arbitration unit that transfers the same data to the CPU at the same time and compares the processing results, and the CPU is connected to the bus arbitration unit via the cache memory. It is characterized by being configured with an internal bus.

[0006]

A plurality of processes are simultaneously performed by one MPU using a plurality of CPUs. Then, the cache memories of the respective CPUs do not require the CPUs to access the outside when performing repeated processing. Further, the same processing is simultaneously processed by a plurality of CPUs in one MPU.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing the configuration of an MPU which is an embodiment of the present invention. In the figure, 1 is M of the present invention.
The PUs 2a, 2b, 2c each have a first CPU, a second CPU, an n-th CPU, 3a, 3b, which have an arithmetic processing unit, a register, a buffer, and a control unit for controlling these operations.
3c is the first CPU 2a, the second CPU 2b, the nth CPU 2
The first cache, the second cache, the nth cache, and 4 are MPUs that cache the data used by c.
In 1 inside, 1st CPU2a, 2nd CPU2b, nth
The internal bus arbitration unit 5 that arbitrates the access right to the CPU 2c is an internal bus inside the MPU 1.
The MPU 1 is composed of a plurality of CPUs. Reference numeral 6 is a main storage unit of the MPU 1 in which programs to be executed are stored.

The operation of the MPU 1 will be described below. When the MPU 1 reads and executes the program A (instruction code A) stored in the main storage unit 6, first,
The first CPU 2a fetches the instruction code A via the first cache 3a and starts the processing. While the instruction code A is fetched and this processing is being performed, the internal bus 5 is in an open state, and the second CPU 2b ...
-The nth CPU 2c is in a state where nothing is done. When the bus arbitration unit 4 recognizes this state, if there is another instruction code B to be executed, the instruction code B is sent to the second CPU 2
Allow b to capture. As a result, the second C
The PU 2b fetches the instruction code B via the second cache 3b and processes it.

As described above, the MPU 1 can process instruction codes of different programs almost simultaneously. Further, for example, when the instruction code A processed by the first CPU 2a is processed again, since the instruction code A is cached in the first cache 3a, it is not necessary to retrieve it from the main storage unit 6 and access to the outside is not required. Can be reduced. On the other hand, the internal bus 5
For example, it is also used when the first CPU 2a transfers predetermined data to the main storage unit 6 by processing the instruction code A or by ending the processing. Therefore, the first CPU 2a, the second C
PU2b ... If the access to the main storage unit 6 of each of the nth CPUs 2c can be reduced, the free time of the internal bus 5 increases, and the waiting time for accessing the main storage unit 6 can be reduced accordingly. The CPU can newly take in the instruction code, and the processing capability of the MPU 1 is improved.

By the way, in the above embodiment, different CPUs are used.
Then, the different instruction code is executed, but it is not limited to this. If the bus arbitration unit 4 causes the first CPU 2a, the second CPU 2b, ..., And the nth CPU 2c to process the same instruction code and compare the calculation results, the reliability of the processing result can be improved. In this way, if the bus arbitration unit 4 causes a plurality of CPUs to process the same instruction code, unlike the case described above, the processing speed cannot be improved when the instruction code is executed only once. When, for example, one instruction code is repeatedly executed several times for the purpose of improving reliability, the instruction code can be executed a plurality of times at a time, so that the processing speed can be improved.

[0011]

As described above, according to the present invention, a plurality of CPUs and caches corresponding to them are arranged in one MPU, so that one MPU can perform one operation.
It becomes possible to perform a plurality of different calculation processes each time.
It has the effect of improving the processing speed of the PU. Further, since one MPU is provided with a plurality of CPUs and the same data is processed by these CPUs, it is possible to improve the reliability of the processing result in a single processing without performing the same processing a plurality of times. It is possible to achieve this, and it also has the effect of improving the processing speed of the MPU.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of an MPU which is an embodiment of the present invention.

[Explanation of symbols]

 1 MPU 2a 1st CPU 2b 2nd CPU 2c nCPU 3a 1st cache 3b 2nd cache 3c nth cache 4 Internal bus arbitration unit, 5 Internal bus 6 Main storage unit

Claims (2)

[Claims] 1. A plurality of CPUs including an arithmetic processing unit, a register, a buffer, and a control unit for controlling these operations, a plurality of cache memories respectively corresponding to the CPUs, and access rights of the CPUs. An MPU comprising an internal bus arbitration unit that performs arbitration, and an internal bus that connects the CPU to the bus arbitration unit via the cache memory. 2. A plurality of CPUs including an arithmetic processing unit, a register, a buffer, and a control unit for controlling these operations, a plurality of cache memories respectively corresponding to the CPUs, and the same CPU to the CPUs at the same time. An MPU comprising: an internal bus arbitration unit that transfers data and compares processing results; and an internal bus that connects the CPU to the bus arbitration unit via the cache memory.