JPH06230985A - Task control circuit and microprocessor - Google Patents

Abstract

PURPOSE:To speed up task processing and improve a system throughput by determining a task to be executed next on the basis of the holding contents of a register. CONSTITUTION:When a CPU 31 executes a specific instruction and a task switching request signal is asserted at this time, a bit 6 of an in-execution register 10 is reset and the holding contents of an execution wait register 11 are inputted to a selecting circuit 2. Assuming that the connection relation with the selecting circuit 2 is so set by the execution wait register 11 that the priority increases from the bottom to the top in the drawing, the priority of a bit 7 is higher between bits 7 and 8 in an execution wait state, so the selecting circuit 2 selects it. Then a task information register 3 as a stage following the selecting circuit 2 selects corresponding task information 12 and sends it to the CPU 31, which executes the task on the basis of the information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a task processing circuit for processing multitasking, and more particularly to a technique effective when applied to a microprocessor, for example.

[0002]

2. Description of the Related Art A real-time operating system is intended for real-time control and is usually an operating system that supports multitasking. This operating system (abbreviated as OS)
Is incorporated into an actual machine such as a measurement system, and its main purpose is to exchange data with mechanical systems such as measurement equipment and uncontrolled processes. A program started under the control of the real-time OS is treated as a task, and the program execution,
Priority processing, parallel processing, etc. are all performed in units of tasks. The program, which is the unit of processing procedure coding,
Execution processing can be performed only when linked to the OS as a task, and a qualification such as priority is given. Each task is given a unique number, which is called the task number. This task number is used only to identify the task and does not include any meaning such as priority. The priority order is determined when the task is registered in the OS, but it can be temporarily changed during execution.

In existing microprocessor systems, multitask processing is generally realized by software. In addition, distributed O, which is in practical use
The tendency seen in S is that the program occupied in one task is short and the number of system calls is large. Therefore, if the OS becomes more complex in the future, it is possible to significantly improve the throughput by reducing the portion occupied by the OS in the processing of the entire system. At present, however, high-speed transfer of registers and stacking are possible. The reality is that the burden on the OS is reduced by dividing the registers.

An example of a document describing a real-time OS is "Microcomputer Handbook (Page 546-)" issued by Ohm Co., Ltd. on December 25, 1985.

[0005]

The speeding up of task processing is important for improving the throughput of the microprocessor system as a whole, and the inventors of the present invention have studied it. We have found that software for task switching, etc., can be made into hardware because almost fixed algorithms are used, and by doing so, speedup of processing can be expected.

An object of the present invention is to provide a technique for improving the system throughput by accelerating task processing.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, it includes a status register for holding information on execution of a plurality of tasks to be used, and a selection circuit for determining a task to be executed next based on the contents held in this register. Thus, it constitutes a task control circuit. At this time, the selection circuit
A priority encoder for determining the task to be executed next can be configured by selecting the information with the highest priority from the information held in the status register. The status register can be configured to include a register for holding task execution information and a register for holding task execution wait information. Further, in order to be compatible with a multiprocessor system, the status register can be provided with a register capable of holding information for identifying a plurality of central processing units.

[0010]

According to the above-mentioned means, a status register for holding information on the execution of a plurality of tasks to be used, and a task to be executed next for determining the task to be executed next based on the contents held in this register. The configuration of the task control circuit including the selection circuit achieves high-speed processing due to the hardware of the task switching processing function.

[0011]

FIG. 1 shows a microprocessor according to an embodiment of the present invention.

The microprocessor shown in FIG. 1 includes, but is not limited to, a central processing unit (CPU) 31, a task control circuit 9, and other peripheral circuit modules,
It is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The microprocessor according to this embodiment is
Although not particularly limited, the main purpose is to be incorporated into an actual machine such as a measuring system and exchange data with a mechanical system such as a measuring instrument or a non-control process. Programs started under the control of the real-time OS are handled as tasks,
Program execution, priority processing, parallel processing, etc. are all performed in units of tasks.

The CPU 31 is an arithmetic logic unit (ALU), which is a hardware unit for performing necessary numerical and logical operations on data stored in a register or a memory, and one of the operations in this ALU. It includes an accumulator for storing the input or its result, a general-purpose register for storing various general data, a control circuit for operation timing, and the like.

The task control circuit 9 is a circuit for controlling task switching in a real-time OS that supports multitasking in response to a task switching request from the CPU 31, and task switching control that has been realized by conventional software. Is realized by hardware. The task control circuit 9 is not particularly limited, but a status register 1 for holding information on execution of a plurality of tasks to be used, and a task to be executed next based on the contents held in the status register 1. And a selection circuit 2 for determining
And a task information register 3 for outputting the corresponding task information 5 from among a plurality of preset task information based on the output of.

The selection circuit 2 is not particularly limited,
A priority encoder for determining the task to be executed next can be configured by selecting the information with the highest priority from the information held in the status register 1. The priority encoder is
When a plurality of data are given at the same time, it has a function of outputting the code of the input terminal having the highest priority.
A priority encoder circuit known per se can be applied. The number of input terminals of this priority encoder is made equal to the number of output terminals of the status register 1.

Although not particularly limited, the status register 1 includes a running register 10 for holding information on task execution and an execution waiting register 11 for holding task execution wait information. This running register 1
The number of bits of 0 and the execution wait register 11 are made equal to each other.

It is assumed that bit 6 of the running register 10 is currently set, indicating that the corresponding task is being executed. When a predetermined instruction is executed by the CPU 31 and the task switching request signal is asserted at that time, bit 6 of the executing register 10 is reset and the content held in the execution waiting register 11 is taken into the selection circuit 2. In the execution wait register 11, assuming that the connection relationship with the selection circuit (priority encoder) 2 is set so that the priority becomes higher from the bottom to the top in the drawing, bits 7 and 8 are set.
Since the priority of the bit 7 is high in the execution wait of, the selection circuit 2 selects it. Then, the corresponding task information 12 is selected in the task information register 3 in the subsequent stage of the selection circuit 2, and the selected task information 12 is transmitted to the CPU 31, and the CPU 31 executes the task based on the information. At this time, the execution wait register 11
7 is reset and bit 13 of the in-execution register 10 is set, thereby indicating that the task has changed from the execution wait state to the execution state. Similarly, when the task switching request signal is asserted again by the CPU 31, the selection circuit 2 selects a bit with a high priority, and based on this, the task information register 3 outputs the relevant task information to the CPU 31. . In this way, task switching is performed.

As described above, by providing the task control circuit 9 and performing the multitasking processing by the dedicated hardware, the task switching can be performed in 1 to 2 machine cycles. Generally, since the multitasking processing by software requires 30 to 50 machine cycles, the processing time can be greatly shortened by processing by the dedicated hardware as in this embodiment, and the microprocessor Throughput can be improved.

FIG. 2 shows a multiprocessor system which is another embodiment of the present invention.

This multiprocessor system has a plurality of microprocessors 31-1 to 31-n, and tasks executed by the plurality of microprocessors 31-1 to 31-n are switched and controlled by a task control circuit 14. It has become so. In this embodiment, the microprocessors 31-1 to 31-n and the task control circuit 14 are
Each is composed of one chip. Further, the system of the present embodiment is not particularly limited, but is incorporated in an actual machine such as a measurement system, and its main purpose is to exchange data with a mechanical system such as a measurement device or a non-control process.

The plurality of microprocessors 31-1 to 31-1
Reference numeral 31-n stores an ALU, which is a hardware unit for performing necessary numerical and logical operations on data stored in a register or a memory, and one input of the operation by this ALU or the result thereof. It includes an accumulator, a general-purpose register for storing various general data, a control circuit for operation timing, and the like.

The basic function of the task control circuit 14 is similar to that of the above-described embodiment, and by selecting the information with the highest priority from the information held in the status register 15, the task to be executed next is selected. A selection circuit 16 including a priority encoder for determining is provided, and the task information register 17 outputs corresponding task information based on the output thereof. In the present embodiment, since it is necessary to control the task switching for each multiprocessor, a comparison circuit 18 for comparing processor numbers, a priority encoder 19 for selecting a high priority microprocessor,
A decoder 20 for decoding the output of the priority encoder 19 is provided.

Each microprocessor 31-1 to 31-n
When the task switch request signal is asserted by
The priority encoder 19 selects the processor number 24 having the highest priority, and the processor number 24 is transmitted to the comparison circuit 18 in the subsequent stage. In the comparison circuit 18, the processor number 24 and the information held in the processor number register 21 are compared, and if they match, the corresponding bit 26 of the executing register 22 and the processor number 25 of the processor number register 21 are reset. To be done. Then, the information held in the execution waiting register 23 is input to the selection circuit 16, the output of the bit 27 having the highest priority is selected, and the task information 28 corresponding thereto is selected.
Is output from the task information register 17 to the microprocessors 31-1 to 31-n. At this time, the output 24 (processor number) of the priority encoder 19
However, the microprocessor 20 is decoded by the decoder 20 in the subsequent stage, whereby the task information output from the task information register 17 is taken in only by the relevant microprocessor. Then, the corresponding bit of the executing register 22 is set, the bit 27 of the execution waiting register 23 is reset, and the bit 29 of the processor number register 21 is set to
The processor number selected by the priority encoder 19 is set.

As described above, since the task control circuit 14 is provided and the multitasking process is performed by the dedicated hardware, the time required for task switching can be greatly shortened as in the above embodiment. The throughput of the multiprocessor system can be improved.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited thereto and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above-mentioned embodiment, the microprocessors 31-1 to 31-n and the task control circuit 14 are described as being composed of one chip, respectively, but they may be formed on one semiconductor substrate. You can

A cache memory may be provided instead of the task information registers 3 and 17, and the task information may be read out through the cache memory.

In the above description, the case where the invention made by the present inventor is mainly applied to a microprocessor which is a field of application which is the background of the invention has been described. It can be widely applied to devices, control board systems, and the like.

The present invention can be applied on condition that it supports at least a multitasking process.

[0031]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, it includes a status register for holding information on execution of a plurality of tasks to be used, and a selection circuit for determining a task to be executed next based on the contents held in this register. By configuring a task control circuit with a dedicated hardware for task switching processing, it is possible to speed up the processing and further improve the system throughput.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a microprocessor that is an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a multiprocessor system which is another embodiment of the present invention.

[Explanation of symbols]

 1,15 Status register 2,16 Selection circuit 3,17 Task information register 4,14 Task control circuit 6,26 Execution bit 7,8,27 Execution wait bit 12,28 Task information 18 Comparison circuit 19 Priority encoder 20 Decoder 21 Processor number register 10,22 Running register 11,23 Execution wait register

Claims (5)

[Claims] 1. A task control circuit for controlling task switching in response to a task switching request from a central processing unit, and a status register for holding information on execution of a plurality of tasks used. A task control circuit, comprising: a selection circuit for determining a task to be executed next based on the contents held in this register. 2. The selection circuit includes a priority encoder for determining a task to be executed next by selecting the highest priority information from the information held in the status register. The task control circuit according to item 1. 3. The task control circuit according to claim 1, wherein the status register includes a register for holding task execution information and a register for holding task execution wait information. 4. The task control circuit according to claim 1, wherein the status register includes a register capable of holding information for identifying a plurality of central processing units. 5. A task control circuit according to claim 1, and a central part for issuing a task switching request to this task control circuit and executing a task selected by the task control circuit. A microprocessor in which a processing device is formed on one semiconductor substrate.