JPH03111962A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To prevent service from being stopped by restoring the contents of a register in the processor control block concerned to all processors in a failed processor module when a recoverable temporary failure occurs in any one of processor modules. CONSTITUTION:If a recoverable temporary failure occurs in the processor module 1 e.g., all the processors 11 to 13 in the failed processor module 1 are reset by a reset circuit 15 in the module 1. The module 1 detects a processor control block having the same processor number as the number obtained from a processor number generating circuit 16 in the module 1 and restores the contents of the register in the processor control block concerned to all the processors 11 to 13 in the module 1. Consequently, service to the other normal processor module 2 can be prevented from being stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system, and particularly to a multiprocessor system using a plurality of redundant processor modules each consisting of a plurality of processors and a majority circuit.

[Conventional technology]

In conventional multiprocessor systems of this type, when a recoverable failure occurs in one processor module, the failed processor module is unable to provide service to other normally operating processor modules. The only option was to shut down and reset all processor modules simultaneously.

[Problem to be solved by the invention]

In the conventional multiprocessor system described above, when a recoverable temporary failure occurs in one processor module in the processor system, service to other normally operating processor modules is stopped and the failure occurs again. When a processor module performs failure processing, all processors in the multiprocessor system.

Since the module is reset, there is a problem in that even if there is a processor module that is operating normally, the entire system is temporarily stopped.

[Means to solve the problem]

A first system of the present invention is a multiprocessor system using a plurality of redundant processor modules each consisting of a plurality of processors and a majority circuit, in which each processor module includes a reset circuit, a processor number generation circuit, A processor management block consisting of a processor number storage area, a register save area, and an inter-processor communication area is provided, and when a recoverable temporary failure occurs in any of the processor modules, the block is allocated to the failed processor module. A processor management block stores the number obtained from the processor number generation circuit of the failed processor module and register contents of the normal processor in the failed processor module, and after the storage process, all processors in the failed processor module are stored. The faulty processor
reset by the reset circuit of the module, after which the failed processor module finds a processor management block having the same processor number as the number acquired from the processor number generation circuit of the failed processor module, and resets the corresponding processor management block. The contents of the register are restored to all processors in the failed processor module.

A second system of the present invention is a multiprocessor system using a plurality of redundant processor modules each consisting of a plurality of processors and a majority circuit, in which each processor module includes a reset circuit, a processor number generation circuit, A processor management block consisting of a processor number storage area, a register save area, and an inter-processor communication area is provided, and when a recoverable temporary failure occurs in any of the processor modules, the block is allocated to the failed processor module. The processor management block stores the number obtained from the processor number generation circuit of the failed processor module and the register contents of the normal processor in the failed processor module, and after the storage process, all the numbers in the failed processor module are stored. resetting the processor by the reset circuit of the failed processor module, after which the failed processor module finds a processor management block having the same processor number as the number obtained from the processor number generation circuit of the failed processor module; , the register contents of the corresponding processor management block are restored to all the processors in the failed processor module, and the processors assigned to the processor module are restored regardless of whether the processor is in the middle of processing for the recoverable temporary failure or in normal operation. The present invention is characterized in that inter-processor communication is performed using the inter-processor communication area of the management block, and after the return processing, a message request through the inter-processor communication is processed.

〔Example〕

The present invention will be explained below using FIGS. 1, 2, and 3.

FIG. 1 shows an embodiment of the present invention.

The multiprocessor system of this embodiment has the same configuration as the processor module 1, including a processor module 1 consisting of three processors 11, 12, and 13, a majority circuit 14, a reset circuit 15, and a processor number generation circuit 16. Processor module 2 and shared memory 4
and are connected by a shared bus 3.

The processor module 1 is connected by an internal bus 19 to a common bus 3 and has three processors 11.12.13.
The reset circuit 15 and processor number generation circuit 16 are connected to an internal bus 19.

The three processors 11, 12, and 13 are the reset circuit 1
5 and the reset signal line 18, the majority circuit J4 and the mismatch detection signal lines 111, 112, 113, the interrupt signal line 17, and the bus hold signal lines 141, 142, 143.

As shown in FIG. 2, the shared memory 4 includes a processor number storage area 42. It has an internal processor management block 41 consisting of a register save area 43 and an interprocessor communication area 44.

Among the three processors 11, 12.13, one processor 11 actually accesses the shared memory 4 via the common bus 3.
It runs in normal mode reading from and writing to shared memory 4, and the other two processors 12.13
indicates the operation of processor 1.1 in normal mode using the internal bus]
It operates in a monitoring mode that monitors 9.

When a mismatch between the monitor mode processor 12 and the processor 13 with the normal mode processor 11 is detected, the majority circuit 14 is notified via the mismatch detection signal lines 112 and 113, and the normal mode processor 11 is detected via the bus hold signal line 141. The bus is held, the processor 12 is changed to the normal mode, and the processor 13 continues to operate in the monitoring mode. The majority circuit 14 then selects the three processors 11 . ．． 12. An interrupt is applied via the interrupt signal line 17 at 13.

Further, at the time of system initialization, each processor module determines its own processor management block by storing its own processor number obtained by the processor number generation circuit 16 in the storage area 42.

Next, referring to FIG. 3, a procedure for handling failures in the multiprocessor system of FIG. 1 will be explained.

Program step (hereinafter referred to as PS) 500 is normal processing. P for normal processing in processor module 1
In S500, when a recoverable failure occurs in the processor 11 in the normal mode among the constituent processors of the processor module 1, interrupt processing of PS501 to PS507 is performed. When the processor module 1 receives inter-processor communication between PS501 and PS507, the number in the processor number storage area 42 of the processor management block in the shared memory 4 is the number of the processor module 1 (the same processor management block Messages are stored in the inter-processor communication area 44 of 41.

PS501 to PS503 are the first half of interrupt processing that is executed until a local reset is applied to the three processors in the processor module 1 where a recoverable failure has occurred.

In the PS 501, the processors 12 and 13 in the monitoring mode notify the majority circuit 14 of the occurrence of a mismatch through the mismatch detection signal lines 112 and 113, and the majority circuit 14 sends a signal to the bus hold signal line 14 to which the processor 11 is connected.
1, the processor 13 in the normal state remains in the monitoring mode, the processor 12 is changed to the normal mode processor, and the interrupt signal line 17 interrupts the three processors 11, 12, and 13.

In the PS 502, the own processor number obtained by the processor number generation circuit 16 and the processor number storage area 42 of the processor management block 41 in the shared memory 4 have the same number, and the register save area 43 of the processor management block 41 is set to the normal mode. The contents of the registers of the processor 12 are saved.

In the PS 503, when the save of the contents of the register of the processor 12 is completed, the reset circuit 15 outputs a reset signal! 1
8, resets 1 to 1 are applied to the three processors 11, 12, and 13 in the processor module 1.

From PS 504 to PS 507, the processor
This is the second half of the interrupt processing from when the three processors 11, 12 and 13 in the module 1 are restarted after local reset in the PS 503 until they resume normal operation.

In the PS504, the processor 1 is selected by the majority circuit 14.
1 is released from bus hold. From now on, processor 11
becomes a processor in a monitor mode, and the processor module 1 operates with a configuration of a processor 12 in a normal mode and processors 11 and 13 in a monitor mode.

In the PS505, the three processors 11, 12, and 13 of the processor module 1 are the processor number generation circuit 1.
6 and the processor number storage area 4 in the processor management block 41.
The data in the register save area 43 of the processor management block 41 with the matching processor number is restored to the register of the processors 11, 12, and 13.

In PS506, if the processor module 1 has received inter-processor communication, it performs the service requested by the message in the inter-processor communication area 44 in the processor management block 41 of the processor module 1.
In S507, the process returns immediately after the occurrence of a failure in the processor module 1 is detected and an interrupt is generated. PS50
At 8, processor module 1 ends normal processing.

〔Effect of the invention〕

The present invention provides a multiprocessor system using a plurality of redundant processor modules each consisting of a plurality of processors and a majority voting circuit, with the configuration described above. In this case, a normally operating processor module becomes capable of interprocessor communication with a failed processor module.

Additionally, if a recoverable temporary failure occurs in a processor module in a multiprocessor system,
It is now possible to perform fault processing limited to a faulty processor module without temporarily stopping the entire system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a configuration diagram of a processor management block, and FIG. 3 is a flowchart of this embodiment. 1.2... Processor module, 3... Common bus, 4... Shared memory, 11, 12.13... Processor, 14... Majority circuit, 15... Reset circuit, 16... - Processor number generation circuit, 17... Interrupt signal line, 18... Reset signal line, 19 Internal bus, 41... Processor management block, 42... Processor number storage area, 43... Register save area, 4
4... Processor communication area, 111, 112, 113
... Mismatch detection signal line, 141, 142, 143...
- Bus hold signal line.

Claims (2)

[Claims] (1) In a multiprocessor system using a plurality of redundant processor modules each consisting of a plurality of processors and a majority circuit, each processor module has a reset circuit, a processor number generation circuit, a processor number storage area, and a register. A processor management block consisting of an evacuation area and an inter-processor communication area is provided, and when a recoverable temporary failure occurs in any of the processor modules, the processor management block assigned to the failed processor module is provided with:
The number obtained from the processor number generation circuit of the failed processor module and the register contents of the normal processor in the failed processor module are stored, and after the storage process, all processors in the failed processor module are assigned to the failed processor. reset by a reset circuit of the module; thereafter, the failed processor module finds a processor management block having the same processor number as the number acquired from the processor number generation circuit of the failed processor module; A multiprocessor system characterized in that register contents of are restored to all processors in the failed processor module. (2) Regardless of whether the recovery process is being processed for the recoverable temporary failure or during normal operation, the inter-processor communication area of the processor management block assigned to the processor module is used to perform inter-processor communication, and the recovery process is performed. 2. The multiprocessor system according to claim 1, wherein a message request through said inter-processor communication is later processed.