JPS6290068A - Auxiliary monitor system - Google Patents

Abstract

PURPOSE:To detect the trouble of an auxiliary processor system in an earlier time and to securely switch a present system to an auxiliary one by always monitoring the normalcy of the auxiliary system through the use of an exclusively used memory which each duplicated processor can access independently and a state display device, when the operation is normal. CONSTITUTION:It is assumed that a processor system 1 and a processor system 2 are the present system and the auxiliary system, respectively. Normally, the auxiliary processor 11 executes a processor diagnosis program stored in the exclusively used memory 21 and a memory-only diagnosis program at every fixed period. When the processor or memory is decided to be normal, a state display device 110 displays the effect. if they are abnormal, the state display device 110 does no display the effect. Then the present system processor 10 executes the auxiliary monitor program stored in the exclusively used memory 20 or main memories 30 and 31. This monitor program reads the display on the state display device 110 at every fixed period, decides that the auxiliary system is normal fixed period, decides that the auxiliary system is normal if the display is present, and resets the display on the state display device 110. If the display cannot be found during a fixed period, the program decides that the auxiliary system is troubled, and trouble information processing is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a standby monitoring system, and more specifically, to a standby monitoring system in which an active processor monitors the operating state of a standby processor system in a duplex processor system. Regarding.

[Background of the invention]

For example, in order to increase the reliability of an electronic switch, such as switching processing equipment in an electronic switch, the processing equipment is configured in a dual system, with an active (used) system and a standby (standby) system, and one of the active processing equipment fails. When this occurs, measures are taken to improve reliability by promptly switching to the standby processing device and eliminating interruptions in the replacement process.

These redundant processing units have a microprocessor, memory, and input/output devices, but in order to make effective use of the backup system, a dedicated memory that can be used when the processing unit becomes the backup system is installed. A device is known that uses a standby system processing device for other purposes (Japanese Patent Laid-Open No. 57-54491), but the dedicated memory in the conventionally known processing device mentioned above is Efficiency of use is necessary because only a few people are used. Furthermore, no consideration is given to the monitoring system for the standby processing device.

[Purpose of the invention]

The purpose of the present invention is to utilize the dedicated memory mentioned above, and to maintain the normality of the backup system, that is, to operate normally without failure, by using the dedicated memory and status display device that each of the duplicated processors can access independently during normal times. The purpose is to provide a method for smoothly monitoring whether or not the system is in a state where it can be used.

[Summary of the invention]

In order to achieve the above object, the standby system monitoring method of the present invention is as follows:
In a processor system that has dual processors, a dedicated memory that each processor can access independently, and a dual main memory that can only be accessed by the active processor, the backup processor normally performs processor diagnostics and memory diagnostics stored in the backup dedicated memory. The program is executed at a fixed cycle, and if the program completes normally, that fact is displayed on the status display device.On the other hand, the active processor monitors the standby system by storing it in a dedicated memory or a redundant main memory that can only be accessed by the active processor. The normal operation of the standby processor system is monitored by executing a program, reading the status display from the status display device at a cycle longer than the cycle at which the standby processor displays the status, and resetting the display. shall be.

[Embodiments of the invention]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a backup system monitoring system according to the present invention.

In the dual processor system configuration shown in FIG. 1, processor systems 1 and 2 each include a processor 10 and a
11. Dedicated memory 20; 21. Main memory 30, 31;
Consisting of processor buses 40 and 41 and processor bus switches 50 and 51, there is a memory confounding bus 100 and a status display device @11 between the processor systems 1 and 2.
o is provided.

Next, the operation of each processor system will be explained.

When the processor system 1 is the active system that performs normal program processing and the processor system 2 is simultaneously operated as the standby system, the processor bus switch 45 of the active system is
0 is a closed and standby processor bus switch 51
can access the main memory 31 via the released status bus 100, and can also access the status display device 110. This allows the active processor 10 to execute programs stored in the dedicated memory 20 or the main memory 30-31, and to access data. On the other hand, when the processor bus switch 51 is released, the standby processor 11 is connected to the main memory 30.
Although the main memory 31 cannot be accessed, the status display device 110 and the dedicated memory 21 can be accessed, so the program stored in the dedicated memory 21 can be executed.

Next, the processor system l shown in FIG.

2, a method for monitoring the normality of the standby processor system 2 will be explained. Under normal conditions, the standby processor 11 executes the processor diagnostic program and the dedicated memory diagnostic program stored in the dedicated memory 21 at regular intervals, and if it is determined to be normal, it displays a message to that effect on the status display device 110. , If it is determined that there is an abnormality, the status display [
The status is not displayed on 110. In addition, the standby processor 11
Also, if the diagnostic program cannot be executed due to some failure in the dedicated memory 21, the status is not displayed on the status display device 110.

On the other hand, the active processor 10 executes a standby monitoring program stored in the dedicated memory 2° or the main memory 30, 31. This monitoring program runs on the standby processor 11.
reads the display indicating normality set by the status display device 110 at regular intervals, and if there is a display, it determines that "the standby processor system 2 is normal" and resets the display on the status display device 110. do. If the display is not displayed for a certain period of time, it is determined that "the standby processor system 2 is in a failure state" and a failure notification process is performed. The execution cycle of the monitoring program in the active system is longer than the execution cycle of the diagnostic program in the standby system, so that the active system can reliably read the status display of the standby system.

FIG. 2 is a diagram showing the main circuit configuration of the status display bag @110.

The status display device 110 includes a processor bus 40, 41, address decoders 120, 121, and a flip-flop circuit 1.
30 and 131, and output gate circuits 140 and 141, and can be accessed from processors 10 and 11 via processor buses 40 and 41.

Next, the operation of the status display device 110 will be explained. The results of the diagnostic program executed by the standby processor 11 are as follows:
Processor bus 41. The address is displayed on the flip-flop 130 via the address decoder 121. On the other hand, the active processor 10 has a processor bus 40. Address decoder 120. The status display of the standby processor system 2 displayed on the flip-flop 130 is read through the output gate circuit 140, and the result is output to the processor bus 40 as data. After the active processor 1o reads the standby status display, the processor bus 40. Via the address decoder 120, the status display of the standby system displayed on the flip-flop 130 is reset. This series of operations is repeated at regular intervals.

〔Effect of the invention〕

As described above, according to the present invention, a standby processor,
Using dedicated memory and a status display device, the backup processor executes a diagnostic program at regular intervals, and the results are transmitted to the monitoring program of the active processor via the status display device, so that the backup processor system is This has the advantage that failures can be detected early and switching from the active processor system to the standby processor system can be reliably performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a main circuit configuration diagram of the status display device of FIG. 1. 1.2... Processor system, 10.11... Processor, 20.21... Dedicated memory, 30.31.
・・Main memory, 40.41 ・・Processor bus, 5o
. 51... Processor bus switch, 100... Memory confounding bus, 110... Status display device, 120° 121... Address decoder, 130, 131...
Flip-flop circuit, 140, 141...output gate circuit.
i go

Claims (1)

[Claims] 1. Consists of a duplex processor, a memory that can be accessed exclusively by each processor, a duplex main memory that can be accessed only by the active processor in normal times, and a status display device that displays the operating status between systems. In a processor system, under normal conditions, the standby processor executes a diagnostic program for the processor and memory stored in the standby memory at regular intervals, and if it is normal, it displays this on the status display device, and The processor executes the program stored in the dedicated memory or the redundant main memory, reads the status display of the backup system displayed on the status display device at a cycle longer than that of the backup system processor to indicate that it is normal, and displays the status. If there is, it is determined to be normal, and the status display is further reset, and if there is no status display within a certain period of time, it is determined to be a failure. 2. In the standby system monitoring system described in item 1, the status display device has first and second flip-flops, and the bus of one of the duplexed processors is connected to the bus of the dual processor via the first address decoder; is coupled to the output gate of the flip-flop, the reset terminal, and the set terminal of the second flip-flop, and the bus of the other processor is coupled to the output gate of the second flip-flop.
A standby system supervisory system coupled to the output gate of the second flip-flop, the reset terminal, and the set terminal of the first flip-flop through an address decoder of the flip-flop.