JPH07230392A - Self-diagnostic system for processor - Google Patents

Abstract

PURPOSE:To detect the fault of a processor at all times by the processor by itself by comparing an instruction peculiar code generated according to a peculiar rule before the execution of the instruction of the processor with one after the execution of the instruction and reporting an alarm at the time of the occurrence of a difference between them. CONSTITUTION:When the processor fetches an instruction from an instruction storage memory, an instruction code generating part 1 generates the instruction peculiar code in accordance with the determined rule and inputs it to a code comparison part 4; and when the fetched instruction is executed in the processor by an instruction execution part 2, an executed instruction code generating part 3 generates the instruction peculiar code in accordance with the opposite rule of the instruction code generating part 1 and inputs it to the code comparison part 4. The code comparison part 4 compares the instruction peculiar code generated by the instruction code generating part 1 and that generated by the execution instruction code generating part 3 with each other to observe the difference; and when the code comparison part 4 reports the occurrence of the difference between them to an alarm generating part 5 in the case of the occurrence of the difference, the alarm generating part 5 generates an alarm to report it to the outside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-diagnosis method for a processor, and more particularly to a self-diagnosis method for a processor in a system including a processor and an instruction storage memory for storing instructions executed by the processor.

[0002]

2. Description of the Related Art Conventionally, in a method of diagnosing a processor that is in an online state, two or more processors having the same function are connected to perform a parallel simultaneous operation, and the result of the parallel simultaneous operation is observed to diagnose the processor. And a method of executing a diagnostic program stored in the memory and determining the result to make a diagnosis.

For example, in the "multiprocessor system" disclosed in Japanese Patent Laid-Open No. 2-306362, a self-diagnosis of a failure is executed for each processor, and the self-diagnosis result is sent to a system control processor via a status register. When a notification is sent, each processor is connected to the system bus via the control register under the control of the system control processor, and the processor under self-diagnosis is disconnected from the system bus and the result of the self-diagnosis is determined to be normal. In, it is configured to connect to the system bus.

Further, in the "processor failure diagnosis device" disclosed in Japanese Patent Laid-Open No. 4-112236, a plurality of all self-tests are executed by executing an instruction for instructing the start of the test during normal operation of the processor. Each of the divided unit self-tests is performed between normal processes by utilizing the idle time of the processor, and all the self-tests are performed discretely. According to the embodiment, the main constituent elements of the normal process are In addition, the main components of the self-test operation are provided.

Further, FIG. 2 is a block diagram of a multiprocessor system showing an example of a conventional processor diagnosis method. With reference to FIG. 2, this conventional multiprocessor system includes processors 21 and 22 and a state management unit 23 that monitors the states of these processors 21 and 22 to perform online / offline control.

[0006] Normally, the state management unit 23 monitors the operating state by bringing both the processors 21 and 22 online. Then, one processor, for example, the processor 22
When the diagnosis is performed, the state management unit 23 sets the processor 22 that is online to be offline and instructs the processor 21 to diagnose the processor 22. The processor 21 started the diagnostic program and executed the diagnosis of the processor 22.

[0007]

However, each of these conventional methods has a problem that the hardware circuit is complicated, and thus the cost increase cannot be avoided.

An object of the present invention is to detect a fault in a processor by comparing the instruction peculiar code generated by the peculiar rule before and after the instruction execution of the processor and reporting an alarm when a difference between them occurs. It is to provide a self-diagnosis method of a processor that can always perform the above.

[0009]

According to the present invention, in a multiprocessor system including a processor and an instruction storage memory for storing an instruction to be executed by the processor, the processor fetches the instruction from the instruction storage memory. In this case, a self-diagnosis method for a processor is provided, which comprises means for comparing this instruction with an instruction execution result by the processor and generating an alarm when the failure of the processor is detected and notifying the alarm to the outside. To be

Further, an instruction code generation unit for generating an instruction unique code according to a rule determined when the processor fetches an instruction from the instruction storage memory, an instruction execution unit for executing the fetched instruction, and this instruction. An execution instruction code generation unit that generates an instruction unique code according to a rule opposite to the rule used by the instruction code generation unit at the time of execution, and the instruction unique code from the instruction code generation unit and the execution instruction code generation unit A self-diagnosis method for a processor is provided, which comprises a code comparison unit for observing the difference between the two and an alarm generation unit for generating an alarm and notifying the outside when the difference is detected. To be

Further, the first rule is a rule for generating the instruction unique code in ascending order of the instruction number when fetched, and the second rule is a descending order of the instruction number when executing the instruction. May be a rule for generating the instruction specific code, or the first rule is a rule for generating the instruction specific code from the instruction code by using a CRC when fetched, and the second rule is The rule may be a rule for generating the instruction unique code from the result at the time of executing the instruction.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a self-diagnosis system for a processor of the present invention.

Referring to FIG. 1, in the present embodiment, an instruction code generation for generating an instruction specific code according to a first rule defined when a processor (not shown) fetches an instruction from an instruction storage memory (not shown). Unit 1, an instruction execution unit 2 that executes the fetched instruction, and an execution instruction code that generates an instruction unique code by a second rule that is the reverse of the first rule used by the instruction code generation unit 1 when executing the instruction The generation unit 3, a code comparison unit 4 that compares the instruction specific code from the instruction code generation unit 1 and the instruction specific code from the execution instruction code generation unit 3 and observes the difference between them, and the time when the difference is detected And an alarm generation unit 5 for generating an alarm and notifying it to the outside.

Next, the operation of this embodiment will be described.

When the processor fetches an instruction from the instruction storage memory, the instruction code generation unit 1 generates an instruction unique code according to a predetermined first rule and inputs it to the code comparison unit 4.

When the instruction execution unit 2 executes the instruction fetched in the processor, the execution instruction code generation unit 3
Generates an instruction unique code according to a second rule which is the reverse of the first rule used by the instruction code generation unit 1 and inputs it to the code comparison unit 4.

In the code comparison unit 4, the instruction code generation unit 1
The instruction peculiar code generated in (1) and the instruction peculiar code generated in the execution instruction code generation unit are compared to observe the difference.

Then, when there is a difference, the code comparison unit 4 reports this to the alarm generation unit 5, and the alarm generation unit 5 generates an alarm and notifies it to the outside.

Therefore, in this embodiment, one processor can always diagnose its own failure, and immediately notify an external alarm when a failure occurs.

The first rule is a rule for generating instruction-specific codes in ascending order of the instruction numbers when the processor fetches them from the instruction storage memory, and the second rule is for the instructions when the instruction is executed. It may be a rule that the instruction specific code is generated in descending order of numbers. Alternatively, the first rule is a rule for generating an instruction unique code from the instruction code by using the CRC code when the processor fetches it from the instruction storing memory, and the second rule is the instruction unique from the result at the time of executing this instruction. It may be a rule that generates code.

[0022]

As described above, according to the present invention, in a multiprocessor system including a processor and an instruction storing memory for storing an instruction executed by the processor, when the processor fetches an instruction from the instruction storing memory, By providing a means for comparing an instruction with the instruction execution result by the processor and generating an alarm when a failure of the processor is detected and notifying the outside, each processor always keeps its own status without stopping the processor in the online state. Since it is possible to diagnose a failure, it is possible to construct a multiprocessor system having high safety and reliability with a simple hardware configuration, which brings about an effect of significantly reducing the cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a self-diagnosis system of a processor of the present invention.

FIG. 2 is a block diagram of a multiprocessor system showing an example of a conventional processor diagnosis method.

[Explanation of symbols]

 1 Instruction Code Generation Unit 2 Instruction Execution Unit 3 Execution Instruction Code Generation Unit 4 Code Comparison Unit 5 Alarm Generation Unit 21, 22 Processor 23 State Management Unit

Claims (4)

[Claims] 1. A multiprocessor system comprising a processor and an instruction storage memory for storing an instruction to be executed by the processor, wherein the instruction and the instruction by the processor when the processor fetches the instruction from the instruction storage memory. A self-diagnosis method for a processor, comprising means for comparing an execution result and generating an alarm when the failure of the processor is detected and notifying the alarm to the outside. 2. An instruction code generation unit that generates an instruction unique code according to a first rule defined when the processor fetches an instruction from the instruction storage memory,
An instruction execution unit that executes the fetched instruction and an instruction unique code that is generated by the instruction execution unit when the instruction is executed, using a second rule that is the reverse of the first rule that the instruction code generation unit uses when generating the instruction. An execution instruction code generation unit, a code comparison unit that compares the instruction specific codes from the instruction code generation unit and the execution instruction code generation unit, and observes a difference therebetween, and the code comparison unit detects the difference. The self-diagnosis method for a processor according to claim 1, further comprising: an alarm generation unit that generates an alarm at a time point and notifies the outside. 3. The first rule is a rule for generating the instruction unique code in ascending order of the instruction number when fetched, and the second rule is a descending order of the instruction number when executing the instruction. 3. The self-diagnosis method for a processor according to claim 2, wherein the rule is to generate the instruction specific code. 4. The first rule is C when fetched.
3. A rule for generating the instruction specific code from an instruction code using RC, and the second rule is a rule for generating the instruction specific code from a result at the time of executing the instruction. Processor self-diagnosis method.