JPH08202589A - Information processor and fault diagnostic method - Google Patents

Abstract

PURPOSE: To monitor and judge the presence or the absence of fault of a monitoring circuit by providing a means which judges the fault of the monitoring circuit in the case where there is no reset signal from the monitoring circuit within a standby period in a cold start mode, and starting a system in a hot start mode when the reset signal is received within the standby period. CONSTITUTION: When a CPU is reset, a start mode is judged by an MPU (step S1). When the hot start mode is judged by a watch-dog timer(WDT), etc., normal processing is executed (step S2), and when the start mode is judged to be the cold start mode, the system is turned into a standby state for the period enough for the WDT to operate (step S3). Then, when the WDT operates normally within the standby period, the CPU is reset, and when it is restarted, the system is tuned into the hot start mode. On the other hand, in the case where the WDT does not operate within the standby period, the WDT is judged to be faulty (step S4).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU and a CPU.
An information processing apparatus including a watchdog timer (hereinafter, abbreviated as WDT) for monitoring the
The present invention relates to a failure diagnosis method for performing failure diagnosis of the information processing device.

[0002]

2. Description of the Related Art Generally, an information processing apparatus of this type includes a C
In addition to the PU, the W
Some have DT. This WDT interrupts the program in the CPU at regular intervals, and is normally reset by the program in a normal state.
On the other hand, if there is a CPU failure, the WDT
Will not be reset by the program and will generate an alarm. As a result, the WDT can detect and notify an abnormality due to a program runaway or the like.

On the other hand, such an information processing apparatus tends to be widely applied to automobiles and the like, and is required to have high reliability and low cost. Therefore, it is very important to detect abnormalities due to program runaway at low cost and accurately.

[0004]

However, in the above-mentioned information processing apparatus, it is premised that the WDT normally operates, and in reality, it is not guaranteed whether or not the WDT itself operates normally. is there. Therefore, W
As far as abnormality detection by DT is concerned, it cannot be said that high reliability is guaranteed. Further, in an information processing apparatus having a plurality of CPUs, it may be possible to monitor the operation of one WDT by another CPU, but this configuration has a drawback that it cannot meet the demand for cost reduction.

Further, the information processing apparatus of this type includes a WDT
Other than that, various types of monitoring circuits for monitoring the abnormality of the CPU are used, but no consideration is given to monitoring whether or not these monitoring circuits are normal.

An object of the present invention is to provide an information processing apparatus capable of monitoring and determining the presence / absence of a failure in a monitoring circuit such as WDT.

Another object of the present invention is to provide a failure diagnosis method capable of easily diagnosing the presence or absence of a failure in a monitoring circuit such as WDT.

[0008]

According to the present invention, the failure diagnosis of the monitoring circuit can be performed by effectively utilizing the cold start mode and the hot start mode provided in this type of information processing apparatus.

Here, the cold start mode is a mode which is started from a power-off state, while the hot start mode is a mode which is started from a power-on state.

More specifically, according to the present invention, in the information processing apparatus having a central processing unit and a monitoring circuit for monitoring the CPU, which is activated in either the cold start mode or the hot start mode, the cold start is performed. Means for distinguishing between the mode and the hot start mode, a waiting time sufficient for the monitoring circuit to operate in the cold start mode, a means for waiting for the operation of the monitoring circuit, and a means for waiting for the operation of the monitoring circuit; and within the waiting time, When there is no reset signal from the monitoring circuit, the monitoring circuit is provided with a judging means for judging that the monitoring circuit has a failure. An information processing device whose state can be confirmed is obtained.

Further, according to the present invention, in a failure diagnosis method for an information processing apparatus, which comprises a CPU and a monitoring circuit and is activated in either a cold start mode or a hot start mode, the monitoring circuit operates in the cold start mode. If there is no reset signal from the monitoring circuit within this waiting time, the monitoring circuit determines that the monitoring circuit has failed, and outputs a reset signal from the monitoring circuit within the waiting time. Then, it is started in the hot start mode, which provides a failure diagnosis method capable of confirming the normality of the monitoring circuit.

[0012]

As described above, in the present invention, the reliability of the operation of the monitoring circuit can be guaranteed by confirming the operation of the monitoring circuit every cold start.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An information processing apparatus according to an embodiment of the present invention and a failure diagnosis method for the information processing apparatus will be described below with reference to the drawings.

Referring to FIG. 1, an information processing apparatus according to an embodiment of the present invention has a CPU 10 and a WDT 11 externally attached to the CPU 10. Furthermore, CPU1
0 has a microprocessor (MPU) 12, RO
M13 and RAM14 are provided.
The ROM 13 stores programs, data, etc., while the RAM 14 temporarily stores data, instructions, etc. The ROM 13 also stores programs to be described later. ROM 13 and RA
The M14 is connected to the MPU 12 via the address bus AB and the data bus DB.

The CPU 10 is also connected to a start mode determination circuit 16 that distinguishes between the cold start mode and the hot start mode. This judgment circuit 1
Although various circuits can be considered as 6, the circuit described in JP-A-63-307516 can be used, for example. On the other hand, the function of the startup mode determination circuit 16 can also be realized by the program of the ROM 13. In this case, the means for determining the start mode is built in the CPU.

Briefly, in the start mode determination, in response to the turning on of the power supply voltage Vcc, a signal indicating the turning on of the power supply voltage Vcc is generated and, in the case of the hot start mode, an identification signal indicating the hot start mode. Can be realized by configuring so as to generate.

Referring to FIG. 2, a program for monitoring the WDT 11 is shown, and this program is stored in the ROM 13 of FIG. First, when the CPU 10 is reset, the MPU 12 detects the output signal from the determination circuit 16 and determines the startup mode (step S1). When the hot start mode by the WDT 11 or the like is determined, normal processing according to the hot start mode is executed (step S2).

On the other hand, if it is determined in step S1 that the mode is the cold start mode, the process proceeds to step S3 and the program enters the mode for monitoring the WDT 11. Therefore, steps S1 and S3 are
It constitutes a means for determining a starting mode such as a cold start mode and a hot start mode, and means for monitoring the WDT 11.

In step S3, the WDT 11 waits for a sufficient time to work, and the watchdog timer (WDT) process is not performed during this time. This step S
The waiting time in 3 can be arbitrarily set for each system. The standby time may be determined by an external timer (not shown) attached outside the CPU 10, or may be set in the form of a count number such as a clock.

In step S3, within the waiting time, W
When the DT 11 operates normally, the CPU 10 is reset, and when it is restarted, the hot start mode is set. After the hot start mode is identified in step S1, the normal processing of step S2 is performed.

On the other hand, if the WDT 11 does not operate within the waiting time in step S3, the MPU 12 executing the program executes the WDT 11 in step S4.
It is determined to be a failure. Therefore, step S4 is WDT.
The determination means for determining the failure of 11 is configured.

When the WDT 11 is determined to be faulty in step S4, the process proceeds to step S5 and the fail safe measure is executed. In this fail-safe measure, a warning of failure is generated and notified, or a control operation is stopped.

Referring to FIGS. 3A and 3B, there is shown a schematic configuration of an information processing apparatus according to another embodiment of the present invention. In FIG. 3 (a), CP is used instead of WDT11.
It differs from the embodiment shown in FIG. 1 in that a monitoring circuit 20 for monitoring the abnormality of U10 is used. The monitoring circuit 20 is a circuit that monitors a pulse A of a constant cycle given from the CPU 10 and outputs a reset signal B to the CPU 10 when the pulse stops to determine that the CPU 10 is abnormal.

More specifically, the pulse signal A is given to the NPN transistor Q of the monitoring circuit 20 via the capacitor. The collector of this transistor Q is
It is connected to the connection point between the resistor R and the charging capacitor C, and the power supply voltage Vcc is applied to the other end of the resistor R.

The connection point between the resistor R and the charging capacitor C is connected to one of the input terminals of the comparator COM, and the reference voltage V is applied to the other input terminal of the comparator COM.
Is given.

First, the operation of the monitoring circuit 20 in the normal state will be described. If the CPU 10 is operating normally,
A pulse signal A as shown in FIG. 3B is given, and as a result, the transistor Q of the monitoring circuit 20 is charged by the power supply voltage Vcc every time the pulse signal A is received. The electric charge of C is discharged. Therefore, while the pulse signal A is being input, the transistor Q
As shown in FIG. 3 (b), the collector voltage Vc of the circuit has a sawtooth shape and does not exceed the reference voltage V. Therefore, the comparator COM does not output the reset signal B, and guarantees that the CPU 10 is operating normally.

On the other hand, when the pulse signal A is no longer input,
The voltage at the input terminal of the comparator COM connected to the charging capacitor C becomes higher than the reference voltage V, and as a result,
The reset signal B is output from the comparator COM, and the CPU 1
0 is reset and the CPU 10 is instructed to be abnormal.

The monitoring circuit 20 itself which performs the above-described monitoring operation of the CPU 10 in the normal state is also monitored by the CPU 20 for its normality, as in the embodiment shown in FIG. First, as described with reference to FIG. 1, when the startup mode determination circuit 16 determines that the cold start mode is in effect, the monitoring circuit 20 has sufficient time to determine that the CPU 20 is abnormal (see FIG. 3 (b) t),
That is, the pulse signal A is stopped for a sufficient time so that the charging voltage of the charging capacitor C exceeds the reference voltage.

If the monitoring circuit 20 is operating normally and the pulse signal A is stopped for the time t,
The reset signal B is output from the comparator COM, and the CPU 1
0 is reset and restarted. This reset state is similar to the hot start mode, so the CPU
No. 10 determines that it is in the hot start mode, and also determines that the monitoring circuit 20 is operating normally. After these determinations, the CPU 10 shifts to normal processing.

On the other hand, even if the pulse signal A is stopped for the time t, the reset signal B is sent from the monitoring circuit 20 to the CPU 10.
If not given to the monitoring circuit 20,
It is determined that the failure has occurred, fail-safe processing is executed, and processing such as failure warning and control stop is performed.

As mentioned above, in this embodiment, the CP
It is possible to monitor and detect whether or not there is a failure in the monitoring circuit 20 itself that monitors U10.

Referring to FIG. 4, an information processing apparatus according to yet another embodiment of the present invention includes a monitoring circuit 20 'for monitoring a failure of the CPU 10, as in FIG. The reference numeral 20 ′ includes an interrogation and determination section 21. Here, the interrogation and determination unit 21 outputs an interrogation signal X to the CPU 10 in order to monitor and confirm the normality of the operation of the CPU 10. This interrogation signal X is, for example,
(1 + 1 =?) Is a signal indicating a question, and the CPU 10 sends the answer signal Y to the monitoring circuit 20.
Send to ' In the case of the above example, the response signal Y is "2".
If so, the monitoring circuit 20 'determines that the CPU 10 is operating normally. When the response signal Y is other than "2", the monitoring circuit 20 'determines that the CPU 10 is abnormal and sends the reset signal RS to the CPU 10. Upon receiving the reset signal RS, the CPU 10 will be restarted.

On the other hand, when the CPU 10 according to this embodiment determines the cold start mode as a result of the determination of the start mode, the CPU 10 responds to the interrogation signal X from the monitoring circuit 20 '.
By intentionally outputting an incorrect response signal Y to the monitoring circuit 20 ',
The monitoring circuit 20 'waits for a sufficient time to determine the abnormality of the CPU 10.

When the monitoring circuit 20 'which has intentionally received an incorrect answer signal Y is operating normally, the monitoring circuit 20'
′ Returns the reset signal RS to the CPU 10
Reset to 10. As a result, the CPU 10 is restarted to enter the hot start mode, and the monitoring circuit 20 '
Check the normality of. In this way, when it is determined that the monitoring circuit 20 'is operating normally, the CPU 10 shifts to normal processing.

Further, the monitoring circuit 20 'which intentionally receives the incorrect reply signal Y cannot judge the abnormality of the CPU 10, and as a result, the reset signal RS is sent from the monitoring circuit 20' to the CPU.
If it is not sent to the CPU 10, the CPU 10 determines that the monitoring circuit 20 'has a failure, and performs the same processing as in the other embodiments.

The WDT 11 and the monitoring circuits 20 and 20 'in the above embodiments may be simply referred to as a monitoring circuit.

[0037]

As described above, according to the present invention, the WDT is
Since it is possible to determine whether or not there is a failure in the monitoring circuit for each cold start, even if a failure occurs in the monitoring circuit, the failure state of the monitoring circuit is not left for a long time, and the information processing device The overall reliability and safety can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining a failure detection operation of the information processing apparatus shown in FIG.

FIG. 3A is a block diagram showing a schematic configuration of an information processing apparatus according to another embodiment of the present invention. (B) is FIG.
It is a time chart for explaining operation of (a).

FIG. 4 is a block diagram showing a schematic configuration of an information processing apparatus according to still another embodiment of the present invention.

[Explanation of symbols]

10 CPU 11 Watchdog timer (WD
T) 12 microprocessor (MPU) 13 ROM 14 RAM 16 startup mode determination circuit 20, 20 'monitoring circuit 21 interrogation and determination unit

Continued Front Page (72) Inventor Masahiro Ofuji 1-1, Shinrashima-cho, Kanagawa-ku, Yokohama, Kanagawa Prefecture NEC Robot Engineering Co., Ltd. 25

Claims (5)

[Claims] 1. An information processing apparatus comprising a central processing unit (hereinafter abbreviated as CPU) and a monitoring circuit for monitoring the CPU, wherein the information processing apparatus is activated in either a cold start mode or a hot start mode, wherein the cold start mode is used. And a means for distinguishing between the hot start mode and a means for waiting the operation of the monitoring circuit in a standby state for a sufficient time for the monitoring circuit to operate in the cold start mode, and for monitoring during the waiting time. If there is no reset signal from the circuit, the monitoring circuit is provided with a judging means for judging a failure of the monitoring circuit, and when the reset signal is received from the monitoring circuit within the waiting time, the monitoring circuit is started in the hot start mode, thereby the normal state of the monitoring circuit An information processing device characterized by being able to confirm. 2. The information processing apparatus according to claim 1, further comprising an alarm generation unit that generates an alarm when the determination unit determines that the monitoring circuit has failed. 3. The information processing apparatus according to claim 1, further comprising means for performing a fail-safe measure when the determination means determines that the monitoring circuit has failed. 4. A failure diagnosis method for an information processing apparatus, comprising a CPU and a monitoring circuit, which is activated in either a cold start mode or a hot start mode,
In the cold start mode, the monitoring circuit is in a standby state for a sufficient waiting time for operation, and if there is no reset signal from the monitoring circuit within this waiting time, it is determined that the monitoring circuit has failed. Failure diagnosis method. 5. The fault diagnosis according to claim 4, wherein when a reset signal is output from the monitor circuit within the waiting time, the monitor circuit is activated in a hot start mode, whereby the normality of the monitor circuit can be confirmed. Method.