JPH03266131A - Power source state decision system for multiple system - Google Patents
Power source state decision system for multiple systemInfo
- Publication number
- JPH03266131A JPH03266131A JP2066704A JP6670490A JPH03266131A JP H03266131 A JPH03266131 A JP H03266131A JP 2066704 A JP2066704 A JP 2066704A JP 6670490 A JP6670490 A JP 6670490A JP H03266131 A JPH03266131 A JP H03266131A
- Authority
- JP
- Japan
- Prior art keywords
- state
- processing device
- response
- power
- holding means
- Prior art date
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- Granted
Links
- 230000005856 abnormality Effects 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000001514 detection method Methods 0.000 claims abstract description 9
- 238000011084 recovery Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 10
- 238000012544 monitoring process Methods 0.000 description 9
- 238000004891 communication Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
相互監視を行う多重化システムにおいて、無応答検出時
に電源状態を判定することにより適切な異常処理を行う
ことができる多重化システムの電源状態判定方式に関し
、
瞬断その他の外部要因による無応答か、処理装置の内部
要因による無応答かを簡単に判断し、対応する異常処理
を行うことことを目的とし、複数の処理装置間で相互監
視を行い、異常が発生した処理装置を他系処理装置に切
り替えて処理を続行する冗長構成をとった多重化システ
ムにおいて、各処理装置には、自系処理装置の入力電源
の状態を監視し、瞬断に伴い電源が再投入されたことを
示す情報を保持する電源状態保持手段と、他系処理装置
の無応答検出に応じて、他系処理装置の電源状態保持手
段の状態を参照し、無応答の原因が電源の瞬断に伴うシ
ステム再立ち上げによるものか否かを判断するとともに
、他系処理装置の電源状態保持手段の状態をリセットす
る制御手段とを備えて構成される。[Detailed Description of the Invention] [Summary] This invention relates to a power state determination method for a multiplex system that can perform appropriate abnormality processing by determining the power state when no response is detected in a multiplex system that performs mutual monitoring. The purpose is to easily determine whether non-response is due to a momentary power outage or other external factors, or non-response is due to an internal factor in the processing device, and to take appropriate abnormality processing. In a multiplexed system with a redundant configuration in which a processing device in which a problem occurs is switched to another processing device to continue processing, each processing device monitors the input power status of its own processing device and The power state holding means retains information indicating that the power has been turned on again, and in response to detection of non-response from the other processing device, the state of the power state holding means of the other processing device is referred to and the cause of the non-response is determined. The control means determines whether or not the problem is caused by restarting the system due to a momentary power interruption, and resets the state of the power state holding means of the other system processing device.
本発明は、相互監視を行う多重化システムにおいて、無
応答検出時に電源状態を判定することにより適切な異常
処理を行うことができる多重化システムの電源状態判定
方式に関する。The present invention relates to a method for determining the power state of a multiplex system that performs mutual monitoring and is capable of performing appropriate abnormality processing by determining the power state when a non-response is detected.
近年、オンラインシステムの高信頼性化の要求に伴い、
多重化システムが提供されている。In recent years, with the demand for higher reliability of online systems,
A multiplexing system is provided.
多重化システムでは、運用系、待機系間で通信を行って
他系処理装置の正常性を監視している。In a multiplexed system, communication is carried out between the active system and the standby system to monitor the normality of processing devices of other systems.
待機系は、運用系が無応答のときには運用系の異常発生
とみなし、運用系の処理を代行するとともに、運用系の
異常発生をオペレータに通知していた。When the active system does not respond, the standby system assumes that an abnormality has occurred in the active system, performs processing on behalf of the active system, and notifies the operator of the occurrence of an abnormality in the active system.
〔発明が解決しようとする課題〕
ところで、運用状態にある処理装置に瞬断が発生した場
合には、電源の復旧に応じて、再立ち上げ処理が行われ
ている。[Problems to be Solved by the Invention] By the way, when a momentary power outage occurs in a processing device that is in operation, restart processing is performed in response to restoration of power supply.
一方、待機状態で相互監視を行っている処理装置では、
この瞬断から再立ち上げ処理中に生じる運用処理装置の
無応答を異常発生とみなし、所定の異常処理が起動され
る。ここで、運用状態にある処理装置の瞬断に伴う従来
の処理の流れを第４図に示す。なお、処理装置Ｏ系が運
用状態にあり、処理装置ｌ系が待機状態にあるものとす
る。On the other hand, processing devices that perform mutual monitoring in a standby state,
The non-response of the operation processing device that occurs during the restart process from this instantaneous interruption is regarded as an abnormality occurrence, and a predetermined abnormality process is activated. Here, FIG. 4 shows the flow of conventional processing in response to a momentary power outage of a processing device in an operating state. It is assumed that the processing device O system is in the operating state and the processing device I system is in the standby state.
すなわち、待機状態にある処理装置１系では、運用状態
にある処理装置０系の無応答検出に応じて、例えばオペ
レータに処理装置０系の異常を通知し、また修理を要請
する等の異常処理を行い、処理装置Ｏ系に代わって運用
状態に移行する一連の処理を行う。In other words, in response to the detection of no response from the processing device 0 system in the operating state, the processing device 1 system in the standby state performs abnormal processing such as notifying the operator of the abnormality in the processing device 0 system and requesting repair. , and performs a series of processes to transition to an operational state on behalf of the O-system processors.
このように、従来の異常処理は、その原因に基づくもの
ではなく、無応答検出に応じて直ちに起動されている。In this way, conventional abnormality processing is not based on the cause of the abnormality, but is activated immediately in response to detection of no response.
したがって、瞬断等のように外部要因に伴う無応答で、
所定の立ち上げ処理後には復旧が可能であっても所定の
異常処理が行われていた。すなわち、異常検出がいずれ
復旧する外部要因によるものか、あるいは処理装置自体
にあるものかの区別ができず、オペレータその他への適
切な指示ができなかった。Therefore, if there is no response due to external factors such as instantaneous power outages,
Even if recovery is possible after a predetermined start-up process, a predetermined abnormality process is performed. In other words, it was not possible to distinguish whether the detected abnormality was caused by an external factor that would eventually recover, or whether it was caused by the processing device itself, and it was not possible to give appropriate instructions to the operator or others.
本発明は、瞬断その他の外部要因による無応答か、処理
装置の内部要因による無応答かを簡単に判断し、対応す
る異常処理を行うことができる多重化システムの電源状
態判定方式を提供することを目的とする。The present invention provides a power state determination method for a multiplexed system that can easily determine whether non-response is due to a momentary power outage or other external factors, or non-response is due to internal factors of the processing device, and can perform corresponding abnormality processing. The purpose is to
第１図は、本発明の原理ブロック図である。 FIG. 1 is a block diagram of the principle of the present invention.
図において、多重化システムは、複数の処理装置１１．
１５間で相互監視を行い、異常が発生した処理装置を他
系処理装置に切り替えて処理を続行する冗長構成をとる
。In the figure, a multiplexed system includes a plurality of processing units 11 .
A redundant configuration is adopted in which mutual monitoring is performed among the 15 systems, and a processing device in which an abnormality occurs is switched to another processing device to continue processing.
本発明では、各処理装置１１．１５に電源状態保持手段
１３、制御手段１７を備える。In the present invention, each processing device 11.15 is equipped with a power state holding means 13 and a control means 17.
電源状態保持手段１３は、自系処理装置の入力電源の状
態を監視し、瞬断に伴い電源が再投入されたことを示す
情報を保持する。The power state holding unit 13 monitors the state of the input power of the processing device of its own system, and holds information indicating that the power has been turned on again due to a momentary power outage.
制御手段１７は、他系処理装置の無応答検出に応じて、
他系処理装置の電源状態保持手段１３の状態を参照し、
無応答の原因が電源の瞬断に伴うシステム再立ち上げに
よるものか否かを判断するとともに、他系処理装置の電
源状態保持手段１３の状態をリセットする。The control means 17, in response to detection of non-response from the other system processing device,
With reference to the state of the power state holding means 13 of the other system processing device,
It is determined whether the cause of the non-response is due to restarting the system due to a momentary power interruption, and the state of the power state holding means 13 of the other system processing device is reset.
処理装置１１に瞬断が発生したときには、処理装置１１
の電源状態保持手段１３に電源が再投入されたことを示
す情報が保持される。When a momentary interruption occurs in the processing device 11, the processing device 11
Information indicating that the power has been turned on again is held in the power state holding means 13 of the device.
処理袋Ｗ１５の制御手段１７は、処理袋２１１の無応答
検出に応じて、処理装置１１の電源状態保持手段１３の
状態を参照する。無応答の原因が瞬断に伴う立ち上げ処
理中であれば、電源状態保持手段１３に電源が再投入さ
れたことを示す情報が保持されているので、それにより
、無応答が外部要因によるか否かを判断することができ
、適切な異常処理を行うことができる。The control means 17 of the processing bag W15 refers to the state of the power state holding means 13 of the processing device 11 in response to the detection of the non-response of the processing bag 211. If the cause of the non-response is during startup processing due to a momentary power outage, the power status holding means 13 holds information indicating that the power has been turned on again, so it is possible to determine whether the non-response is due to an external factor. It is possible to determine whether or not the error occurs, and appropriate abnormality processing can be performed.
処理装置１５０制御手段１７は、無応答の原因の判断後
に、次の瞬断に備えて、処理装置１１の電源情報保持手
段１３の状態をリセットする。After determining the cause of the non-response, the processing device 150 control unit 17 resets the state of the power information holding unit 13 of the processing device 11 in preparation for the next instantaneous power outage.
以下、図面に基づいて実施例の動作について詳細に説明
する。Hereinafter, the operation of the embodiment will be described in detail based on the drawings.
第２図は、本発明方式の実施例構成を示すブロック図で
ある。FIG. 2 is a block diagram showing the configuration of an embodiment of the system of the present invention.
図において、処理装置０系、処理装置１系の各ＣＰＵ２
１゜、２１．は、通信バスを介して相互監視を行う。各
処理装置は、それぞれ電源電圧を監視し、瞬断後の電源
の再投入−に応じて復電信号を出力する電圧監視回路２
３゜、２３□と、その復電信号によってセットされる復
電レジスタ２５゜、２５１とを備える。In the figure, each CPU 2 of the processing device 0 system and the processing device 1 system
1°, 21. perform mutual monitoring via a communication bus. Each processing device has a voltage monitoring circuit 2 that monitors the power supply voltage and outputs a power recovery signal when the power is turned on again after a momentary power outage.
3° and 23□, and recovery registers 25° and 251 that are set by the recovery signal.
各処理装置のＣＰＵ２１゜、２１１は、それぞれインタ
フェース線を介して対向する処理装置の復電レジスタ２
５１．２５゜の状態を読み取り、また、その状態をリセ
ットする構成である。The CPUs 21 and 211 of each processing device connect to the power recovery register 2 of the opposing processing device via an interface line, respectively.
It is configured to read the state of 51.25° and reset the state.
ここで、第１図と第２図との対応を示す。Here, the correspondence between FIG. 1 and FIG. 2 will be shown.
電源状態保持手段１３は、電圧監視回路２３゜、２３、
と、復電レジスタ２５゜、２５．とに相当する。The power state holding means 13 includes voltage monitoring circuits 23°, 23,
and power recovery register 25°, 25. corresponds to
制御手段１７は、ＣＰＵ２１゜、２１１の処理プログラ
ムに相当する。The control means 17 corresponds to the processing program of the CPUs 21° and 211.
第３図は、実施例の処理の流れを説明する図である。FIG. 3 is a diagram illustrating the flow of processing in the embodiment.
以下、第２図および第３図を参照して、実施例の処理の
流れについて説明する。The processing flow of the embodiment will be described below with reference to FIGS. 2 and 3.
処理装置０系に瞬断が発生したとき、処理装置０系では
電源再投入に応じて、再立ち上げ処理が開始されるとと
もに、電圧監視回路２３゜から復電信号が出力され、復
電レジスタ２５゜がセットされる。When a momentary power outage occurs in the processing device 0 system, the processing device 0 system starts restart processing in response to the power being turned on again, and a power recovery signal is output from the voltage monitoring circuit 23°, and the power recovery register is 25° is set.
一方、処理袋ｗｌ系は、処理装置ｏ系が瞬断から再立ち
上げ処理の間、無応答を検出する。On the other hand, the processing bag wl system detects a non-response while the processing device o system is restarting from a momentary interruption.
処理装置１系のＣＰＵ２１．は、処理装置ｏ系の無応答
検出に応じて、所定時間後に処理装置０系の復電レジス
タ２５゜の状態を読み取る。なお、所定時間は、日常起
こり得る瞬断時間である数十ｍｓ以上とすることにより
、復電レジスタ２５の状態をみれば、瞬断が生じたか否
かを特定することができる。CPU 21 of the processing device 1 system. reads the state of the power recovery register 25° of the processing device 0 system after a predetermined time in response to the detection of no response from the processing device 0 system. Note that by setting the predetermined time to several tens of milliseconds or more, which is a momentary power outage that can occur on a daily basis, it is possible to identify whether or not a momentary power outage has occurred by looking at the state of the power recovery register 25.
すなわち、この許容瞬断時間内に処理装置０系の電圧が
復旧するときには、処理装置１系のＣＰＵ２１．が読み
取る復電レジスタ２５゜の状態はセットされているので
、処理装置１系は処理装置０系の無応答の原因が瞬断発
生によるものであることを認識することができる。また
、処理装置０系の復電レジスタ２５゜の状態は、次の瞬
断発生に備えてリセットされる。That is, when the voltage of the processing device 0 system is restored within this allowable instantaneous interruption time, the CPU 21 . Since the state of the power recovery register 25° read by is set, the processing device 1 system can recognize that the cause of the non-response of the processing device 0 system is due to the occurrence of a momentary power outage. Further, the state of the power recovery register 25° of the processing device 0 system is reset in preparation for the next instantaneous power outage.
ＣＰＵ２１＋ は、瞬断発生認識に応じて、立ち上げ処
理に要する時間が経過した後に処理装置ｏ系が正常に復
帰することをオペレータに通知し、処理装置０系に代わ
って運用状態に移行する。In response to the recognition of the occurrence of a momentary power outage, the CPU 21+ notifies the operator that the processing device o system will return to normal after the time required for startup processing has elapsed, and shifts to the operating state in place of the processing device no.
処理装置ｏ系は、立ち上げ処理により一定時間経過後に
は正常状態に復帰し、待機状態となる。After a certain period of time has elapsed due to startup processing, the processing device o system returns to a normal state and enters a standby state.
処理装置１系は、系間通信再開に応じて、処理装置０系
が復旧したことを確認し、処理装置０系の復旧をオペレ
ータに通知する。In response to the resumption of inter-system communication, the processing device 1 system confirms that the processing device 0 system has been restored, and notifies the operator of the recovery of the processing device 0 system.
このように、復電レジスタ２５の状態を参照することに
より、処理装置０系の無応答の原因が瞬断に伴う再立ち
上げ処理であると特定され、処理装置０系は立ち上げ処
理に要する時間が経過した後に正常に復帰することが処
理装置１系からオペレータに通知され、無用な異常処理
が起動されることを回避することができる。In this way, by referring to the status of the power recovery register 25, it is determined that the cause of the non-response of the processing device 0 system is the restart processing due to a momentary power outage, and the processing device 0 system The operator is notified from the processing device 1 system that the system will return to normal after a period of time has elapsed, making it possible to avoid starting unnecessary abnormal processing.
なお、無応答検出に応じて参照する復電レジスタ２５の
状態がセットされていないときには、通常の異常処理が
行われる。Note that when the state of the power recovery register 25 referred to in response to detection of no response is not set, normal abnormality processing is performed.
上述したように、本発明によれば、無応答が検出された
処理装置の電源状態保持手段の状態を参照することによ
り、無応答の原因が瞬断その他の外部要因であるか否か
を判断することができる。As described above, according to the present invention, by referring to the state of the power state holding means of the processing device in which non-response is detected, it is determined whether the cause of non-response is a momentary power outage or other external factor. can do.
したがって、外部要因による無応答時には、オペレータ
にシステムが正常復帰することを通知することが可能と
なり、適切な異常処理を行うことができる。Therefore, when there is no response due to external factors, it is possible to notify the operator that the system will return to normal, and appropriate abnormality handling can be performed.
第１図は本発明の原理ブロック図、
第２図は実施例構成を示すブロック図、第３図は実施例
の処理の流′れを説明する図、第４図は従来の処理の流
れを説明する図である。
図において、
１１．１５は処理装置、
−１３は電源状態保持手段、
１７は制御手段、
２１はｃｐｕ。
２３は電圧監視回路、
２５は復電レジスタである。
実施例構成のブロック図
第２図
本発明の原理ブロック図
第１図
実施例の処理の流れを説明する図
第３図Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing the configuration of an embodiment, Fig. 3 is a diagram explaining the processing flow of the embodiment, and Fig. 4 is a diagram showing the conventional processing flow. FIG. In the figure, 11.15 is a processing device, -13 is a power state holding means, 17 is a control means, and 21 is a CPU. 23 is a voltage monitoring circuit, and 25 is a power recovery register. Figure 2: A block diagram of the configuration of the embodiment Figure 1: A block diagram of the principle of the present invention Figure 3: A diagram explaining the flow of processing in the embodiment
Claims (1)
い、異常が発生した処理装置を他系処理装置に切り替え
て処理を続行する冗長構成をとった多重化システムにお
いて、 各処理装置（１１、１５）には、 自系処理装置の入力電源の状態を監視し、瞬断に伴い電
源が再投入されたことを示す情報を保持する電源状態保
持手段（１３）と、 他系処理装置の無応答検出に応じて、他系処理装置の前
記電源状態保持手段（１３）の状態を参照し、無応答の
原因が電源の瞬断に伴うシステム再立ち上げによるもの
か否かを判断するとともに、他系処理装置の前記電源状
態保持手段（１３）の状態をリセットする制御手段（１
７）と を備えたことを特徴とする多重化システムの電源状態判
定方式。(1) In a multiplex system with a redundant configuration in which multiple processing devices (11, 15) mutually monitor each other, and a processing device in which an abnormality occurs is switched to another processing device to continue processing, each processing device (11, 15) includes a power state holding means (13) that monitors the input power state of the own processing device and holds information indicating that the power has been turned on again due to a momentary power outage; In response to detection of non-response from the device, refer to the state of the power state holding means (13) of the other system processing device to determine whether the cause of the non-response is due to restarting the system due to a momentary power outage. At the same time, the control means (1) resets the state of the power state holding means (13) of the other system processing device.
7) A power state determination method for a multiplex system, characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2066704A JP2505299B2 (en) | 1990-03-16 | 1990-03-16 | No-response judgment method for multiplexing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2066704A JP2505299B2 (en) | 1990-03-16 | 1990-03-16 | No-response judgment method for multiplexing system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03266131A true JPH03266131A (en) | 1991-11-27 |
| JP2505299B2 JP2505299B2 (en) | 1996-06-05 |
Family
ID=13323592
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2066704A Expired - Fee Related JP2505299B2 (en) | 1990-03-16 | 1990-03-16 | No-response judgment method for multiplexing system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2505299B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001056701A (en) * | 1999-07-15 | 2001-02-27 | Robert Bosch Gmbh | Method and device for mutually monitoring control units |
| EP1703401A2 (en) | 2005-03-17 | 2006-09-20 | Fujitsu Limited | Information processing apparatus and control method therefor |
| JP2008158951A (en) * | 2006-12-26 | 2008-07-10 | Meidensha Corp | Control cpu module, and programmable controller duplex system |
| JP2011022957A (en) * | 2009-07-21 | 2011-02-03 | Nec Corp | System and method for monitoring voltage |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58103061A (en) * | 1981-12-16 | 1983-06-18 | Hitachi Ltd | Calculation synchronism restoring system |
-
1990
- 1990-03-16 JP JP2066704A patent/JP2505299B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58103061A (en) * | 1981-12-16 | 1983-06-18 | Hitachi Ltd | Calculation synchronism restoring system |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001056701A (en) * | 1999-07-15 | 2001-02-27 | Robert Bosch Gmbh | Method and device for mutually monitoring control units |
| EP1703401A2 (en) | 2005-03-17 | 2006-09-20 | Fujitsu Limited | Information processing apparatus and control method therefor |
| US7802138B2 (en) | 2005-03-17 | 2010-09-21 | Fujitsu Limited | Control method for information processing apparatus, information processing apparatus, control program for information processing system and redundant comprisal control apparatus |
| JP2008158951A (en) * | 2006-12-26 | 2008-07-10 | Meidensha Corp | Control cpu module, and programmable controller duplex system |
| JP2011022957A (en) * | 2009-07-21 | 2011-02-03 | Nec Corp | System and method for monitoring voltage |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2505299B2 (en) | 1996-06-05 |
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