JPS62106564A - Using/spare processor switching control system for information processing system - Google Patents

Abstract

PURPOSE:To avoid such a case where an input/output channel operates with a response given from an input/output controller immediately after a switching action and gives disturbance to an information processing system, by stopping temporarily the operations of the input/output channel in addition to a using central processing unit having a fault. CONSTITUTION:When a watch dog timer has a time-out state owing to the fault occurrence of a central processing unit 11, a monitor/control device 50 decides that a using processor 10 has a fault and performs the switching control between the processor 10 and a spare processor by outputting a signal of a high level to an output terminal OUT. This signal produces an interruption to an interruption input terminal INT of the unit 11 via a signal line 52. The unit 1 is sifted to a waiting state of the interruption signal with intervention of an operator and stops its operation. At the same time, the output of a high level of the device 50 is supplied to an enable terminal E of an input/output channel 13 via a signal line 53. When the signal supplied to the terminal E is set at a high level, all system operations are stopped after the internal state is reset.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention Industrial Field of Application The present invention relates to a current/preliminary □1N switching control system for an information processing system.

In conventional technical information processing systems, a parallel redundant configuration with a working processor and a standby processor is often adopted to improve operability and reliability.

When the occurrence of a failure in the current processor is detected by an appropriate operation monitoring circuit such as a watchdog timer, the operation of the central processing unit of the current processor is stopped, and the backup processor starts a transition process to the current operation.

Problems to be Solved by the Invention Conventionally, when the current processor stops operating, the operation of its central processing unit is stopped; however, regarding input/output channels, when a failure occurs, the current processor is stopped by the backup processor that attempts to switch to active operation. The controller is placed in an operational state to enable reading of the status of the controller and diagnosis from the control console.

As a result, connection responses to input/output requests that were issued to the input/output control device immediately before switching are returned to the input/output channel that is no longer on the active side, which may cause system operation to be disrupted. There is a problem.

Means for Solving the Problems The present invention's active/standby switching control system that solves the problems of the prior art described above detects the occurrence of a failure in the active processor and switches between the central processing unit of the active processor and the human output channel. The JIF processor is configured to stop the operation of the human output channel and to release the stopped operation of the human output channel by the active transition operation initiated by the JIF processor.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

Embodiment FIG. 1 is a block diagram showing the configuration of an information +1 processing system to which a working/standby switching system according to an embodiment of the present invention is applied.

This information processing system includes an active processor IO, a backup processor 20, and input/output control devices 30°31...3n.
In addition to the common bus 40 that connects each of these processors and the human output control device 111, there is also a monitoring/control device 5.
0.

The current processor 10 is a central processing unit (C))U)11
And above 1. α device (MM) 12 and input/output channel 1
3. Similarly, the preprocessor 20 also includes a central processing unit 21 , a main memory 22 , and an input/output channel 23 .

The monitoring unit in the monitoring/control device 50 is the current processor lO.
The normality of the operation of the current processor 10 is monitored by monitoring predetermined instructions that appear with a predetermined frequency during the normal operation 101 of the central processing unit 11 in the current processor 10 via the signal line 51 and resetting the watchdog timer. to monitor.

When this watchdog timer times out due to a failure in the central processing unit 11, the monitoring/control unit 5
0, it is assumed that a fault has occurred in the active processor 1o, and a high signal is output to its output terminal OUT in order to control switching between active and standby processors.

This high signal is transmitted to the central processing unit 11 via the signal line 52.
generates an interrupt to the interrupt input terminal INT of the interrupt input terminal INT.

The central processing unit 11 that has received this interrupt stops its operation by transitioning to a wait state for the W11 inclusion signal due to operator intervention.

At the same time, the high output of the monitoring/control device 50 is activated by the signal cotton 53.
to the enable terminal E of the human output channel 13. Human output channel 13 has its enable terminal E
When the signal supplied to
Even if a connection response signal in response to the input/output request issued to 3n is returned from the corresponding input/output control device, the input/output channel 13 does not perform any operation.

A high output from the monitor and control device 50 causes an interrupt to be generated at the interrupt input terminal INT of the central processing unit 21 in the preprocessor 20 via the Shingetsu line 54 . Accept this
The central processing unit 21 transits from the wait state for this interrupt to a predetermined current transfer routine.

The central processing unit 21 in the first sensor 20 that has started the current transfer routine makes the input/output channel 23 operational by raising the output on the signal line 56 low, and also closes the switch 55. The accompanying rise of the signal line 53 to low releases the operation stop state of the input/output channel 13.

Thereafter, the central processing unit 21 requests the input/output channel 13, via the input/output channel 23 and the common lotus 40, to read the state of the processor 10 at the time of the failure. Upon receiving this request, the human output channel 13 reads the contents of the program counter, various status signals, execution history information, etc. stored in a predetermined area in the main memory 12, and transfers it to the central processing unit 2I. .

During this data exchange with the central processing unit 21, even if a response is returned from the human output control devices 33 to 3r+ to the input/output request before the failure, the internal state of the human output channel 53 is temporarily suspended. Therefore, no response is made to this, and the operation of transitioning from shoes to current use is not disturbed.

The central processing unit 21 receives the status information of the processor 10 at the time of failure via the human output channel 13 and starts the current operation to take over the subsequent processing.

For convenience of explanation, the case where the processors 10 and 20 are fixed as active and spare, respectively, has been illustrated above. When the configuration is configured to shift to active operation, the monitoring/control circuit 50
a monitoring target switching circuit for constantly monitoring the central processing unit on the active operating side; and signal fibers 51 to 53. Portions corresponding to the switch 55 and the signal line 56 may be added to the configuration shown in FIG. 2.

In addition, although we have shown an example of a case in which the current user output channel is set and the operation is stopped at the same time, it is also possible to have a configuration in which only the operation is stopped for the time being, and then reset is performed when the operation stop state is canceled due to the operation to transfer to the current use. Good too.

Effects of the Invention As explained in detail above, the active/standby switching control system of the present invention is configured to temporarily suspend operation of not only the central processing unit of the active processor in which a failure has occurred, but also the human output channel. Therefore, it is possible to effectively avoid a situation in which the human output channel operates in response to a response from the input/output control device immediately after switching and the system is disturbed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an information processing system to which a working/standby switching control system according to an embodiment of the present invention is applied. 10.20... Processor, 11.21... Central processing unit, 12.22... Main memory, 13.23... Input/output channel, 30.31... 3n... Human output control device,
40...Common lotus, 5o...Monitoring/control device.

Claims (1)

[Claims] A current/standby switching control method for an information processing system including a current processor and a backup processor, which detects the occurrence of a failure in the current processor, stops the operation of the central processing unit and input/output channels of the current processor, and . A working/standby switching control method for an information processing system, characterized in that the operation of the input/output channel is released from a stopped state by a working shift operation initiated by a standby processor.