JPS60254338A - Abnormality detecting system of multiprocessor - Google Patents

Abnormality detecting system of multiprocessor

Info

Publication number
JPS60254338A
JPS60254338A JP59111374A JP11137484A JPS60254338A JP S60254338 A JPS60254338 A JP S60254338A JP 59111374 A JP59111374 A JP 59111374A JP 11137484 A JP11137484 A JP 11137484A JP S60254338 A JPS60254338 A JP S60254338A
Authority
JP
Japan
Prior art keywords
command
sub
processing unit
subprocessor
spu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59111374A
Other languages
Japanese (ja)
Inventor
Takeshi Nakayama
毅 中山
Kunio Tabata
田端 邦男
Kouichi Nie
贄 浩一
Tetsuo Senbon
千本 哲男
Tatsuo Kimura
辰雄 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59111374A priority Critical patent/JPS60254338A/en
Publication of JPS60254338A publication Critical patent/JPS60254338A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751Error or fault detection not based on redundancy
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit

Abstract

PURPOSE:To monitor a response time from a subprocessor by a counter and to detect a fault by providing a main processor with a counter to be started at the generation of a state informing request command from the main processor to the subprocessor. CONSTITUTION:The main processor MPU outputs a normal command to the subprocessor SPU and also outputs a state informing request command T so as to mix the command T in the normal command at a prescribed interval. At the output of the command T, the main processor MPU starts a timer counter. When receiving the command T, the subprocessor SPU returns a response T after a time Tans. Since a time Tout counted by the counter is set so as to be Tout>Tans when the subprocessor SPU operates normally, the counter is reset and the normal operation can be checked. If the response T is not returned withing the time Tout, the main processor MPU decides that the subprocessor SPU is failed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は主処理装置及び従処理装置で構成されるシステ
ムにおける従処理装置に発生した障害をマクロに検出し
得るマルチプロセッサの異常検出方式に関する。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a multiprocessor abnormality detection method capable of macroscopically detecting a failure occurring in a slave processor in a system composed of a master processor and a slave processor. .

最近、P OS (Point Of 5ales)端
末装置の制御に用いられるPO8制御用プロセッサ(以
下、S L P (Store Level Proc
essor )と略称する。)は通常の汎用電算機の構
成部分(主処理装置(MPU))とpos特有の制御を
行なう副処理装置(SPU)とから構成されている。
Recently, a PO8 control processor (hereinafter referred to as SLP (Store Level Proc) used to control a POS (Point of 5ales) terminal device
essor). ) is composed of a general-purpose computer component (main processing unit (MPU)) and a sub-processing unit (SPU) that performs POS-specific control.

このような構成の下において、副処理装置に障゛害が発
生した場合に、その障害発生を可及的速や2かに検出し
得ることが必要になる。これはそれに接続されるpos
端末装置の正常な稼働を確保する上から要請される事項
である。
In such a configuration, when a failure occurs in the sub-processing device, it is necessary to be able to detect the failure in two ways as quickly as possible. This is the pos connected to it
This is a matter required to ensure normal operation of the terminal device.

そして、その要求は副処理装置に発生する障害のマクロ
的な検出を行ない得ることがシステム全体の正常な稼働
を維持する上で必要になって来る事柄である。
The requirement is that macroscopic detection of failures occurring in sub-processing units is necessary in order to maintain normal operation of the entire system.

〔従来の技術〕[Conventional technology]

従来における上述のような副処理装置に生ずる障害検出
は主処理装置と副処理装置との間に設けられるインター
フェース部のハードウェア信号線レベルで行なわれてい
た。即ち、副処理装置の状態を監視するのに応答待ちタ
イマを主記憶装置に設け、そのタイマがハードウェア信
号線を経て返される応答信号に応答するように構成され
、その応答信号がタイマに設定された時間内に返らない
場合には副処理装置に障害発生と判断していた。
In the past, failures occurring in the above-mentioned sub-processing devices have been detected at the hardware signal line level of the interface section provided between the main processing device and the sub-processing devices. That is, a response waiting timer is provided in the main memory to monitor the status of the sub-processing unit, and the timer is configured to respond to a response signal returned via a hardware signal line, and the response signal is set in the timer. If the request did not return within the specified time, it was determined that a failure had occurred in the subprocessing device.

しかし、副処理装置がプロセッサ、メモリ等を備えるよ
うになると、上述のような単なるインターフェース部の
障害だけでは不十分なものとなって来ている。
However, as sub-processing devices have come to include processors, memories, etc., it has become insufficient to simply have a failure in the interface section as described above.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

即ち、副処理装置がプロセッサ等を備えるに至ると、そ
のプログラムまでを含めたマクロな監視の必要性が出て
来る。
That is, when a sub-processing device is equipped with a processor or the like, it becomes necessary to perform macroscopic monitoring including its programs.

そのため、従来においては、すべてのコマンドについて
その終結に至るまでの時間を監視するような技法がとら
れていた。
Therefore, in the past, a technique was used to monitor the time taken for all commands to complete.

従って、発生する障害を短時間の内に検出し得ないばか
6か、その監視間隔の自由なる設定性に欠けている。
Therefore, either the failure cannot be detected within a short period of time, or the monitoring interval cannot be freely set.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は障害検出時間の短縮化を為し得てその監視間隔
を自由に設定し得るマルチプロセッサの異常検出方式を
提供するもので、その手段は各々プロセッサを有する主
処理装置及び副処理装置を備えて構成されるシステムに
おいて、前記主処理装置から前記副処理装置へ発行され
るコマンドの中に前記副処理装置のための状態通知要求
コマンドを設け、前記主処理装置から前記副処理装置へ
他の通常コマンドに混在させて前記状態通知要求コマン
ドを転送し、該状態通知要求コマンドの転送時点から予
め決められた時間内に前記状態通知要求コマンドに対す
る前記副処理装置の状態通翅レスポンスが前記副処理装
置の各種レスポンス中に見い出されないとき前記副処理
装置に異當が発生していると判断するようにしたもので
ある。
The present invention provides a multiprocessor abnormality detection method that can shorten the failure detection time and freely set the monitoring interval. In the system, a status notification request command for the sub-processing device is provided in a command issued from the main processing device to the sub-processing device, and a status notification request command for the sub-processing device is provided, The status notification request command is transferred mixed with the normal command of the sub-processing device, and the status notification response of the sub-processing device to the status notification request command is transferred to the sub-processing device within a predetermined time from the time of transfer of the status notification request command. When the sub-processing device is not found in various responses of the processing device, it is determined that an abnormality has occurred in the sub-processing device.

〔実施例〕。〔Example〕.

以下、添付図面を参照しながら本発明の詳細な説明する
Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

第1図は本発明を実施するシステム構成を示す。FIG. 1 shows a system configuration for implementing the present invention.

この図において、lはPO8制御用プロセッサSLPで
、こればシリアルインターフェース2を介して複数のp
os端末装置3t、32、・・・が接続されている。そ
して、プロセッサSLPは主処理装置Q p uと副処
理装置SP’Uとを備夫、これらはいずれもその内部に
プロセッサ、メモリ等を有する。プロセッサSLPは主
処理装置MPUから副処理装置SPUへ通常コマンドを
発行して副処理装置SPUに処理を依頼し、コマンドに
応答した副処理装置SPUはpos端末装置へポーリン
グを行ない、夫々のPO8端末装置のデータ収集を行な
ってこれをレスポンスの形式で主処理装置MPUへ返す
ように構成されると共に、上述の通常コマンドに混在さ
せて主処理装置MPUから状態通知要求コマンドを発行
し得るように構成されたことに本発明の要部がある。そ
して、この状態通知要求コマンドの発行時に起動される
カウンタが主処理装置に設けられて本発明の特徴部分が
構成されている。
In this figure, l is a processor SLP for controlling PO8, and this is a processor SLP for controlling PO8.
OS terminal devices 3t, 32, . . . are connected. The processor SLP includes a main processing unit Q p u and a sub-processing unit SP'U, both of which have a processor, memory, etc. therein. The processor SLP issues a normal command from the main processing unit MPU to the sub-processing unit SPU to request processing from the sub-processing unit SPU, and in response to the command, the sub-processing unit SPU polls the POS terminal device and sends a message to each PO8 terminal. It is configured to collect device data and return it to the main processing unit MPU in the form of a response, and is also configured to be able to issue a status notification request command from the main processing unit MPU in combination with the above-mentioned normal commands. The essential part of the present invention lies in what has been done. The main processing unit is provided with a counter that is activated when the status notification request command is issued, forming a characteristic part of the present invention.

このように構成されることによって、主処理装置MPU
から発行された通常コマンドと、この通常コマンドによ
って処理、例えばPO3端末装置3i(+は複数のpo
s端末装置の1つ)から入力された取引データを分類、
ブロッキング(成る一定量のデータにまとめること)し
た後主処理装置MPUへ送り返すことを依頼された副処
理装置SPUがその依頼事項の処理つまりpos端末装
置3量へポーリングを行ない、一定量のデータを収集し
て主処理装置MPUへ返すレスポンスとの間隔がたとえ
処理内容によって異なって来たとしても、そのような間
隔の相異によるレスポンスの遅れが副処理装置SPUで
の正常な処理であって且つその処理が所要時間の長きG
こ亘るものに起因するのか、又は副処理装置SPUに発
生した障害によって無応答状態に陥っていることに起因
するのかを判別することができる。
With this configuration, the main processing unit MPU
For example, a normal command issued from a PO3 terminal device 3i (+ indicates multiple
Classify transaction data input from one of the s terminal devices),
After blocking (combining data into a certain amount of data), the sub-processing unit SPU, which is requested to send it back to the main processing unit MPU, processes the request, that is, polls the three POS terminal devices, and sends a certain amount of data. Even if the interval between the response collected and returned to the main processing unit MPU differs depending on the processing content, a delay in response due to such a difference in interval is normal processing in the sub-processing unit SPU, and The process takes a long time
It is possible to determine whether the problem is caused by any of the above, or whether the problem is caused by a failure occurring in the sub-processing unit SPU, which causes it to become unresponsive.

即ち、本発明によれば、主処理装置MPUは通常コマン
ドを副処理装置SPUへ発行すると共に、これらjff
i常コマンドに混在させて所定間隔で状態通知要求コマ
ンドTを発行する(第2図参照)。
That is, according to the present invention, the main processing unit MPU issues normal commands to the sub-processing unit SPU, and also issues these jff
A status notification request command T is issued at predetermined intervals mixed with the i regular command (see FIG. 2).

この状態通知要求コマンドTの発行時に主処理袋W M
 P Uはタイマを起動する。副処理装置SPUではコ
マンドTを受信すると、時間T ans後にレスポンス
Tを主処理装置に返す。レスポンスTを返すのに要する
時間T ansは副処理装置SPUのソフトウェアを含
めた検査対象を総合的にチェックするためである。
When this status notification request command T is issued, the main processing bag W M
PU starts a timer. When the sub-processing unit SPU receives the command T, it returns a response T to the main processing unit after a time T ans. The time T ans required to return the response T is for comprehensively checking the inspection target including the software of the sub-processing unit SPU.

副処理装置SPUが正常に動作している限り、カウンタ
で計時する時間ToutはTout >Tan5になる
ように設定されているから、カウンタは必ずリセットさ
れる。これにより、副処理装置SPUの正常な動作は確
認し得ることになる。
As long as the sub-processing unit SPU is operating normally, the time Tout measured by the counter is set so that Tout>Tan5, so the counter is always reset. Thereby, the normal operation of the sub-processing unit SPU can be confirmed.

又、第2図に示されるように、レスポンスTが時間To
ut以内に返って来ない場合には、他のコマンドのレス
ポンスも同時に返らないこととなるが、時間Tan5以
内に返される筈のレスポンスTが主処理装置MPSに返
されないことから、副処理装置SPUが障害であると判
断することができる。
Moreover, as shown in FIG. 2, the response T is the time To
If the response is not returned within ut, responses to other commands will not be returned at the same time, but since the response T that should be returned within time Tan5 is not returned to the main processing unit MPS, the sub-processing unit SPU can be determined to be a disability.

このような判断は可及的短時間内に行なうことができる
から、その異字検出が遅れたなら大量のデータを失って
しまう可能性のあるシステム環境、例えば上述のような
主処理装置によるPO3端末装置からのデータを集積を
要する場合等に本発明の機能が十分に発揮し得ることに
なる。
Since such judgment can be made within the shortest possible time, system environments where there is a possibility of losing a large amount of data if the abnormal character detection is delayed, such as the PO3 terminal using the main processing unit as described above, are This means that the functions of the present invention can be fully utilized in cases where it is necessary to accumulate data from devices.

このような作用効果はコマンドTの発行される間隔を自
在に変えることにより、その意図する効果を最も良く発
揮させることができる。
By freely changing the interval at which the command T is issued, the intended effect can be best exhibited.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、■副処理装置に
生じた障害の検出時間の短縮化を果たし、検出遅れから
生ずる弊害の可及的除去を図り、 ■又、このような効果を検出間隔の自在な設定により高
揚させ得る、等の効果が得られる。
As explained above, according to the present invention, 1) the detection time of a failure occurring in the sub-processing device is shortened, and the harmful effects caused by the detection delay are eliminated as much as possible; Effects such as enhanced detection can be obtained by freely setting the detection interval.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明を実施するシステム構成を示す図、第2
図は本発明を説明するための信号方式を示す図である。 図中、1はPO8制御用プロセッサ、2はシリアルイン
ターフェース、31.’32 ・・・はP。 S端末装置、MPUは主処理装置、SPUは副処理装置
である。 第1図
FIG. 1 is a diagram showing the system configuration for implementing the present invention, and FIG.
The figure is a diagram showing a signal system for explaining the present invention. In the figure, 1 is a PO8 control processor, 2 is a serial interface, 31. '32... is P. In the S terminal device, MPU is a main processing unit, and SPU is a sub-processing unit. Figure 1

Claims (1)

【特許請求の範囲】[Claims] 各々プロセッサを有する主処理装置及び副処理装置を備
えて構成されるシステムにおいて、前記主処理装置から
前記副処理装置へ発行されるコマンドの中に前記副処理
装置のための状態通知要求コマンドを設け、前記主処理
装置から前記副処理装置へ他の通常コマンドに混在させ
て前記状態通知要求コマンドを転送し、該状態通知要求
コマンドの転送時点から予め決められた時間内に前記状
態通知要求コマンドに対する前記副処理装置の状態通知
レスポンスが前記副処理装置の各種レスポンス中に見い
出されないとき前記副処理装置に異常が発生していると
判断するようにしたことを特徴とするマルチプロセッサ
の異常検出方式。
In a system configured with a main processing unit and a sub-processing unit each having a processor, a status notification request command for the sub-processing unit is provided in a command issued from the main processing unit to the sub-processing unit. , transfer the status notification request command from the main processing device to the sub-processing device mixed with other normal commands, and respond to the status notification request command within a predetermined time from the time of transfer of the status notification request command. An abnormality detection method for a multiprocessor, characterized in that when a status notification response of the subprocessor is not found among various responses of the subprocessor, it is determined that an abnormality has occurred in the subprocessor. .
JP59111374A 1984-05-31 1984-05-31 Abnormality detecting system of multiprocessor Pending JPS60254338A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59111374A JPS60254338A (en) 1984-05-31 1984-05-31 Abnormality detecting system of multiprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59111374A JPS60254338A (en) 1984-05-31 1984-05-31 Abnormality detecting system of multiprocessor

Publications (1)

Publication Number Publication Date
JPS60254338A true JPS60254338A (en) 1985-12-16

Family

ID=14559569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59111374A Pending JPS60254338A (en) 1984-05-31 1984-05-31 Abnormality detecting system of multiprocessor

Country Status (1)

Country Link
JP (1) JPS60254338A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01177645A (en) * 1988-01-07 1989-07-13 Ricoh Co Ltd Method for detecting run-away for control system
JPH03269759A (en) * 1990-03-20 1991-12-02 Fujitsu Ltd Multiprocessor control system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS558134A (en) * 1978-07-04 1980-01-21 Oki Electric Ind Co Ltd Fault detection system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS558134A (en) * 1978-07-04 1980-01-21 Oki Electric Ind Co Ltd Fault detection system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01177645A (en) * 1988-01-07 1989-07-13 Ricoh Co Ltd Method for detecting run-away for control system
JPH03269759A (en) * 1990-03-20 1991-12-02 Fujitsu Ltd Multiprocessor control system

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