JPS62162155A - Information processing system - Google Patents

Abstract

PURPOSE:To facilitate the analysis of a faulty by judging in a fault processing circuit to or not to report a fault to peripheral controllers in case detecting the fault, and in case of reporting, activating the EATT on a common bus to inform the peripheral controllers of the fault in a memory access controller. CONSTITUTION:A fault detecting circuits 30-32 execute the parity-check of data and the check of control action by using a buss control circuit 20, a processing circuit 21, and a MEM control circuit 22. In case of detecting a fault, it is immediately reported to the fault processing circuit 41 through a gate circuit 40. The circuit 41 analyses the content of the fault, and after editing, judges whether or not to report it to the peripheral controllers 15-17. In case of reporting it, the circuit 41 issues the second fault-report 101 to an EATT 13 together with an end signal outputted from the bus control circuit 20 on a CNTL 14 to report the fault to the peripheral controllers. Thereafter, by means of the first fault-report 102, the circuit 41 reports to a central processing unit 11, and instructs a clock control circuit 42 to stop clock.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an information processing system.

“Prior Art” A memory access control device, which is a component of a conventional information processing system, determines the priority of access requests sent from multiple peripheral control devices on a common path, and then performs acceptance processing. performs main memory access processing between multiple peripheral control devices and the main memory by sending an access request to the main memory and sending a response from the main memory to the request to a common bus. .Furthermore, the peripheral control device side operates a monitoring timer from the time the request is outputted onto the common bus until the end signal from the memory access control device is received from the common bus.During the above main memory access processing, When a failure occurs in the memory access control device, after detecting the failure, the memory access control device stops main memory access processing and reports the failure to the central processing unit, but it does not notify the peripheral control device connected to the common bus. The system consisted of an information processing system that did not report any failures.

[Problem that the invention seeks to solve]

In the conventional information processing system described above, if a failure occurs in the memory access control device during main memory access processing from a peripheral control device, the memory access control device cancels the main memory access processing and However, since the failure is not reported to the peripheral control device connected to the common bus, the monitoring timer in the peripheral control device detects a timeout, and the peripheral control device also causes a failure. That will happen. Furthermore, when a double failure occurs in system failure analysis, there is a problem in that failure analysis cannot be easily performed.

[Means for solving problems]

The system of the present invention is an information processing system that includes a main storage device, a plurality of peripheral control devices connected to a common lot, a memory access control device that collectively controls requests from the peripheral control devices, and a central processing unit. In the memory access control device, the memory access control device includes a fault detection means for detecting a fault in each circuit constituting the device, and a fault detection means that analyzes the content of the fault detected by the serious crime and generates a first fault notification signal to the peripheral control device. further comprising a fault processing means for generating a second fault notification signal when a fault requires reporting, and a signal stop means for stopping the clock signal in response to the supply of the first fault notification signal, includes a transmission means for transmitting the second fault notification signal to the peripheral control device, and each of the plurality of peripheral devices is configured to issue an access request to the common bus and then receive a response from the common bus. a time monitoring means that monitors the time until the time elapses, issues an alarm when a certain period of time has elapsed, and is reset by the second fault alarm signal;
The central processing unit is configured to include receiving means for receiving the first failure notification signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Reference numeral 10 is the main memory, reference numeral 11 is the central processing unit, reference numeral 12 is the memory access control unit, reference numeral 1
3 is a signal line (hereinafter referred to as EATT) indicating a failure state of the memory access control device 12, and reference numeral 14 is a control line (hereinafter referred to as CNTL) for transmitting and receiving request signals and termination signals to and from the peripheral control devices 16 to 18. ) is shown. Reference numeral 15 indicates an address data line (hereinafter referred to as ADR) indicating a bus for address signals and data for requests from peripheral control units 16 to 18 or data sent from main memory 10.
3-DATA).

The bus control circuit 20 performs priority control on requests from a plurality of peripheral control devices 16 to 18, gives bus usage rights to the prioritized peripheral control device, and receives details of requests on the ADR3-DATA line ]5. and a response circuit that outputs a response from the main memory device 10 to the common bus. The processing circuit 21 holds data between the bus control circuit 20 in the memory access control device 12 and the MEM control circuit 22, which controls access requests to the main storage device 10 and responses from the main storage device 0. It consists of a circuit and a control circuit for the holding circuit. Reference numbers 30 to 32 indicate bus control circuit 20;
Each failure detection circuit of the processing circuit 21 and the MEM control circuit 22 is shown. Gate circuit 'd@40 is fault detection circuit 30
A circuit that calculates the logical sum of the output signals of ~32, and reference numeral 41 is a circuit that analyzes the detected failure content and determines whether the analyzed content should be reported to the peripheral control devices 16 to 18 connected to the common bus. 6 Reference numeral 42 is a clock control circuit of the memory access control device 12, and the first failure report 102
It has the function of stopping the clock of the device. Reference numerals 50-52 are contained in peripheral control devices 16-18,
A monitoring timer is shown that monitors the time from outputting a main memory access request onto the bus until receiving a response from the main storage device 10 from the bus.

Next, the operation of the embodiment will be explained.

When requests from a plurality of peripheral control devices 16 to 18 are issued to the CNTL 14 on the common bus, the bus control circuit 20 performs priority control, gives the right to use the bus to the prioritized peripheral control device, and assigns the address. .

Receives detailed contents such as data from ADRS-DATA15. The peripheral control device given priority at this time sets a monitoring timer. The request accepted by the bus control circuit 20 is sent to the processing circuit 21, and when the MEM control circuit 22 is in a busy state, the request is held, and when the MEM control circuit 22 enters the reso state, the MEM
It is transferred to the EM control circuit 22. The request transferred to the MEM control circuit 22 is converted to match the request to the main storage device 10. The MEM control circuit 22 receives a response from the main storage device 10 to the request, and receives information such as read data and status. The response is transferred to the processing circuit 21 and sent to the bus control circuit 20 when the bus control circuit 20 is in the reso state. The bus control circuit 20 is A
When DRS-DATA 15 becomes reso-state,
It outputs the data and also outputs an end signal to the CNTL 14. The peripheral control device, which had set the monitoring timer in response to the above request, resets the monitoring timer after receiving the completion signal on the CNTL 14.

In the above sequence, the bus control circuit 20, the processing circuit 2
1. In the MEM control circuit 22, the failure detection circuits 30 to 32 perform a data parity check and control operation check, and when a failure is detected, it is immediately reported to the failure processing circuit 41 through the gate circuit 40. The fault processing circuit 41 analyzes the details of the fault, collects Wa, and then determines whether the fault should be reported to the peripheral control devices 15 to 17. If a report is to be made, a second failure report 101 is sent to the EATT 13 together with an end signal output from the bus control circuit 20 on the CNTL 14, and the failure is reported to the peripheral control device, and then, by the failure report 102 of the cylinder 1, A report is also sent to the central processing unit 11, and a clocking instruction is given to the clock control circuit 42. The clock control circuit 42 stops the clock of the memory access control device 12 in accordance with the instruction. By performing the failure processing described in L, the peripheral control devices 16 to 18 connected to the common bus are connected to the memory access control device 12.
Before the memory access controller 11 enters the clock stop state due to a failure, the failure of the memory access control unit 11 is known and the monitoring timer is reset.
Do soto.

[Effects of the Invention゛j As explained above, the present invention includes a fault detection circuit that detects a fault, a fault processing circuit that determines whether the fault should be reported to the peripheral control device, and a common method when the fault should be reported. By activating the EA TT on the bus, it is possible to notify the peripheral control device of a failure in the memory access control device, reset the monitoring timer set in the peripheral control device, and prevent timeouts while waiting for a response to a request. This has the effect of preventing double failures and facilitating failure analysis.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 10... Main storage device, 11... Central processing unit, 12
...Memory access control device, 13...EATT,
14...CNTL, 15...ADRS-DATA
, 16-18... Peripheral control device, 20... Bus control circuit, 21... Processing circuit, 22... MEM control circuit, 30-32... Failure detection circuit, 40... Gate circuit , 41... Failure processing circuit, 42... Clock control circuit, 50-52... Monitoring timer.

Claims (1)

[Claims] An information processing system including a main storage device, a plurality of peripheral control devices connected to a common bus, a memory access control device that collectively controls requests from the peripheral control devices, and a central processing unit. In the memory access control device, the memory access control device includes a fault detection means for detecting a fault in each circuit constituting the device, and a fault detection means that analyzes the content of the detected fault and generates a first fault notification signal to the peripheral control device. further comprising a fault processing means for generating a second fault notification signal when a fault requires reporting, and a signal stop means for stopping a clock signal in response to supply of the first fault notification signal; includes a transmission means for transmitting the second failure notification signal to the peripheral control device, and each of the plurality of peripheral devices has a transmission means for transmitting the second failure notification signal to the peripheral control device, and each of the plurality of peripheral devices has a transmission means for transmitting the second failure notification signal to the peripheral control device, and each of the plurality of peripheral devices has a transmission means for transmitting the second failure notification signal to the peripheral control device. The central processing unit includes a time monitoring unit that monitors time and issues an alarm when a certain period of time has elapsed, and is reset by the second failure notification signal, and the central processing unit includes a reception unit that receives the first failure notification signal. An information processing system characterized by: