JPS62162156A - Memory access controller - Google Patents

Abstract

PURPOSE:To facilitate the analysis of a fault by judging in a fault processing circuit to or not to report a fault to peripheral controllers in case detecting the fault, and in case of reporting, activating the EATT on a common bus to inform the peripheral controllers of the fault in a memory access controller. CONSTITUTION:A fault detecting circuits 30-32 execute the parity-check of data and the check of control action by using a bus control circuit 20, a processing circuit 21, and a MEM control circuit 22. In case of detecting a fault, it is immediately reported to the fault processing circuit 34 through a gate circuit 33. The circuit 34 analyses the content of the fault, and after editing, judges whether or not it is to be reported to the peripheral controllers 15-17. In case of reporting it, the circuit 34 issues the second fault-report 102 to an EATT 12 together with an end signal outputted from the bus control circuit 20 on a CNTL 13 to report the fault to the peripheral controllers 15-17, and thereafter issues a stop-instruction 101 to a clock control circuit 35. At the time of receiving the stop-instruction 101, the circuit 35 stops the supply of clock 103 to a memory-access controller 11.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a memory access control device.

[Conventional technology]

Conventional memory access control devices determine the priority of access requests sent from peripheral control devices onto a common bus, perform reception processing, send access requests to the main storage device, and store access requests in response to this request. Main memory access processing between the peripheral control device and the main memory device is performed by sending responses from the device onto the common bus. If a failure occurs in the memory access control device when performing this main memory access processing, after detecting the failure, determine the details of the failure,
The main memory access process was simply halted by issuing a signal such as tallock stop within the memory access control device, but no failure was reported to the peripheral control devices connected to the common bus.

[Problem that the invention seeks to solve]

The conventional memory access control device described above is connected to a common bus because when a failure occurs during main memory access processing from a peripheral control device, the process is aborted without reporting the failure status to the peripheral control device. Multiple peripheral control devices in the system will time out while waiting for the end signal from the memory access control device, and a failure will occur on the peripheral control device side as well.Furthermore, if a double failure occurs during system failure analysis, the failure analysis will be difficult. The problem is that it is not easy to do.

Means for Solving Problem 1] The device of the present invention is a memory access control device that collectively controls main memory access from a plurality of peripheral control devices.
a fault detection means for detecting a fault in each circuit constituting the memory access control device; and a fault detection means for analyzing the content of the detected fault and generating a first fault notification signal, when the fault requires reporting to the peripheral control device. Furthermore, a failure processing means for generating a second failure notification signal, a signal transmission means for transmitting the second failure notification signal to the peripheral control device, and a first failure notification signal.
and signal stopping means for stopping the clock signal in response to the supply of the failure notification signal.

[Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Reference numeral 10 in the figure is a main memory, reference numeral 11 is a memory access control device which is an embodiment of the present invention, and reference numeral 1 is
Reference numeral 2 indicates a signal line (hereinafter not referred to as EATT) indicating a failure state of the memory access control device 11, and reference numeral 13 indicates a control line for transmitting and receiving request signals and termination signals to and from the peripheral control devices 15 to 17. (hereinafter referred to as CNTl-).

Reference numeral 14 is an address/data line (hereinafter referred to as ADR9-DATA) indicating a bus for address signals and data for requests from the peripheral control units 15-17, or data sent from the main memory 10. Hass control circuit 2
0 performs priority control of requests from multiple peripheral control devices 15 to 17, gives priority to the /:2 peripheral control devices, gives the right to use the bus, and connects the circuit that receives requests on the ADR9/DATA line 14 and the common bus. and a response circuit that outputs a response from the main storage device 10. The processing circuit 21 includes a bus control circuit 20 in the memory access control device 11 and a main storage device 10.
ME that controls requests to and responses from the main storage device 10
It consists of a data holding circuit with respect to the M control circuit 22 and a control circuit for the holding circuit. Reference numbers 30-32
are failure detection circuits of the bus control circuit 20, the processing circuit 21, and the MEM control circuit 22, respectively. Gate circuit 33
Reference numeral 34 is a circuit that takes the logical sum of the output signals of the fault detection circuits 30 to 32, and a reference numeral 34 analyzes the detected fault content and determines whether the analysis content should be reported to the peripheral control devices 15 to 17 connected to the common bus. This is a circuit that does this. Reference numeral 35 is a clock control circuit of the memory access control device 11, which has a function of stopping the clock of the device in response to a stop instruction 101.

Next, the operation of the embodiment will be explained.

Is it an access request from multiple peripheral control devices 15 to 17?
When the data is sent to the CNTL 13 on the common bus, the bus control circuit 20 performs priority control and then gives the right to use the bus to the prioritized peripheral control device, and receives detailed contents such as addresses and data from the common bus. Next, the accepted request is sent to the processing circuit 21. If the MEM control circuit 22 is in a busy state, the request is held, and when the MEM control circuit 22 is in a busy state, it is sent to the processing circuit 21.
It is transferred to the control circuit 22. The request transferred to the MEM control circuit 22 is converted to match the request to the main storage device 10 and transferred. The MEM control circuit 22 receives a response from the main storage device 10 to the request, and receives information such as read data and status. The response is transferred to the processing circuit 21 and sent to the bus control circuit 20 when the bus control circuit 20 is in the reso state. The bus control circuit 20 outputs a response to ADR3-DA'r'A14 when ADR3-DATA14 enters the reso state, and
CNTL13'\Outputs end signal.

In the above sequence, the bus control circuit 20, the processing circuit 2
1. In the MEM control circuit 22, the failure detection circuits 30 to 32 perform a data parity check and a control wiring check, and when a failure is detected, they immediately report it to the failure processing circuit 34 through the data I-circuit 33. Failure processing circuit 34
analyzes the content of the fault, and after editing, determines whether the fault should be reported to the peripheral control devices 15-17. If a report is to be made, a failure notification signal 102 is sent to the EAT "I" 12 along with a termination signal output from the bus control circuit 20 on the CNTL 13, the failure is reported to the peripheral control devices 15 to 17, and then the clock control circuit 35 A stop instruction 101 is issued to. Upon receiving the stop instruction 101, the clock control circuit 35 stops supplying the clock 103 to the memory access control device 11.

In this embodiment, by performing the above fault processing, the peripheral control devices 15 to 17 connected to the common bus can access memory by performing fault processing for the peripheral control devices 15 to 17 connected to the common bus. The failure of the memory access control device 11 is known before the control device 11 enters the clock stop state due to the failure.

〔Effect of the invention〕

As explained above, in the present invention, when a fault is detected by the fault detection circuit, the fault processing circuit determines whether the fault should be reported to the peripheral control device, and if the fault should be reported, the common bus "EATT" is Activation has the effect of informing the peripheral control device of a failure in the memory access control device, preventing double failures such as timeouts while waiting for a response to a request in the peripheral control device, and facilitating failure analysis.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 10... Main memory device, 11... Memory access control device, I2... EATT, 13... CNTL, 14
... ADR3-DATA, 15-17... Peripheral control device, 20... Bus control circuit, 21... Processing circuit,
22... MEM control circuit, 30-32... Fault detection circuit, 33... Gate circuit, 34... Fault processing circuit, 35... Clock control circuit. one

Claims (1)

[Scope of Claims] A memory access control device that collectively controls main memory access from a plurality of peripheral control devices, comprising: a fault detection means for detecting a fault in each circuit constituting the memory access control device; a fault processing means that analyzes the details of a fault, generates a first fault notification signal, and further generates a second fault notification signal when a fault requires a report to the peripheral control device; A memory access control device comprising: signal transmission means for transmitting a signal to a peripheral control device; and signal stop means for stopping a clock signal in response to supply of the first failure notification signal.