JP2507969B2 - Parity error detection method test method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method for parity error detection means, and more particularly to a test method for parity error detection means in bus crossing means of a duplex processor.

[0002]

2. Description of the Related Art In a bus crossing means of a dual processor, a method for testing the normality of a means for applying a parity to a crossing signal line and detecting a parity error is conventionally controlled by firmware from an instruction from a CPU. It requires complicated processing such as generation of pseudo parity error by the microprocessor. Moreover, at the time of test access, the procedure and restrictions for stopping the normal access for the original operation were indispensable.

[0003]

In the conventional test method of the parity error detecting means, since the microprocessor and unnecessary peripheral means other than the test function are provided, the amount of hardware increases, and the normal access is made during the test access. Therefore, there is a problem that the installed software is complicated and the development amount increases.

[0004]

The test method of the parity error detecting means of the present invention is a bus crossing means of a dual processor, which is connected to an internal bus of each processor and communicates with the other processor of the dual structure. Access determining means having a function of giving parity to normal communication between the bus crossing means and a function of distinguishing normal communication from the processor internal bus and test communication of the parity error detecting means; and a judgment result of the access judging means. A means for receiving and generating test data, a parity inverting means for giving the test data a parity that is the inverse of the normal data parity, and a decision result from the access deciding means, One of the normal communication and the test data from the parity inverting means is selected to provide the other bus of the duplex configuration. Parity error detection having a selector means for sending information to the difference means, a function for checking the parity of the information sent from the other bus crossing means and detecting an error, and a function for notifying the other bus crossing means of a parity error. And means.

[0005]

The access judging means provided in the bus crossing means judges whether the communication from the processor internal bus is the normal communication or the test communication of the parity error detecting means, and the test data is received based on the judgment result. The parity is generated and added with the inverted parity for the test, and sent as the test information to the parity error detecting means of the other bus crossing means to test the other parity error detecting means.

[0006]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a test system for a parity error detecting means according to an embodiment of the present invention. In the present embodiment, the parity error detecting means 55 of the communication performed from the bus crossing means 2 toward the bus crossing means 5 between the bus crossing means 2 and 5 of the processor of the duplex configuration which is the whole of FIG. Although the normality test will be described as an object, the same applies to the case of the parity error detecting means 25 of the communication performed from the bus crossing means 5 to the bus crossing means 2 on the contrary.

Communications sent from the CPU 1 or I / O device 3 to the CPU 4 or I / O device 6 of the other processor are input to the access determination means 21 of the bus crossing means 2 via the processor internal bus 100. . In advance, information about a specific portion of the communication content is set to have different settings for normal communication and communication for testing the parity error detecting means. When this parity error detection means test communication is received, the access determination means 21 identifies this, and the test communication data generation means 22, parity inversion means 24, and selector means 23 pass through the test communication transmission instruction signal line 201, Instruct to send test communication.

In the test communication data generating means 22, the start data of the test communication is set in advance, and the test communication data generating means 22 which has received the test communication transmission instruction,
First, the start data is output for the first test communication. After that, each time the test communication transmission instruction is received, the data is shifted to the left by one bit and transmitted, and the data is changed each time the test communication is performed.

By the test communication transmission instruction signal line 201,
Upon receiving the test communication transmission instruction, the parity inverting means 24 adds parity to the test communication data output from the test communication data generating means 22 with a polarity opposite to that of the parity to be added to the normal communication data. , To the selector means 23.

The selector means 23 normally selects the normal communication received from the access determination means 21 and transmits it to the bus crossing means 5 of the other processor which constitutes the duplex configuration. The selector 23, which has received the test communication transmission instruction through the test communication transmission instruction signal line 201, is given a parity having a polarity opposite to that of the parity given to the normal communication data received from the parity inverting means 24. The communication data for use is selected and transmitted to the bus crossing means 5 of the other processor having the duplex configuration.

The parity error detecting means 55 inside the bus crossing means 5 which has received the test communication data from the bus crossing means 2 of the other processor forming the duplex configuration checks the parity of the received data received through the bus crossing signal line 300. If it is normal, a parity error is notified to the bus crossing means 2 on the transmitting side. When the bus crossing means 2 receives the parity error notification from the bus crossing means 5 of the other processor having the duplicated configuration, the bus crossing means 2 displays the normality of the test communication. Further, when the normal end is notified although the test communication which should be a parity error is sent, the abnormality of the parity error detecting means is displayed.

It should be noted that, after the parity error detecting means test communication is received through the processor internal bus 100 until the test communication is completed by the notification of the parity error or the normal end from the other processor, the bus crossing means is not When the communication is received, the busy response is returned to the transmission source, so that the parity error is not notified to the communication other than the test communication for which a normal response is expected.

[0014]

As described above, according to the present invention, in a dual processor system, the bus crossing means for connecting to the internal bus of each processor and communicating with the other processor of the dual structure has normal communication and communication content. Parity error detecting means different from each other, access determining means for distinguishing between test communication and normal communication of the processor internal bus defined for testing, and test data is generated in response to the identification result of the access determining means. Means, a means for giving the test data parity that is the inverse of the normal data parity, and one of the communication from the processor internal bus and the test data selected in response to the identification result of the access determination means for duplication. Since it has a selector means for sending it to the other processor of the configuration, it is a microprocessor unnecessary for other than the test function. Beauty without requiring its peripheral means, since it is not necessary to stop the normal access during the test access, a small amount of hardware, easier to develop software capable of realizing a highly reliable processor system.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1, 4 CPU 2, 5 Bus crossing means 3, 6 I / O 21, 51 Access determination means 22, 52 Test communication data generation means 23, 53 Selector means 24, 54 Parity inversion means 25, 51 Parity error detection means 100 , 400 Processor internal bus 201, 501 Test communication transmission instruction signal line 202, 502 Test communication data signal line 203, 503 Normal communication data signal line 300 Bus crossing signal line

Claims (2)

(57) [Claims] 1. A function of adding parity to normal communication between bus crossing means in a bus crossing means of a duplicated processor, which is connected to an internal bus of each processor and communicates with another processor in a duplicated structure, and the inside of the processor. Access determining means having a function of distinguishing normal communication from the bus and test communication of the parity error detecting means, means for generating test data in response to the determination result of the access determining means, and the test data Parity inversion means for giving parity inverted to normal data parity, and one of the normal communication from the access determination means and the test data from the parity inversion means in response to the determination result of the access determination means. Selector means for selecting and transmitting information to the other bus crossing means of the duplex configuration, and the other bus crossing means And a parity error detecting means having a function of checking the parity of information transmitted from the device and detecting an error and a function of notifying the other bus crossing means of a parity error. Test method for parity error detection means. 2. The means for generating the test data comprises:
2. The test method of the parity error detecting means according to claim 1, further comprising a function of shifting a bit position of "1" of data and adding or deleting each time a judgment result from the access judging means is received.